diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/quick/fs/10.linux-boot/ref | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref')
13 files changed, 9038 insertions, 8892 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 59ee1a74c..af5c79ab1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2397277 # Simulator instruction rate (inst/s) -host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 68943602925 # Simulator tick rate (ticks/s) -host_mem_usage 377676 # Number of bytes of host memory used -host_seconds 27.11 # Real time elapsed on the host +host_inst_rate 2198730 # Simulator instruction rate (inst/s) +host_op_rate 2198729 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63233555824 # Simulator tick rate (ticks/s) +host_mem_usage 377528 # Number of bytes of host memory used +host_seconds 29.56 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -86,61 +86,6 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 3738723791 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed @@ -231,6 +176,61 @@ system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # n system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed +system.cpu0.committedInsts 49478313 # Number of instructions committed +system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses +system.cpu0.num_func_calls 1124639 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_fp_insts 197598 # number of float instructions +system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written +system.cpu0.num_mem_refs 12536155 # number of memory refs +system.cpu0.num_load_insts 7783785 # Number of load instructions +system.cpu0.num_store_insts 4752370 # Number of store instructions +system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles +system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles +system.cpu0.Branches 7530941 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 49486454 # Class of executed instruction system.cpu0.dcache.tags.replacements 1781373 # number of replacements system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. @@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks -system.cpu0.dcache.writebacks::total 632989 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks +system.cpu0.dcache.writebacks::total 632988 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618298 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use @@ -354,6 +354,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks +system.cpu0.icache.writebacks::total 618298 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -390,61 +392,6 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 3738297607 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed @@ -518,6 +465,61 @@ system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # nu system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed +system.cpu1.committedInsts 15522157 # Number of instructions committed +system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses +system.cpu1.num_func_calls 493140 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_fp_insts 198941 # number of float instructions +system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written +system.cpu1.num_mem_refs 4961785 # number of memory refs +system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_store_insts 2112696 # Number of store instructions +system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles +system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles +system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 15525873 # Class of executed instruction system.cpu1.dcache.tags.replacements 201756 # number of replacements system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. @@ -639,6 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks +system.cpu1.icache.writebacks::total 380671 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -737,22 +741,22 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999687 # number of replacements -system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use -system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks. +system.l2c.tags.replacements 999918 # number of replacements +system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use +system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id @@ -761,62 +765,66 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 # system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365678 # Number of tag accesses -system.l2c.tags.data_accesses 46365678 # Number of data accesses -system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits -system.l2c.Writeback_hits::total 777520 # number of Writeback hits +system.l2c.tags.tag_accesses 46365909 # Number of tag accesses +system.l2c.tags.data_accesses 46365909 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits -system.l2c.overall_hits::cpu0.data 738161 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910319 # number of overall hits +system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits +system.l2c.overall_hits::cpu0.data 738156 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits +system.l2c.overall_hits::cpu1.data 185614 # number of overall hits +system.l2c.overall_hits::total 1910402 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses -system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066180 # number of overall misses -system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses +system.l2c.overall_misses::cpu1.data 12104 # number of overall misses +system.l2c.overall_misses::total 1066097 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) @@ -848,25 +856,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.882002 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -875,47 +883,47 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80913 # number of writebacks -system.l2c.writebacks::total 80913 # number of writebacks +system.l2c.writebacks::writebacks 80921 # number of writebacks +system.l2c.writebacks::total 80921 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948866 # Transaction distribution +system.membus.trans_dist::ReadResp 948782 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 122433 # Transaction distribution -system.membus.trans_dist::CleanEvict 917961 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution +system.membus.trans_dist::CleanEvict 917844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126472 # Transaction distribution -system.membus.trans_dist::ReadExResp 124247 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution +system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::ReadExResp 124222 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205834 # Request fanout histogram +system.membus.snoop_fanout::samples 2205642 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205834 # Request fanout histogram +system.membus.snoop_fanout::total 2205642 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -926,8 +934,9 @@ system.toL2Bus.trans_dist::ReadReq 7449 # Tr system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution @@ -940,17 +949,17 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5 system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083281 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram +system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083512 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram @@ -958,7 +967,7 @@ system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 34e6d6348..3a45545f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2390951 # Simulator instruction rate (inst/s) -host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72850763127 # Simulator tick rate (ticks/s) -host_mem_usage 374092 # Number of bytes of host memory used -host_seconds 25.11 # Real time elapsed on the host +host_inst_rate 2238603 # Simulator instruction rate (inst/s) +host_op_rate 2238602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68208828665 # Simulator tick rate (ticks/s) +host_mem_usage 373932 # Number of bytes of host memory used +host_seconds 26.82 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory -system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory +system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -76,61 +76,6 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3658670905 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038341 # Number of instructions committed -system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913563 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115702 # number of memory refs -system.cpu.num_load_insts 9747508 # Number of load instructions -system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles -system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles -system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064400 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed @@ -216,6 +161,61 @@ system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # nu system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.committedInsts 60038341 # Number of instructions committed +system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1484182 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913563 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 16115702 # number of memory refs +system.cpu.num_load_insts 9747508 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles +system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064400 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 60050179 # Class of executed instruction system.cpu.dcache.tags.replacements 2042728 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks -system.cpu.dcache.writebacks::total 833493 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks +system.cpu.dcache.writebacks::total 833492 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -335,19 +335,21 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 919605 # number of writebacks +system.cpu.icache.writebacks::total 919605 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992219 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992425 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id @@ -356,40 +358,44 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses -system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses +system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) @@ -408,16 +414,16 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -426,8 +432,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks -system.cpu.l2cache.writebacks::total 74334 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks +system.cpu.l2cache.writebacks::total 74365 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -439,8 +445,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution @@ -450,21 +457,21 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1075788 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1075994 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -563,42 +570,42 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7184 # Transaction distribution -system.membus.trans_dist::ReadResp 948374 # Transaction distribution +system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115846 # Transaction distribution -system.membus.trans_dist::CleanEvict 917156 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116946 # Transaction distribution -system.membus.trans_dist::ReadExResp 116946 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution +system.membus.trans_dist::CleanEvict 917027 # Transaction distribution +system.membus.trans_dist::UpgradeReq 147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 116931 # Transaction distribution +system.membus.trans_dist::ReadExResp 116931 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2150005 # Request fanout histogram +system.membus.snoop_fanout::samples 2149824 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2150005 # Request fanout histogram +system.membus.snoop_fanout::total 2149824 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 69fe46592..ce1bb41a0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982585 # Number of seconds simulated -sim_ticks 1982585357000 # Number of ticks simulated -final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.977709 # Number of seconds simulated +sim_ticks 1977709274000 # Number of ticks simulated +final_tick 1977709274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1043358 # Simulator instruction rate (inst/s) -host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33918612914 # Simulator tick rate (ticks/s) -host_mem_usage 377952 # Number of bytes of host memory used -host_seconds 58.45 # Real time elapsed on the host -sim_insts 60985541 # Number of instructions simulated -sim_ops 60985541 # Number of ops (including micro ops) simulated +host_inst_rate 1549555 # Simulator instruction rate (inst/s) +host_op_rate 1549555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51561372502 # Simulator tick rate (ticks/s) +host_mem_usage 334884 # Number of bytes of host memory used +host_seconds 38.36 # Real time elapsed on the host +sim_insts 59435338 # Number of instructions simulated +sim_ops 59435338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 23907392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 165888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1310592 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory -system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26079168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 165888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 860224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7747712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7747712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 373553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20478 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407445 # Number of read requests accepted -system.physmem.writeReqs 120910 # Number of write requests accepted -system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407487 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 351081 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12088426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 83879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 662682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13186553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 351081 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 83879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434960 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3917518 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3917518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 351081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12088426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 83879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 662682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17104071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407487 # Number of read requests accepted +system.physmem.writeReqs 121058 # Number of write requests accepted +system.physmem.readBursts 407487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121058 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26071296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue +system.physmem.bytesWritten 7746112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26079168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7747712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25232 # Per bank write bursts -system.physmem.perBankRdBursts::1 25377 # Per bank write bursts -system.physmem.perBankRdBursts::2 25433 # Per bank write bursts -system.physmem.perBankRdBursts::3 24853 # Per bank write bursts -system.physmem.perBankRdBursts::4 25156 # Per bank write bursts -system.physmem.perBankRdBursts::5 25421 # Per bank write bursts -system.physmem.perBankRdBursts::6 25501 # Per bank write bursts -system.physmem.perBankRdBursts::7 25341 # Per bank write bursts -system.physmem.perBankRdBursts::8 25248 # Per bank write bursts -system.physmem.perBankRdBursts::9 25578 # Per bank write bursts -system.physmem.perBankRdBursts::10 25745 # Per bank write bursts -system.physmem.perBankRdBursts::11 25922 # Per bank write bursts -system.physmem.perBankRdBursts::12 25991 # Per bank write bursts -system.physmem.perBankRdBursts::13 25558 # Per bank write bursts -system.physmem.perBankRdBursts::14 25312 # Per bank write bursts -system.physmem.perBankRdBursts::15 25655 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7774 # Per bank write bursts -system.physmem.perBankWrBursts::2 7467 # Per bank write bursts -system.physmem.perBankWrBursts::3 6887 # Per bank write bursts -system.physmem.perBankWrBursts::4 7102 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7434 # Per bank write bursts -system.physmem.perBankWrBursts::7 7145 # Per bank write bursts -system.physmem.perBankWrBursts::8 7156 # Per bank write bursts -system.physmem.perBankWrBursts::9 7306 # Per bank write bursts -system.physmem.perBankWrBursts::10 7741 # Per bank write bursts -system.physmem.perBankWrBursts::11 8153 # Per bank write bursts -system.physmem.perBankWrBursts::12 8257 # Per bank write bursts -system.physmem.perBankWrBursts::13 7909 # Per bank write bursts -system.physmem.perBankWrBursts::14 7539 # Per bank write bursts -system.physmem.perBankWrBursts::15 7820 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 306935 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25840 # Per bank write bursts +system.physmem.perBankRdBursts::1 26009 # Per bank write bursts +system.physmem.perBankRdBursts::2 26271 # Per bank write bursts +system.physmem.perBankRdBursts::3 25739 # Per bank write bursts +system.physmem.perBankRdBursts::4 24904 # Per bank write bursts +system.physmem.perBankRdBursts::5 25588 # Per bank write bursts +system.physmem.perBankRdBursts::6 25282 # Per bank write bursts +system.physmem.perBankRdBursts::7 25179 # Per bank write bursts +system.physmem.perBankRdBursts::8 24919 # Per bank write bursts +system.physmem.perBankRdBursts::9 24911 # Per bank write bursts +system.physmem.perBankRdBursts::10 25224 # Per bank write bursts +system.physmem.perBankRdBursts::11 25266 # Per bank write bursts +system.physmem.perBankRdBursts::12 25817 # Per bank write bursts +system.physmem.perBankRdBursts::13 25627 # Per bank write bursts +system.physmem.perBankRdBursts::14 25517 # Per bank write bursts +system.physmem.perBankRdBursts::15 25271 # Per bank write bursts +system.physmem.perBankWrBursts::0 8076 # Per bank write bursts +system.physmem.perBankWrBursts::1 7966 # Per bank write bursts +system.physmem.perBankWrBursts::2 8289 # Per bank write bursts +system.physmem.perBankWrBursts::3 8035 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7755 # Per bank write bursts +system.physmem.perBankWrBursts::6 7349 # Per bank write bursts +system.physmem.perBankWrBursts::7 7181 # Per bank write bursts +system.physmem.perBankWrBursts::8 6971 # Per bank write bursts +system.physmem.perBankWrBursts::9 7004 # Per bank write bursts +system.physmem.perBankWrBursts::10 7220 # Per bank write bursts +system.physmem.perBankWrBursts::11 7086 # Per bank write bursts +system.physmem.perBankWrBursts::12 7863 # Per bank write bursts +system.physmem.perBankWrBursts::13 7891 # Per bank write bursts +system.physmem.perBankWrBursts::14 7798 # Per bank write bursts +system.physmem.perBankWrBursts::15 7404 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 21 # Number of times write queue was full causing retry -system.physmem.totGap 1982577992500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1977655892500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407445 # Read request sizes (log2) +system.physmem.readPktSize::6 407487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120910 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121058 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,177 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 65 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 497.292884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.084252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.105473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16504 24.27% 24.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12590 18.51% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5294 7.78% 50.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3182 4.68% 55.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2479 3.65% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4294 6.31% 65.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1483 2.18% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2078 3.06% 70.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20099 29.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 68003 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.144069 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2865.262786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5418 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads -system.physmem.totQLat 2792890500 # Total ticks spent queuing -system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5421 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5421 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.006479 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.134399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4779 88.16% 88.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 22 0.41% 88.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.42% 88.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 175 3.23% 92.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 9 0.17% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.46% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 50 0.92% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.04% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.24% 94.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.35% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.11% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.15% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.04% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.41% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.37% 95.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 34 0.63% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.04% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 2.97% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.06% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.11% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.09% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.06% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 16 0.30% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5421 # Writes before turning the bus around for reads +system.physmem.totQLat 2796894000 # Total ticks spent queuing +system.physmem.totMemAccLat 10434969000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6865.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25615.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 363877 # Number of row buffer hits during reads -system.physmem.writeRowHits 96767 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes -system.physmem.avgGap 3752359.67 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.011108 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states -system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 363824 # Number of row buffer hits during reads +system.physmem.writeRowHits 96570 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.77 # Row buffer hit rate for writes +system.physmem.avgGap 3741698.23 # Average gap between requests +system.physmem.pageHitRate 87.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 262483200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 143220000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1597533600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 400438080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73962048600 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1121745657750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1327285621230 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.123235 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1865834845500 # Time in different power states +system.physmem_0.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 45832914500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.118945 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states -system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states +system.physmem_1.actEnergy 251619480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137292375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579905600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383855760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73584887580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1122076500750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1327188301545 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.074027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1866389529250 # Time in different power states +system.physmem_1.memoryStateTime::REF 66040000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45278230750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416955 # DTB read hits +system.cpu0.dtb.read_hits 5727753 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004564 # DTB write hits +system.cpu0.dtb.write_hits 3981122 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12421519 # DTB hits +system.cpu0.dtb.data_hits 9708875 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482641 # ITB hits +system.cpu0.itb.fetch_hits 3124468 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486512 # ITB accesses +system.cpu0.itb.fetch_accesses 3128339 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -341,91 +351,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851833 # number of cpu cycles simulated +system.cpu0.numCycles 3955086246 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47325532 # Number of instructions committed -system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses -system.cpu0.num_func_calls 1185742 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43895499 # number of integer instructions -system.cpu0.num_fp_insts 207106 # number of float instructions -system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written -system.cpu0.num_mem_refs 12461430 # number of memory refs -system.cpu0.num_load_insts 7443904 # Number of load instructions -system.cpu0.num_store_insts 5017526 # Number of store instructions -system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles -system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles -system.cpu0.Branches 7135463 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction -system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47334130 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4843 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 129735 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 41337 38.33% 38.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.12% 38.45% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1972 1.83% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 64391 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107848 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 40894 48.75% 48.75% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1972 2.35% 51.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% 51.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 40877 48.73% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 83891 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1907093255000 96.44% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94033500 0.00% 96.44% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 783814000 0.04% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 14262000 0.00% 96.48% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 69557728500 3.52% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1977543093000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.989283 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.634825 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777863 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -457,124 +412,179 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147613 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches +system.cpu0.kern.callpal::wripir 93 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 1998 1.74% 1.82% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 1.87% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.87% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101884 88.63% 90.50% # number of callpals executed +system.cpu0.kern.callpal::rdps 6548 5.70% 96.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.21% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.21% # number of callpals executed +system.cpu0.kern.callpal::rti 3843 3.34% 99.55% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.33% 99.88% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.12% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 114960 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5413 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1281 -system.cpu0.kern.mode_good::user 1281 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.236837 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.382972 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1972827474000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3894173000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3027 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1172695 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits -system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency +system.cpu0.kern.swap_context 1999 # number of times the context was actually changed +system.cpu0.committedInsts 36251265 # Number of instructions committed +system.cpu0.committedOps 36251265 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33727452 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 135758 # Number of float alu accesses +system.cpu0.num_func_calls 876834 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248905 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33727452 # number of integer instructions +system.cpu0.num_fp_insts 135758 # number of float instructions +system.cpu0.num_int_register_reads 46333717 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25193797 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 65701 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 66416 # number of times the floating registers were written +system.cpu0.num_mem_refs 9739707 # number of memory refs +system.cpu0.num_load_insts 5749561 # Number of load instructions +system.cpu0.num_store_insts 3990146 # Number of store instructions +system.cpu0.num_idle_cycles 3736968981.972937 # Number of idle cycles +system.cpu0.num_busy_cycles 218117264.027063 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944851 # Percentage of idle cycles +system.cpu0.Branches 5398761 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1979626 5.46% 5.46% # Class of executed instruction +system.cpu0.op_class::IntAlu 23753610 65.51% 70.97% # Class of executed instruction +system.cpu0.op_class::IntMult 36908 0.10% 71.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 22960 0.06% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.14% # Class of executed instruction +system.cpu0.op_class::MemRead 5882505 16.22% 87.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 3995282 11.02% 98.38% # Class of executed instruction +system.cpu0.op_class::IprAccess 587316 1.62% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 36259863 # Class of executed instruction +system.cpu0.dcache.tags.replacements 822072 # number of replacements +system.cpu0.dcache.tags.tagsinuse 480.504845 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 8885001 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822496 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.802485 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.504845 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.938486 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 39682070 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 39682070 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5000163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5000163 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3644006 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3644006 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117543 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117543 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123259 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 123259 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8644169 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8644169 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8644169 # number of overall hits +system.cpu0.dcache.overall_hits::total 8644169 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 612538 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 612538 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 209263 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 209263 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6851 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6851 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 636 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 636 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 821801 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 821801 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 821801 # number of overall misses +system.cpu0.dcache.overall_misses::total 821801 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38657814000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 38657814000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 14917066000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 14917066000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 93675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8969500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 8969500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 53574880000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 53574880000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 53574880000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5612701 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3853269 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 124394 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 123895 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9465970 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9465970 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.109134 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054308 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.054308 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055075 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055075 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005133 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005133 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086816 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086816 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086816 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086816 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 63110.882917 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 63110.882917 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,126 +593,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks -system.cpu0.dcache.writebacks::total 672708 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 366665 # number of writebacks +system.cpu0.dcache.writebacks::total 366665 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 612538 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 612538 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 209263 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 209263 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6851 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 636 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 821801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 821801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 821801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 821801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4814 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8193 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 13007 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38045276000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38045276000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 14707803000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 14707803000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86824500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86824500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 8333500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 8333500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 52753079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 52753079000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 52753079000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 52753079000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1072338000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1072338000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1840159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1840159000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2912497000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2912497000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.109134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.109134 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054308 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055075 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005133 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086816 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086816 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 62110.882917 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 62110.882917 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 70283.819882 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70283.819882 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12673.259378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.259378 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13102.987421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13102.987421 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222754.050686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222754.050686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 224601.367021 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224601.367021 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686863 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 490042 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.476572 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 35769214 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490554 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 72.915956 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.476572 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989212 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989212 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 296 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits -system.cpu0.icache.overall_hits::total 46646633 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses -system.cpu0.icache.overall_misses::total 687497 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 36750512 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 36750512 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 35769214 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35769214 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35769214 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35769214 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35769214 # number of overall hits +system.cpu0.icache.overall_hits::total 35769214 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490649 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490649 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490649 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490649 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490649 # number of overall misses +system.cpu0.icache.overall_misses::total 490649 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7808174000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7808174000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7808174000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7808174000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7808174000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7808174000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36259863 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36259863 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36259863 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36259863 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36259863 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36259863 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013531 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013531 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013531 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013531 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013531 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15913.971087 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +721,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 490042 # number of writebacks +system.cpu0.icache.writebacks::total 490042 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490649 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490649 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7317525000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7317525000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7317525000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013531 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013531 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2508569 # DTB read hits +system.cpu1.dtb.read_hits 3965416 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1828737 # DTB write hits +system.cpu1.dtb.write_hits 2725894 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4337306 # DTB hits +system.cpu1.dtb.data_hits 6691310 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1989876 # ITB hits +system.cpu1.itb.fetch_hits 2218092 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991092 # ITB accesses +system.cpu1.itb.fetch_accesses 2219308 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +780,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965170714 # number of cpu cycles simulated +system.cpu1.numCycles 3955418548 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13660009 # Number of instructions committed -system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses -system.cpu1.num_func_calls 429702 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12598388 # number of integer instructions -system.cpu1.num_fp_insts 178445 # number of float instructions -system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written -system.cpu1.num_mem_refs 4361445 # number of memory refs -system.cpu1.num_load_insts 2523214 # Number of load instructions -system.cpu1.num_store_insts 1838231 # Number of store instructions -system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles -system.cpu1.Branches 1945174 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction -system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction -system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13663373 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3977 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 108865 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 40405 40.60% 40.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 1.98% 42.57% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 93 0.09% 42.67% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 57058 57.33% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 99522 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 39471 48.79% 48.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 2.43% 51.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 93 0.11% 51.33% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 39378 48.67% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 80908 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1902956585000 96.22% 96.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 734079500 0.04% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 70449000 0.00% 96.26% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 73947425500 3.74% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1977708539000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.690140 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.812966 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -864,124 +821,179 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2247 2.20% 2.22% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.22% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 94014 91.97% 94.20% # number of callpals executed +system.cpu1.kern.callpal::rdps 2296 2.25% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3448 3.37% 99.82% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.13% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73942 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 911 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 447 -system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 102224 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2738 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2043 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 518 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 55 +system.cpu1.kern.mode_switch_good::kernel 0.189189 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2065 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 173710 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.026921 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.197559 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 70603027000 3.57% 3.57% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1708148000 0.09% 3.66% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1905397362000 96.34% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2248 # number of times the context was actually changed +system.cpu1.committedInsts 23184073 # Number of instructions committed +system.cpu1.committedOps 23184073 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 21342235 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 193178 # Number of float alu accesses +system.cpu1.num_func_calls 708348 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2510657 # number of instructions that are conditional controls +system.cpu1.num_int_insts 21342235 # number of integer instructions +system.cpu1.num_fp_insts 193178 # number of float instructions +system.cpu1.num_int_register_reads 29195011 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15673593 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 100176 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 102374 # number of times the floating registers were written +system.cpu1.num_mem_refs 6716060 # number of memory refs +system.cpu1.num_load_insts 3980976 # Number of load instructions +system.cpu1.num_store_insts 2735084 # Number of store instructions +system.cpu1.num_idle_cycles 3859200221.998049 # Number of idle cycles +system.cpu1.num_busy_cycles 96218326.001951 # Number of busy cycles +system.cpu1.not_idle_fraction 0.024326 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.975674 # Percentage of idle cycles +system.cpu1.Branches 3468812 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1369332 5.91% 5.91% # Class of executed instruction +system.cpu1.op_class::IntAlu 14462485 62.37% 68.28% # Class of executed instruction +system.cpu1.op_class::IntMult 32790 0.14% 68.42% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 15288 0.07% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 68.49% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.49% # Class of executed instruction +system.cpu1.op_class::MemRead 4085109 17.62% 86.11% # Class of executed instruction +system.cpu1.op_class::MemWrite 2736216 11.80% 97.91% # Class of executed instruction +system.cpu1.op_class::IprAccess 484231 2.09% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 23187437 # Class of executed instruction +system.cpu1.dcache.tags.replacements 637928 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.645459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6059697 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 638440 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.491412 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 77414441500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.645459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.952433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.952433 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits -system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses -system.cpu1.dcache.overall_misses::total 189082 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 27453473 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27453473 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3383453 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3383453 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2527183 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2527183 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 67642 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 67642 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79428 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79428 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5910636 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5910636 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5910636 # number of overall hits +system.cpu1.dcache.overall_hits::total 5910636 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 511536 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 511536 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 119772 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 119772 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12967 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12967 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 653 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 653 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 631308 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 631308 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 631308 # number of overall misses +system.cpu1.dcache.overall_misses::total 631308 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6625803500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6625803500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3933748500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3933748500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 167428500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 167428500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 10386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 10386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 10559552000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 10559552000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 10559552000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 10559552000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3894989 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3894989 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2646955 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2646955 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 80609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 80609 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 80081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6541944 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6541944 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6541944 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6541944 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131332 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.131332 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045249 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.045249 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160863 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160863 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.008154 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.008154 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.096502 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.096502 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.096502 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.096502 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16726.466321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16726.466321 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,128 +1002,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks -system.cpu1.dcache.writebacks::total 119711 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 496006 # number of writebacks +system.cpu1.dcache.writebacks::total 496006 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 511536 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 119772 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12967 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 653 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 631308 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 631308 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 631308 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2385 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4228 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6613 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 6114267500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3813976500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 154461500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 9733500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9928244000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9928244000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9928244000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9928244000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520029500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520029500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 992921500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 992921500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1512951000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1512951000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.131332 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045249 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160863 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.008154 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.096502 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.096502 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331160 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 510167 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.053321 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22676720 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 510679 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.405037 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 117353975500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.053321 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968854 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.968854 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits -system.cpu1.icache.overall_hits::total 13331662 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses -system.cpu1.icache.overall_misses::total 331712 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 23698156 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 23698156 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 22676720 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22676720 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22676720 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22676720 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22676720 # number of overall hits +system.cpu1.icache.overall_hits::total 22676720 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510718 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510718 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510718 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510718 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510718 # number of overall misses +system.cpu1.icache.overall_misses::total 510718 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7116614500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7116614500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7116614500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7116614500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23187438 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23187438 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23187438 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23187438 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23187438 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022026 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022026 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022026 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022026 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022026 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13934.528448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1120,30 +1132,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 510167 # number of writebacks +system.cpu1.icache.writebacks::total 510167 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 510718 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 510718 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 510718 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 510718 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 510718 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6605896500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6605896500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6605896500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022026 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022026 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022026 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1157,110 +1171,110 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7379 # Transaction distribution -system.iobus.trans_dist::ReadResp 7379 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53973 # Transaction distribution +system.iobus.trans_dist::WriteResp 53973 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39240 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 68786 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2730426 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11275500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 391000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6042000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 211500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 130500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215040242 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26819000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41954000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.491123 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1769281205000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.491123 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030695 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030695 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375561 # Number of tag accesses +system.iocache.tags.data_accesses 375561 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses +system.iocache.ReadReq_misses::total 177 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22195883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22195883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429420359 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5429420359 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22195883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22195883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22195883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22195883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1269,40 +1283,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125400.468927 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125400.468927 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.250000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41522 # number of writebacks +system.iocache.writebacks::total 41522 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13345883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13345883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351820359 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13345883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13345883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13345883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1311,195 +1325,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341926 # number of replacements -system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use -system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906123 # Number of tag accesses -system.l2c.tags.data_accesses 35906123 # Number of data accesses -system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits -system.l2c.Writeback_hits::total 792419 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48625 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172720 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674900 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 330771 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005671 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659420 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113743 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 330771 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162368 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951554 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674900 # number of overall hits -system.l2c.overall_hits::cpu0.data 783515 # number of overall hits -system.l2c.overall_hits::cpu1.inst 330771 # number of overall hits -system.l2c.overall_hits::cpu1.data 162368 # number of overall hits -system.l2c.overall_hits::total 1951554 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1808 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 925 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 929 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1854 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7864 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122834 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12571 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 940 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13511 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271540 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 337 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271877 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12571 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 940 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8201 # number of demand (read+write) misses -system.l2c.demand_misses::total 408222 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12571 # number of overall misses -system.l2c.overall_misses::cpu0.data 386510 # number of overall misses -system.l2c.overall_misses::cpu1.inst 940 # number of overall misses -system.l2c.overall_misses::cpu1.data 8201 # number of overall misses -system.l2c.overall_misses::total 408222 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3901500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 36480500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 40382000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3643000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1056500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4699500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 14617384500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1036956000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15654340500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1651627500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 124696500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1776324000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33670754500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 43654000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 33714408500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1651627500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 48288139000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 124696500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1080610000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 51145073000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1651627500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 48288139000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 124696500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1080610000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 51145073000 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 792419 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 792419 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3153 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2365 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5518 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 964 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 953 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239065 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 56489 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295554 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 687471 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 331711 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019182 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 930960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 114080 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1045040 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687471 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1170025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 331711 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 170569 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359776 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687471 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1170025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 331711 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 170569 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359776 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941009 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764482 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.865350 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.959544 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974816 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.967136 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.480915 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.139213 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415606 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018286 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002834 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013257 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291677 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002954 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260159 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.330343 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002834 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.048080 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172992 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.330343 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002834 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.048080 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172992 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1314.964611 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20177.267699 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 8456.963351 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3938.378378 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1137.244349 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2534.789644 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127140.858485 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131861.139369 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127443.057297 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131383.939225 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132655.851064 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 131472.429872 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123999.243205 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 129537.091988 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124006.107541 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 125287.399993 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131383.939225 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 124933.737808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 132655.851064 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131765.638337 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 125287.399993 # average overall miss latency +system.l2c.tags.replacements 342255 # number of replacements +system.l2c.tags.tagsinuse 65190.453062 # Cycle average of tags in use +system.l2c.tags.total_refs 3793407 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407257 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.314529 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 54971.310995 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3771.999936 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4805.186829 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1123.175084 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 518.780218 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.838796 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.073321 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.017138 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007916 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994727 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65002 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1065 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6325 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991852 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 36989627 # Number of tag accesses +system.l2c.tags.data_accesses 36989627 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 862671 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 862671 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 732220 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 732220 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 102038 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 98486 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 200524 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 479778 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 508114 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 987892 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 344131 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 495524 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 839655 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 479778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 446169 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 508114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 594010 # number of demand (read+write) hits +system.l2c.demand_hits::total 2028071 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 479778 # number of overall hits +system.l2c.overall_hits::cpu0.data 446169 # number of overall hits +system.l2c.overall_hits::cpu1.inst 508114 # number of overall hits +system.l2c.overall_hits::cpu1.data 594010 # number of overall hits +system.l2c.overall_hits::total 2028071 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2602 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3085 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 77 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 94 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 103258 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 19364 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122622 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10849 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 2603 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13452 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 270704 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1159 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271863 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 373962 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2603 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20523 # number of demand (read+write) misses +system.l2c.demand_misses::total 407937 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses +system.l2c.overall_misses::cpu0.data 373962 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2603 # number of overall misses +system.l2c.overall_misses::cpu1.data 20523 # number of overall misses +system.l2c.overall_misses::total 407937 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 3090000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2769500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 5859500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 569500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 892000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1461500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 13105172500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2555486000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 15660658500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1419877000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 342190500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1762067500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 33554759000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 151782000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 33706541000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1419877000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 46659931500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 342190500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2707268000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 51129267000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1419877000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 46659931500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 342190500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2707268000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 51129267000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 862671 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 862671 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 732220 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 732220 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2743 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 570 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3313 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 102 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 120 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 222 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 205296 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 117850 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 323146 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 490627 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 510717 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1001344 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 614835 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 496683 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1111518 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 490627 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 820131 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 510717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 614533 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2436008 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 490627 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 820131 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 510717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 614533 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2436008 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948596 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847368 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.931180 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.754902 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.783333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.770270 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.502971 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.164311 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.379463 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.022113 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005097 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013434 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.440287 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.244587 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.022113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.455978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005097 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.033396 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.167461 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.022113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.455978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005097 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.033396 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.167461 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1187.548040 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5733.954451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1899.351702 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7396.103896 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9489.361702 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8546.783626 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126916.776424 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131970.977071 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127714.916573 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130876.301963 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131460.046101 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 130989.258103 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123953.687422 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130959.447800 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 123983.554217 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 125336.184264 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 125336.184264 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1508,247 +1526,248 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79390 # number of writebacks -system.l2c.writebacks::total 79390 # number of writebacks +system.l2c.writebacks::writebacks 79536 # number of writebacks +system.l2c.writebacks::total 79536 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 324 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 324 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2967 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1808 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4775 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 925 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 929 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1854 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114970 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7864 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122834 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12571 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 929 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13500 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271540 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 337 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271877 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12571 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386510 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 929 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8201 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408211 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12571 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386510 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 929 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8201 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408211 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7204 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14131 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21335 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 212307500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 129803000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 342110500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 65706500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 66436000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 132142500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13467684500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958316000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14426000500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1525917500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 114051500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1639969000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30955354500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 40284000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 30995638500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1525917500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 44423039000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 114051500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 998600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 47061608000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1525917500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 44423039000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 114051500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 998600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 47061608000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1400094000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22239000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1422333000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2192043000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 708908500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2900951500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3592137000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731147500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4323284500 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2602 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3085 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 77 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 103258 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 19364 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122622 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10849 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2592 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13441 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 270704 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1159 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271863 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10849 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 373962 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2592 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 20523 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407926 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 10849 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 373962 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2592 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 20523 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407926 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 12421 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 19620 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186370500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34557500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 220928000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5513500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6719500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 12233000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 12072592500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2361846000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 14434438500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1311387000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 314915500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1626302500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30847719000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 140192000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 30987911000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1311387000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 42920311500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 314915500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2502038000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 47048652000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1311387000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 42920311500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 314915500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2502038000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 47048652000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1012133000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 490208000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1502341000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1745847000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 944283500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2690130500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2757980000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1434491500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4192471500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948596 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847368 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.931180 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.754902 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.783333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502971 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.164311 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.379463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013423 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.440287 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244587 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167457 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167457 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7204 # Transaction distribution -system.membus.trans_dist::ReadResp 292756 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::Writeback 120910 # Transaction distribution -system.membus.trans_dist::CleanEvict 262059 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution -system.membus.trans_dist::ReadExReq 123180 # Transaction distribution -system.membus.trans_dist::ReadExResp 122316 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292680 # Transaction distribution +system.membus.trans_dist::WriteReq 12421 # Transaction distribution +system.membus.trans_dist::WriteResp 12421 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121058 # Transaction distribution +system.membus.trans_dist::CleanEvict 261934 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4921 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1238 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3449 # Transaction distribution +system.membus.trans_dist::ReadExReq 122558 # Transaction distribution +system.membus.trans_dist::ReadExResp 122429 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22736 # Total snoops (count) -system.membus.snoop_fanout::samples 883364 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1166399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1205639 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124831 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1330470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31168512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31237298 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33895666 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3262 # Total snoops (count) +system.membus.snoop_fanout::samples 858545 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 858545 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883364 # Request fanout histogram -system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 858545 # Request fanout histogram +system.membus.reqLayer0.occupancy 36672500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323961648 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2184136804 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69798217 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4935792 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2467069 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374533 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution +system.toL2Bus.snoop_filter.hit_single_snoops 1179 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2152619 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12421 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12421 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 983748 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 732220 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 760785 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4956 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1289 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 6245 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 324079 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1001367 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1144069 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484490 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1377223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1357708 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1834010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7047307 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56740736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 76009449 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 54207360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 71099081 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 258056626 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 461903 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2920905 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.337667 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2538432 86.91% 86.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 382238 13.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2920905 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4346798496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 736191563 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1248608962 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 767009132 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 969915969 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 2decdfb20..350260732 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.941266 # Number of seconds simulated -sim_ticks 1941266487500 # Number of ticks simulated -final_tick 1941266487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.941276 # Number of seconds simulated +sim_ticks 1941275996000 # Number of ticks simulated +final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056307 # Simulator instruction rate (inst/s) -host_op_rate 1056307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36524098946 # Simulator tick rate (ticks/s) -host_mem_usage 374096 # Number of bytes of host memory used -host_seconds 53.15 # Real time elapsed on the host -sim_insts 56143021 # Number of instructions simulated -sim_ops 56143021 # Number of ops (including micro ops) simulated +host_inst_rate 1519860 # Simulator instruction rate (inst/s) +host_op_rate 1519860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52515485940 # Simulator tick rate (ticks/s) +host_mem_usage 331552 # Number of bytes of host memory used +host_seconds 36.97 # Real time elapsed on the host +sim_insts 56182743 # Number of instructions simulated +sim_ops 56182743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 848832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24855488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856512 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25705280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 848832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7407552 # Number of bytes written to this memory -system.physmem.bytes_written::total 7407552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13263 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388367 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7410752 # Number of bytes written to this memory +system.physmem.bytes_written::total 7410752 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388383 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401645 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115743 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115743 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 437257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12803749 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401598 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115793 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115793 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 435178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12804213 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13241500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 437257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3815835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3815835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 437257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12803749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13239886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 435178 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3817464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3817464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 435178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12804213 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17057335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401645 # Number of read requests accepted -system.physmem.writeReqs 115743 # Number of write requests accepted -system.physmem.readBursts 401645 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115743 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25697728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7406016 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25705280 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7407552 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17057350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401598 # Number of read requests accepted +system.physmem.writeReqs 115793 # Number of write requests accepted +system.physmem.readBursts 401598 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115793 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25694784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 7408704 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25168 # Per bank write bursts -system.physmem.perBankRdBursts::1 25510 # Per bank write bursts -system.physmem.perBankRdBursts::2 25518 # Per bank write bursts -system.physmem.perBankRdBursts::3 25527 # Per bank write bursts -system.physmem.perBankRdBursts::4 25065 # Per bank write bursts -system.physmem.perBankRdBursts::5 24960 # Per bank write bursts -system.physmem.perBankRdBursts::6 24241 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25225 # Per bank write bursts +system.physmem.perBankRdBursts::1 25628 # Per bank write bursts +system.physmem.perBankRdBursts::2 25541 # Per bank write bursts +system.physmem.perBankRdBursts::3 25494 # Per bank write bursts +system.physmem.perBankRdBursts::4 25069 # Per bank write bursts +system.physmem.perBankRdBursts::5 24955 # Per bank write bursts +system.physmem.perBankRdBursts::6 24242 # Per bank write bursts system.physmem.perBankRdBursts::7 24604 # Per bank write bursts -system.physmem.perBankRdBursts::8 25078 # Per bank write bursts -system.physmem.perBankRdBursts::9 24653 # Per bank write bursts -system.physmem.perBankRdBursts::10 25359 # Per bank write bursts -system.physmem.perBankRdBursts::11 24824 # Per bank write bursts -system.physmem.perBankRdBursts::12 24407 # Per bank write bursts -system.physmem.perBankRdBursts::13 25357 # Per bank write bursts -system.physmem.perBankRdBursts::14 25770 # Per bank write bursts -system.physmem.perBankRdBursts::15 25486 # Per bank write bursts -system.physmem.perBankWrBursts::0 7561 # Per bank write bursts -system.physmem.perBankWrBursts::1 7519 # Per bank write bursts -system.physmem.perBankWrBursts::2 7810 # Per bank write bursts -system.physmem.perBankWrBursts::3 7560 # Per bank write bursts -system.physmem.perBankWrBursts::4 7221 # Per bank write bursts -system.physmem.perBankWrBursts::5 6978 # Per bank write bursts -system.physmem.perBankWrBursts::6 6351 # Per bank write bursts -system.physmem.perBankWrBursts::7 6424 # Per bank write bursts +system.physmem.perBankRdBursts::8 25085 # Per bank write bursts +system.physmem.perBankRdBursts::9 24651 # Per bank write bursts +system.physmem.perBankRdBursts::10 25269 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24508 # Per bank write bursts +system.physmem.perBankRdBursts::13 25360 # Per bank write bursts +system.physmem.perBankRdBursts::14 25616 # Per bank write bursts +system.physmem.perBankRdBursts::15 25359 # Per bank write bursts +system.physmem.perBankWrBursts::0 7625 # Per bank write bursts +system.physmem.perBankWrBursts::1 7638 # Per bank write bursts +system.physmem.perBankWrBursts::2 7842 # Per bank write bursts +system.physmem.perBankWrBursts::3 7532 # Per bank write bursts +system.physmem.perBankWrBursts::4 7224 # Per bank write bursts +system.physmem.perBankWrBursts::5 6973 # Per bank write bursts +system.physmem.perBankWrBursts::6 6356 # Per bank write bursts +system.physmem.perBankWrBursts::7 6427 # Per bank write bursts system.physmem.perBankWrBursts::8 7248 # Per bank write bursts -system.physmem.perBankWrBursts::9 6410 # Per bank write bursts -system.physmem.perBankWrBursts::10 7207 # Per bank write bursts -system.physmem.perBankWrBursts::11 6855 # Per bank write bursts -system.physmem.perBankWrBursts::12 6980 # Per bank write bursts -system.physmem.perBankWrBursts::13 7819 # Per bank write bursts -system.physmem.perBankWrBursts::14 7982 # Per bank write bursts -system.physmem.perBankWrBursts::15 7794 # Per bank write bursts +system.physmem.perBankWrBursts::9 6409 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 6905 # Per bank write bursts +system.physmem.perBankWrBursts::12 7093 # Per bank write bursts +system.physmem.perBankWrBursts::13 7822 # Per bank write bursts +system.physmem.perBankWrBursts::14 7863 # Per bank write bursts +system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 1941254508500 # Total gap between requests +system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401645 # Read request sizes (log2) +system.physmem.readPktSize::6 401598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115743 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401513 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115793 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401467 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,114 +148,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64921 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.908104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.461658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.215984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15228 23.46% 23.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11644 17.94% 41.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4997 7.70% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2980 4.59% 53.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2446 3.77% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4228 6.51% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1452 2.24% 66.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19883 30.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64921 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5102 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.697570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2954.645683 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5099 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64941 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.747124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.189706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.049901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15359 23.65% 23.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11448 17.63% 41.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4958 7.63% 48.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3153 4.86% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4206 6.48% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1429 2.20% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19872 30.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64941 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2951.127642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5102 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.681105 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.154688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.203626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4492 88.04% 88.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 201 3.94% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 29 0.57% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.94% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 38 0.74% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 6 0.12% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.22% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 38 0.74% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 34 0.67% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 1 0.02% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 159 3.12% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 2 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 5 0.10% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 8 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5102 # Writes before turning the bus around for reads -system.physmem.totQLat 2705942000 # Total ticks spent queuing -system.physmem.totMemAccLat 10234573250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6739.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads +system.physmem.totQLat 2717940750 # Total ticks spent queuing +system.physmem.totMemAccLat 10245709500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6769.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25489.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25519.79 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -265,62 +274,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing -system.physmem.readRowHits 358859 # Number of row buffer hits during reads -system.physmem.writeRowHits 93466 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.75 # Row buffer hit rate for writes -system.physmem.avgGap 3752028.47 # Average gap between requests +system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing +system.physmem.readRowHits 358828 # Number of row buffer hits during reads +system.physmem.writeRowHits 93473 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239349600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130597500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564625400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372107520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71640444015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101913691250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302654485925 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.035450 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832853481750 # Time in different power states -system.physmem_0.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_0.actEnergy 240362640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131150250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 71531321220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1102018756500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302655548930 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.030615 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1833026995250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43583902000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43425441000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 251453160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137201625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567285200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377751600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 126793670640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72584952255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101085183500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302797497980 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.109115 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831469435000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64822940000 # Time in different power states +system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72715172175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1100980290750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302819885900 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.115269 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831298493250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 44967962500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45153943000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9058452 # DTB read hits -system.cpu.dtb.read_misses 10327 # DTB read misses +system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728858 # DTB read accesses -system.cpu.dtb.write_hits 6353129 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15411581 # DTB hits -system.cpu.dtb.data_misses 11470 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020790 # DTB accesses -system.cpu.itb.fetch_hits 4975133 # ITB hits +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4975134 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980143 # ITB accesses +system.cpu.itb.fetch_accesses 4980144 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -333,87 +342,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3882532975 # number of cpu cycles simulated +system.cpu.numCycles 3882551992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56143021 # Number of instructions committed -system.cpu.committedOps 56143021 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52016582 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482534 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6465507 # number of instructions that are conditional controls -system.cpu.num_int_insts 52016582 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71267420 # number of times the integer registers were read -system.cpu.num_int_register_writes 38489507 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15464199 # number of memory refs -system.cpu.num_load_insts 9095305 # Number of load instructions -system.cpu.num_store_insts 6368894 # Number of store instructions -system.cpu.num_idle_cycles 3584401371.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298131603.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076788 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923212 # Percentage of idle cycles -system.cpu.Branches 8418668 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199011 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36202225 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61032 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9322424 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6374975 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56154858 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212043 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74906 40.88% 40.88% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212050 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74912 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1935 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106248 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183220 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73539 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106253 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183231 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73545 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73539 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149144 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860736112500 95.85% 95.85% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 92522000 0.00% 95.86% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 746030500 0.04% 95.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79691088500 4.11% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1941265753500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1860509644500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79901062000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692145 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814016 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692169 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814033 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -452,110 +406,165 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175993 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 176004 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6835 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5160 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192944 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5907 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 +system.cpu.kern.callpal::total 192955 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5908 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323345 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323121 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392117 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48524962500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5595783500 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887145005500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390004 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.973850 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14040102 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097045 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 143374500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.973850 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999949 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999949 # Average percentage of cache occupancy +system.cpu.committedInsts 56182743 # Number of instructions committed +system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483394 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15473474 # number of memory refs +system.cpu.num_load_insts 9101503 # Number of load instructions +system.cpu.num_store_insts 6371971 # Number of store instructions +system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles +system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923062 # Percentage of idle cycles +system.cpu.Branches 8422724 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 56194576 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63112993 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63112993 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7808536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7808536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5849272 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5849272 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199252 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199252 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13657808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13657808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13657808 # number of overall hits -system.cpu.dcache.overall_hits::total 13657808 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069028 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069028 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304257 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304257 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17249 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17249 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373285 # number of overall misses -system.cpu.dcache.overall_misses::total 1373285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44750637500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17613913000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232507000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62364550500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62364550500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62364550500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8877564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6153529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200274 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199252 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15031093 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15031093 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15031093 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15031093 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120419 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049444 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086127 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091363 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091363 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091363 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091363 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41861.052751 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41861.052751 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57891.562068 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57891.562068 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13479.448084 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45412.678723 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45412.678723 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits +system.cpu.dcache.overall_hits::total 13666686 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses +system.cpu.dcache.overall_misses::total 1373670 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44770870500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44770870500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634139000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17634139000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62405009500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62405009500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62405009500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62405009500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.681715 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.681715 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57944.517100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57944.517100 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13503.652809 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45429.404078 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,120 +573,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834533 # number of writebacks -system.cpu.dcache.writebacks::total 834533 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069028 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304257 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304257 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373285 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373285 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373285 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks +system.cpu.dcache.writebacks::total 834936 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43681609500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17309656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215258000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 60991265500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 60991265500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450109500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2050243500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3500353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049444 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091363 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40861.052751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56891.562068 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12479.448084 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44412.678723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44412.678723 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.010101 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212394.436963 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211080.805644 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211080.805644 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701528500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17329811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215650500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61031339500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61031339500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.681715 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56944.517100 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12503.652809 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223140.897304 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223140.897304 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928672 # number of replacements -system.cpu.icache.tags.tagsinuse 506.358595 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55225516 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929183 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.434488 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 58555927500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.358595 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.988982 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.988982 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928920 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57084202 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57084202 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55225516 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55225516 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55225516 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55225516 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55225516 # number of overall hits -system.cpu.icache.overall_hits::total 55225516 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929343 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929343 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929343 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929343 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929343 # number of overall misses -system.cpu.icache.overall_misses::total 929343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13682743000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13682743000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13682743000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13682743000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13682743000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13682743000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56154859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56154859 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56154859 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56154859 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56154859 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56154859 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016550 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016550 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016550 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016550 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016550 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016550 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.027989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14723.027989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14723.027989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.027989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14723.027989 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits +system.cpu.icache.overall_hits::total 55264986 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses +system.cpu.icache.overall_misses::total 929591 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686380500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686380500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686380500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686380500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686380500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686380500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.013132 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14723.013132 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14723.013132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14723.013132 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,141 +695,147 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929343 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929343 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929343 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929343 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929343 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12753400000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12753400000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12753400000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016550 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016550 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016550 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016550 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.027989 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.027989 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.027989 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.027989 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 928920 # number of writebacks +system.cpu.icache.writebacks::total 928920 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.013132 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.013132 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336158 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65233.633295 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3929109 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401321 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.790440 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10607812000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54990.166282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4743.088898 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5500.378115 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.839083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.083929 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336393 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65234.360025 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115204 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 718 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3222 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 722 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37802165 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37802165 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 834533 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834533 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187442 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187442 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916060 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916060 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814318 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814318 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916060 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001760 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1917820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916060 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001760 # number of overall hits -system.cpu.l2cache.overall_hits::total 1917820 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116798 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116798 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13263 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13263 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271959 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 271959 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13263 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388757 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402020 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13263 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388757 # number of overall misses -system.cpu.l2cache.overall_misses::total 402020 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14883886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14883886000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1737439000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1737439000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33716172000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33716172000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1737439000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48600058000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50337497000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1737439000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48600058000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50337497000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 834533 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834533 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116820 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13200 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271971 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 271971 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13200 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401991 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses +system.cpu.l2cache.overall_misses::total 401991 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900273000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14900273000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727207500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727207500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719775000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719775000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1727207500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48620048000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50347255500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1727207500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48620048000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50347255500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304240 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304240 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086277 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390517 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2319840 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390517 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2319840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383901 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383901 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250359 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250359 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279577 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173296 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279577 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173296 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24615.384615 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24615.384615 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127432.712889 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127432.712889 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130998.944432 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130998.944432 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123975.202144 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123975.202144 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125211.424805 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130998.944432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125013.975311 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125211.424805 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127548.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127548.989899 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130849.053030 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130849.053030 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123982.979803 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123982.979803 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125244.733091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125244.733091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,131 +844,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74231 # number of writebacks -system.cpu.l2cache.writebacks::total 74231 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 74281 # number of writebacks +system.cpu.l2cache.writebacks::total 74281 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13263 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13263 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271959 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271959 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13263 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402020 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13263 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388757 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402020 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116820 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13200 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13200 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271971 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271971 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13200 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401991 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13200 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401991 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 922500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 922500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13715906000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13715906000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1604809000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1604809000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30996582000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30996582000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1604809000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44712488000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46317297000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1604809000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44712488000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46317297000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363484500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363484500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1939234000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1939234000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302718500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302718500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595207500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595207500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000065000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000065000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595207500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732138000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46327345500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595207500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732138000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46327345500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441222500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441222500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3502599500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3502599500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383901 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383901 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250359 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173296 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173296 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70961.538462 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70961.538462 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117432.712889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117432.712889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120998.944432 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120998.944432 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113975.202144 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113975.202144 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120998.944432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115013.975311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115211.424805 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.010101 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.010101 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200894.436963 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199162.907797 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199162.907797 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117548.989899 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120849.053030 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113982.979803 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211216.275704 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211216.275704 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4638553 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2318842 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1135 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1135 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 950299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1744757 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4203130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6990247 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142457836 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201934508 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419768 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5074727 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029056 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419996 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5070439 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4288 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5074727 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3166927500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394014500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2097540500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1003,45 +1015,45 @@ system.iobus.pkt_size_system.bridge.master::total 44588 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4773000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 371000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 212000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 131000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215085744 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 215014002 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.339381 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.339384 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774103808000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.339381 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083711 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083711 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1055,14 +1067,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21913883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21913883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5427871861 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5427871861 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21913883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21913883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21913883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21913883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21742883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1079,19 +1091,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126669.843931 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126669.843931 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130628.414059 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130628.414059 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126669.843931 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126669.843931 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1105,14 +1117,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13263883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13263883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350271861 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13263883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13263883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13263883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13092883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1121,59 +1133,59 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76669.843931 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80628.414059 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76669.843931 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76669.843931 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292325 # Transaction distribution +system.membus.trans_dist::ReadResp 292274 # Transaction distribution system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution -system.membus.trans_dist::Writeback 115743 # Transaction distribution -system.membus.trans_dist::CleanEvict 261495 # Transaction distribution -system.membus.trans_dist::UpgradeReq 132 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116679 # Transaction distribution -system.membus.trans_dist::ReadExResp 116679 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285395 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution +system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 116683 # Transaction distribution +system.membus.trans_dist::ReadExResp 116683 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139506 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297489 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499692 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33157420 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837762 # Request fanout histogram +system.membus.snoop_fanout::samples 837681 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837762 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837762 # Request fanout histogram -system.membus.reqLayer0.occupancy 30061000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837681 # Request fanout histogram +system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1285186893 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143459620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143288852 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69854947 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 14fab3b83..7875c5c7b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1159279 # Simulator instruction rate (inst/s) -host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22604281025 # Simulator tick rate (ticks/s) -host_mem_usage 628452 # Number of bytes of host memory used -host_seconds 123.16 # Real time elapsed on the host +host_inst_rate 1280554 # Simulator instruction rate (inst/s) +host_op_rate 1558869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24968967598 # Simulator tick rate (ticks/s) +host_mem_usage 628580 # Number of bytes of host memory used +host_seconds 111.49 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 6c9ee9f79..4554ab525 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,70 +4,66 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151168 # Simulator instruction rate (inst/s) -host_op_rate 1402682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21975358508 # Simulator tick rate (ticks/s) -host_mem_usage 637292 # Number of bytes of host memory used -host_seconds 127.55 # Real time elapsed on the host +host_inst_rate 1249421 # Simulator instruction rate (inst/s) +host_op_rate 1522401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23850961642 # Simulator tick rate (ticks/s) +host_mem_usage 637428 # Number of bytes of host memory used +host_seconds 117.52 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1095972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9418276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 148052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1084052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11747952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1095972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 148052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1244024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8467328 # Number of bytes written to this memory +system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8484892 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192710 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132302 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 391014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3360196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4191364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391014 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3020923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3027189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3020923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3366448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7218553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -232,6 +228,8 @@ system.cpu0.itb.accesses 97442689 # DT system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.committedInsts 95426926 # Number of instructions committed system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses @@ -289,8 +287,6 @@ system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 116882065 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 693486 # number of replacements system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. @@ -309,32 +305,32 @@ system.cpu0.dcache.tags.tag_accesses 74113887 # Nu system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145070 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses -system.cpu0.dcache.overall_misses::total 769173 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses +system.cpu0.dcache.overall_misses::total 769220 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) @@ -351,18 +347,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data 35914243 system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,8 +367,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511149 # number of writebacks -system.cpu0.dcache.writebacks::total 511149 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks +system.cpu0.dcache.writebacks::total 693486 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -422,6 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks +system.cpu0.icache.writebacks::total 1109735 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -429,131 +427,128 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252605 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3066089 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.406624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 249527 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.991654 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2731505 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265646 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59674327 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59674327 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511149 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511149 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511149 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10182 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4496 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068613 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446588 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529879 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 130 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26273 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26273 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18435 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175179 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41643 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127922 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 130 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41643 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303101 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345088 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 130 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41643 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303101 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345088 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10396 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4626 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15022 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510201 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10396 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4626 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874967 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10396 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4626 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -562,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192992 # number of writebacks -system.cpu0.l2cache.writebacks::total 192992 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks +system.cpu0.l2cache.writebacks::total 192911 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720205 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860284 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 118049 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 117943 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511149 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1264197 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395204 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5764086 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80884164 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152059908 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 522626 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4217611 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.044172 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.205599 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031417 95.59% 95.59% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 186088 4.41% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 106 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4217611 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -745,6 +740,8 @@ system.cpu1.itb.accesses 53673309 # DT system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.committedInsts 51401314 # Number of instructions committed system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses @@ -802,8 +799,6 @@ system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 65459464 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. @@ -821,32 +816,32 @@ system.cpu1.dcache.tags.tag_accesses 39751979 # Nu system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306291 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses -system.cpu1.dcache.overall_misses::total 259813 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses +system.cpu1.dcache.overall_misses::total 259811 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) @@ -883,8 +878,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120812 # number of writebacks -system.cpu1.dcache.writebacks::total 120812 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks +system.cpu1.dcache.writebacks::total 191938 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -933,6 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks +system.cpu1.icache.writebacks::total 523373 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -940,88 +937,86 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48465 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1296358 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.472151 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47555 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929623 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.929889 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15019 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 530 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9526 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4963 # Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24545002 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24545002 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120812 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120812 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634121 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.916687 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24500378 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24500378 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1913 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5534 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 121109 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 121109 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583044 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583044 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19763 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19763 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510346 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510346 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99093 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99093 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1913 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510346 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 118856 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634736 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1913 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510346 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131449 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120812 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73574 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13539 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117427 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13539 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117427 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3957 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2184 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121109 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583044 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) @@ -1030,39 +1025,39 @@ system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3957 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2184 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 766309 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3957 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2184 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1071,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32915 # number of writebacks -system.cpu1.l2cache.writebacks::total 32915 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks +system.cpu1.l2cache.writebacks::total 32818 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533423 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773258 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 88765 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 88649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 116 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120812 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 583341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776513 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2357779 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873262 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56439998 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 273409 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1745865 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.067447 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.251059 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1628228 93.26% 93.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 117521 6.73% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 116 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1745865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1218,183 +1213,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 106968 # number of replacements -system.l2c.tags.tagsinuse 62096.352232 # Cycle average of tags in use -system.l2c.tags.total_refs 248810 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167499 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.485442 # Average number of references to valid blocks. +system.l2c.tags.replacements 107037 # number of replacements +system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use +system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47767.595021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7914.071704 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4068.609194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1612.456889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 728.691105 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.728876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.120759 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024604 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.947515 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1892 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13030 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45506 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.923523 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5237373 # Number of tag accesses -system.l2c.tags.data_accesses 5237373 # Number of data accesses -system.l2c.Writeback_hits::writebacks 225907 # number of Writeback hits -system.l2c.Writeback_hits::total 225907 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 360 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 59 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17186 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28346 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76399 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11438 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11382 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 127799 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11438 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14469 # number of demand (read+write) hits -system.l2c.demand_hits::total 144985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28346 # number of overall hits -system.l2c.overall_hits::cpu0.data 90498 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11438 # number of overall hits -system.l2c.overall_hits::cpu1.data 14469 # number of overall hits -system.l2c.overall_hits::total 144985 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9985 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3298 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13283 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses +system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5183068 # Number of tag accesses +system.l2c.tags.data_accesses 5183068 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits +system.l2c.demand_hits::total 141076 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits +system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits +system.l2c.overall_hits::cpu0.data 89953 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits +system.l2c.overall_hits::cpu1.data 14891 # number of overall hits +system.l2c.overall_hits::total 141076 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1937 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152401 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16563 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11232 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2303 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1139 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31247 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16761 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11173 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1126 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16563 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2303 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16975 # number of demand (read+write) misses -system.l2c.demand_misses::total 183648 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu0.inst 16761 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147698 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16963 # number of demand (read+write) misses +system.l2c.demand_misses::total 183826 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16563 # number of overall misses -system.l2c.overall_misses::cpu0.data 147797 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2303 # number of overall misses -system.l2c.overall_misses::cpu1.data 16975 # number of overall misses -system.l2c.overall_misses::total 183648 # number of overall misses -system.l2c.Writeback_accesses::writebacks 225907 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225907 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 16761 # number of overall misses +system.l2c.overall_misses::cpu0.data 147698 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses +system.l2c.overall_misses::cpu1.data 16963 # number of overall misses +system.l2c.overall_misses::total 183826 # number of overall misses +system.l2c.WritebackDirty_accesses::writebacks 225729 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 225729 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10554 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13913 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1185 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150664 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18923 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169587 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87631 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 43 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12521 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 159046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238295 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31444 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328633 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238295 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31444 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328633 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971871 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978925 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.973613 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.927873 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966567 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.906421 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.898660 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.368812 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128174 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.167601 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090967 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.196465 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.368812 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.620227 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.167601 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.539849 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.558824 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.368812 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.620227 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.167601 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.539849 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.558824 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150419 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18969 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169388 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 82 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 41643 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87232 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12885 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 155514 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 82 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 41643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237651 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31854 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1403,51 +1390,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96112 # number of writebacks -system.l2c.writebacks::total 96112 # number of writebacks +system.l2c.writebacks::writebacks 95877 # number of writebacks +system.l2c.writebacks::total 95877 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 43997 # Transaction distribution -system.membus.trans_dist::ReadResp 75496 # Transaction distribution +system.membus.trans_dist::ReadReq 43996 # Transaction distribution +system.membus.trans_dist::ReadResp 75712 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 132302 # Transaction distribution -system.membus.trans_dist::CleanEvict 8413 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40918 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15656 # Transaction distribution -system.membus.trans_dist::ReadExReq 196047 # Transaction distribution -system.membus.trans_dist::ReadExResp 151965 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution +system.membus.trans_dist::CleanEvict 8465 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution +system.membus.trans_dist::ReadExReq 196031 # Transaction distribution +system.membus.trans_dist::ReadExResp 151891 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660257 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781641 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17933452 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18123234 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20455522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 580848 # Request fanout histogram +system.membus.snoop_fanout::samples 581009 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580848 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580848 # Request fanout histogram +system.membus.snoop_fanout::total 581009 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1489,41 +1476,41 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 874927 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 450220 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 131568 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9077 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 8809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225907 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 41761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1153838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 416020 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1569858 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685372 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45103086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180140 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1129657 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.285654 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.452250 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180208 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 807234 71.46% 71.46% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 322155 28.52% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 268 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1129657 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 8e10ef807..deec780f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1171566 # Simulator instruction rate (inst/s) -host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22843865684 # Simulator tick rate (ticks/s) -host_mem_usage 624228 # Number of bytes of host memory used -host_seconds 121.87 # Real time elapsed on the host +host_inst_rate 1269873 # Simulator instruction rate (inst/s) +host_op_rate 1545867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24760705808 # Simulator tick rate (ticks/s) +host_mem_usage 624348 # Number of bytes of host memory used +host_seconds 112.43 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.committedInsts 142772879 # Number of instructions committed system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses @@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. @@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu.icache.writebacks::total 1699214 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use @@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits @@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 182974 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram @@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 719058a40..29fa724c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,156 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871120 # Number of seconds simulated -sim_ticks 2871119862000 # Number of ticks simulated -final_tick 2871119862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871820 # Number of seconds simulated +sim_ticks 2871819744000 # Number of ticks simulated +final_tick 2871819744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 654504 # Simulator instruction rate (inst/s) -host_op_rate 791691 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14285860596 # Simulator tick rate (ticks/s) -host_mem_usage 653456 # Number of bytes of host memory used -host_seconds 200.98 # Real time elapsed on the host -sim_insts 131539806 # Number of instructions simulated -sim_ops 159111212 # Number of ops (including micro ops) simulated +host_inst_rate 897166 # Simulator instruction rate (inst/s) +host_op_rate 1085198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19602639675 # Simulator tick rate (ticks/s) +host_mem_usage 617092 # Number of bytes of host memory used +host_seconds 146.50 # Real time elapsed on the host +sim_insts 131436334 # Number of instructions simulated +sim_ops 158983282 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1136484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1250788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8185344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 157844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 581136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 673536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1155428 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1268388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8606976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151764 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 551380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345088 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11986604 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1136484 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 157844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1294328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8637696 # Number of bytes written to this memory +system.physmem.bytes_read::total 12080624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1155428 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151764 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8516928 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8655260 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8534492 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20063 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 127896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2526 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5392 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 196438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134964 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133077 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139355 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137468 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 435645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2850924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 202407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 234590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 402333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 441667 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2997046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 191997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120164 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4174888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395833 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3008476 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4206609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 402333 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2965690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3014594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3008476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2971806 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2965690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 441748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2850924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 202421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 234590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 402333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 447769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2997046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 192011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120164 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7189482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 196438 # Number of read requests accepted -system.physmem.writeReqs 139355 # Number of write requests accepted -system.physmem.readBursts 196438 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 139355 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12561984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8668288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11986604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8655260 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49183 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11406 # Per bank write bursts -system.physmem.perBankRdBursts::1 11655 # Per bank write bursts -system.physmem.perBankRdBursts::2 11752 # Per bank write bursts -system.physmem.perBankRdBursts::3 11575 # Per bank write bursts -system.physmem.perBankRdBursts::4 20585 # Per bank write bursts -system.physmem.perBankRdBursts::5 12467 # Per bank write bursts -system.physmem.perBankRdBursts::6 12095 # Per bank write bursts -system.physmem.perBankRdBursts::7 12222 # Per bank write bursts -system.physmem.perBankRdBursts::8 12044 # Per bank write bursts -system.physmem.perBankRdBursts::9 12120 # Per bank write bursts -system.physmem.perBankRdBursts::10 11627 # Per bank write bursts -system.physmem.perBankRdBursts::11 11103 # Per bank write bursts -system.physmem.perBankRdBursts::12 11588 # Per bank write bursts -system.physmem.perBankRdBursts::13 11719 # Per bank write bursts -system.physmem.perBankRdBursts::14 10853 # Per bank write bursts -system.physmem.perBankRdBursts::15 11470 # Per bank write bursts -system.physmem.perBankWrBursts::0 8250 # Per bank write bursts -system.physmem.perBankWrBursts::1 8603 # Per bank write bursts -system.physmem.perBankWrBursts::2 8782 # Per bank write bursts -system.physmem.perBankWrBursts::3 8359 # Per bank write bursts -system.physmem.perBankWrBursts::4 8401 # Per bank write bursts -system.physmem.perBankWrBursts::5 9093 # Per bank write bursts -system.physmem.perBankWrBursts::6 8866 # Per bank write bursts -system.physmem.perBankWrBursts::7 8828 # Per bank write bursts -system.physmem.perBankWrBursts::8 8708 # Per bank write bursts -system.physmem.perBankWrBursts::9 8716 # Per bank write bursts -system.physmem.perBankWrBursts::10 8411 # Per bank write bursts -system.physmem.perBankWrBursts::11 8212 # Per bank write bursts -system.physmem.perBankWrBursts::12 8400 # Per bank write bursts -system.physmem.perBankWrBursts::13 8108 # Per bank write bursts -system.physmem.perBankWrBursts::14 7766 # Per bank write bursts -system.physmem.perBankWrBursts::15 7939 # Per bank write bursts +system.physmem.bw_total::total 7178416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197908 # Number of read requests accepted +system.physmem.writeReqs 137468 # Number of write requests accepted +system.physmem.readBursts 197908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137468 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12655744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10368 # Total number of bytes read from write queue +system.physmem.bytesWritten 8547392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12080624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8534492 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 64406 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11744 # Per bank write bursts +system.physmem.perBankRdBursts::1 11857 # Per bank write bursts +system.physmem.perBankRdBursts::2 11924 # Per bank write bursts +system.physmem.perBankRdBursts::3 11590 # Per bank write bursts +system.physmem.perBankRdBursts::4 20227 # Per bank write bursts +system.physmem.perBankRdBursts::5 11881 # Per bank write bursts +system.physmem.perBankRdBursts::6 12481 # Per bank write bursts +system.physmem.perBankRdBursts::7 12857 # Per bank write bursts +system.physmem.perBankRdBursts::8 12335 # Per bank write bursts +system.physmem.perBankRdBursts::9 12711 # Per bank write bursts +system.physmem.perBankRdBursts::10 11891 # Per bank write bursts +system.physmem.perBankRdBursts::11 11251 # Per bank write bursts +system.physmem.perBankRdBursts::12 11484 # Per bank write bursts +system.physmem.perBankRdBursts::13 11698 # Per bank write bursts +system.physmem.perBankRdBursts::14 10879 # Per bank write bursts +system.physmem.perBankRdBursts::15 10936 # Per bank write bursts +system.physmem.perBankWrBursts::0 8367 # Per bank write bursts +system.physmem.perBankWrBursts::1 8665 # Per bank write bursts +system.physmem.perBankWrBursts::2 8799 # Per bank write bursts +system.physmem.perBankWrBursts::3 8189 # Per bank write bursts +system.physmem.perBankWrBursts::4 7964 # Per bank write bursts +system.physmem.perBankWrBursts::5 8309 # Per bank write bursts +system.physmem.perBankWrBursts::6 8959 # Per bank write bursts +system.physmem.perBankWrBursts::7 8936 # Per bank write bursts +system.physmem.perBankWrBursts::8 8719 # Per bank write bursts +system.physmem.perBankWrBursts::9 9048 # Per bank write bursts +system.physmem.perBankWrBursts::10 8437 # Per bank write bursts +system.physmem.perBankWrBursts::11 8181 # Per bank write bursts +system.physmem.perBankWrBursts::12 8223 # Per bank write bursts +system.physmem.perBankWrBursts::13 7876 # Per bank write bursts +system.physmem.perBankWrBursts::14 7572 # Per bank write bursts +system.physmem.perBankWrBursts::15 7309 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 2871119474000 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 2871819304000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9731 # Read request sizes (log2) +system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 186679 # Read request sizes (log2) +system.physmem.readPktSize::6 188148 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 134964 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 137894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15510 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10092 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8580 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133077 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 139055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -180,161 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 68 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.210195 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.335340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.154059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46068 52.56% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17715 20.21% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6262 7.14% 79.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3427 3.91% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2480 2.83% 86.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1647 1.88% 88.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 825 0.94% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 930 1.06% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8298 9.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87652 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6626 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.622698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 552.814463 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6624 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.362371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.946957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.393854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46305 52.93% 52.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17523 20.03% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6069 6.94% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3389 3.87% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 2.84% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1521 1.74% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 858 0.98% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 952 1.09% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8385 9.58% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87485 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6517 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.342949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 586.244331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6515 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6626 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.440990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.878741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.359150 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5426 81.89% 81.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 462 6.97% 88.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 72 1.09% 89.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 157 2.37% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.48% 92.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 2.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.62% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.26% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.39% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 21 0.32% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.29% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.38% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6626 # Writes before turning the bus around for reads -system.physmem.totQLat 4505900396 # Total ticks spent queuing -system.physmem.totMemAccLat 8186169146 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 981405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22956.38 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6517 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.493018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.920871 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.293044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5326 81.72% 81.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 466 7.15% 88.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 1.04% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 161 2.47% 92.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 25 0.38% 92.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 129 1.98% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.48% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.31% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 32 0.49% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.28% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.14% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.11% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 150 2.30% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.11% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.37% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6517 # Writes before turning the bus around for reads +system.physmem.totQLat 4471540489 # Total ticks spent queuing +system.physmem.totMemAccLat 8179277989 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988730000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22612.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41706.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41362.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing -system.physmem.readRowHits 163849 # Number of row buffer hits during reads -system.physmem.writeRowHits 80221 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.22 # Row buffer hit rate for writes -system.physmem.avgGap 8550266.01 # Average gap between requests -system.physmem.pageHitRate 73.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 338884560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 184907250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 809296800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 448299360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85706052435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647489846750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1922504718675 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.601510 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740606830696 # Time in different power states -system.physmem_0.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing +system.physmem.readRowHits 164996 # Number of row buffer hits during reads +system.physmem.writeRowHits 78817 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.01 # Row buffer hit rate for writes +system.physmem.avgGap 8562983.95 # Average gap between requests +system.physmem.pageHitRate 73.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815575800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441858240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85932696690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647711485250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1923002863050 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.611581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740967841659 # Time in different power states +system.physmem_0.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34639965804 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34954258341 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 323764560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 176657250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 721687200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 429364800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187527431520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84711391605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648362356250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922252653185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.513716 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742063716846 # Time in different power states -system.physmem_1.memoryStateTime::REF 95872920000 # Time in different power states +system.physmem_1.actEnergy 319750200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 174466875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726835200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 423565200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85000293540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648529382750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922747495685 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.522659 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742335596201 # Time in different power states +system.physmem_1.memoryStateTime::REF 95896320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33181034404 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33587665799 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -390,56 +396,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5019 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5019 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1041 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 3978 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5019 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 4056 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10869.452663 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9826.177645 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7625.006320 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 4042 99.65% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10 0.25% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 4056 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8797 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8797 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1607 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7190 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8797 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8797 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7279 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6527.254746 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7242 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 32 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7279 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3032 74.75% 74.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1024 25.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4056 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5019 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5719 78.57% 78.57% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1560 21.43% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7279 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8797 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5019 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4056 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8797 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7279 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4056 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9075 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7279 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16076 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23515104 # DTB read hits -system.cpu0.dtb.read_misses 4346 # DTB read misses -system.cpu0.dtb.write_hits 17278792 # DTB write hits -system.cpu0.dtb.write_misses 673 # DTB write misses +system.cpu0.dtb.read_hits 25745693 # DTB read hits +system.cpu0.dtb.read_misses 7581 # DTB read misses +system.cpu0.dtb.write_hits 19246585 # DTB write hits +system.cpu0.dtb.write_misses 1216 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2434 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3751 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1554 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1856 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23519450 # DTB read accesses -system.cpu0.dtb.write_accesses 17279465 # DTB write accesses +system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25753274 # DTB read accesses +system.cpu0.dtb.write_accesses 19247801 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40793896 # DTB hits -system.cpu0.dtb.misses 5019 # DTB misses -system.cpu0.dtb.accesses 40798915 # DTB accesses +system.cpu0.dtb.hits 44992278 # DTB hits +system.cpu0.dtb.misses 8797 # DTB misses +system.cpu0.dtb.accesses 45001075 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -469,38 +476,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2305 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 237 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2068 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 1509 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10774.022531 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9696.406116 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7256.111559 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 1436 95.16% 95.16% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 61 4.04% 99.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 10 0.66% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 1509 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3674 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6255.531301 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2268 88.04% 88.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 277 10.75% 98.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1272 84.29% 84.29% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 237 15.71% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1509 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1509 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 3814 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 111711640 # ITB inst hits -system.cpu0.itb.inst_misses 2305 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 121573780 # ITB inst hits +system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -509,178 +517,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1402 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 111713945 # ITB inst accesses -system.cpu0.itb.hits 111711640 # DTB hits -system.cpu0.itb.misses 2305 # DTB misses -system.cpu0.itb.accesses 111713945 # DTB accesses -system.cpu0.numCycles 5741309822 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 121577454 # ITB inst accesses +system.cpu0.itb.hits 121573780 # DTB hits +system.cpu0.itb.misses 3674 # DTB misses +system.cpu0.itb.accesses 121577454 # DTB accesses +system.cpu0.numCycles 5743639488 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 108455216 # Number of instructions committed -system.cpu0.committedOps 130919966 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 115934267 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4495 # Number of float alu accesses -system.cpu0.num_func_calls 12371356 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14793634 # number of instructions that are conditional controls -system.cpu0.num_int_insts 115934267 # number of integer instructions -system.cpu0.num_fp_insts 4495 # number of float instructions -system.cpu0.num_int_register_reads 213655151 # number of times the integer registers were read -system.cpu0.num_int_register_writes 80737315 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3581 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 474775860 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48809609 # number of times the CC registers were written -system.cpu0.num_mem_refs 41877995 # number of memory refs -system.cpu0.num_load_insts 23749275 # Number of load instructions -system.cpu0.num_store_insts 18128720 # Number of store instructions -system.cpu0.num_idle_cycles 5480212444.901863 # Number of idle cycles -system.cpu0.num_busy_cycles 261097377.098137 # Number of busy cycles -system.cpu0.not_idle_fraction 0.045477 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.954523 # Percentage of idle cycles -system.cpu0.Branches 27818534 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2172 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 92606456 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 105045 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7793 0.01% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::MemRead 23749275 17.64% 86.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 18128720 13.47% 100.00% # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 1907 # number of quiesce instructions executed +system.cpu0.committedInsts 117757184 # Number of instructions committed +system.cpu0.committedOps 142314769 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125928094 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses +system.cpu0.num_func_calls 12772213 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16007583 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125928094 # number of integer instructions +system.cpu0.num_fp_insts 11483 # number of float instructions +system.cpu0.num_int_register_reads 231704258 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87445622 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 515435615 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53492348 # number of times the CC registers were written +system.cpu0.num_mem_refs 46148278 # number of memory refs +system.cpu0.num_load_insts 26004695 # Number of load instructions +system.cpu0.num_store_insts 20143583 # Number of store instructions +system.cpu0.num_idle_cycles 5456012961.442100 # Number of idle cycles +system.cpu0.num_busy_cycles 287626526.557900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050077 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949923 # Percentage of idle cycles +system.cpu0.Branches 29545337 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 99836654 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112117 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8321 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::MemRead 26004695 17.80% 86.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 20143583 13.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 134599461 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1796 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 588364 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.639030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40011095 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 588715 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 67.963437 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1836356000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.639030 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.964139 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.685547 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 82121594 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 82121594 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22367728 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22367728 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16608644 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16608644 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300494 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 300494 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 340955 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 340955 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 337105 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 337105 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38976372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38976372 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 39276866 # number of overall hits -system.cpu0.dcache.overall_hits::total 39276866 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 340778 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 340778 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 289444 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 289444 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 113643 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 113643 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20322 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20322 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19364 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19364 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 630222 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 630222 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 743865 # number of overall misses -system.cpu0.dcache.overall_misses::total 743865 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4892226500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5708519500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 329935000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 454112500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1575000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10600746000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10600746000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10600746000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22708506 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16898088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 414137 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 361277 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 356469 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39606594 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40020731 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.015007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017129 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.274409 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054322 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015912 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.015912 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018587 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018587 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14356.051447 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19722.362530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16235.360693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23451.378847 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23451.378847 # average StoreCondReq miss latency +system.cpu0.op_class::total 146107685 # Class of executed instruction +system.cpu0.dcache.tags.replacements 732170 # number of replacements +system.cpu0.dcache.tags.tagsinuse 488.694805 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44080957 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 732682 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.163832 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.694805 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 90660887 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90660887 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 24440244 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 24440244 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18493380 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18493380 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326498 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 326498 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374202 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374202 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371573 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 371573 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 42933624 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 42933624 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 43260122 # number of overall hits +system.cpu0.dcache.overall_hits::total 43260122 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 418073 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 418073 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 337261 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 337261 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133156 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 133156 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22252 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22252 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19918 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19918 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 755334 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 755334 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 888490 # number of overall misses +system.cpu0.dcache.overall_misses::total 888490 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5661692500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5661692500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6946372000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6946372000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344716000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 344716000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 507189500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 507189500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1629000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1629000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12608064500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12608064500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12608064500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12608064500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24858317 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24858317 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18830641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18830641 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459654 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 459654 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396454 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 396454 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391491 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391491 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 43688958 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 43688958 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 44148612 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 44148612 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016818 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016818 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017910 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.289687 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.289687 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056128 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056128 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050877 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050877 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017289 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.017289 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020125 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.020125 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13542.353847 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13542.353847 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20596.428286 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20596.428286 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15491.461442 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16820.653674 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16820.653674 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14250.900365 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14250.900365 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -689,149 +698,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 443107 # number of writebacks -system.cpu0.dcache.writebacks::total 443107 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25234 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25234 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 732170 # number of writebacks +system.cpu0.dcache.writebacks::total 732170 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25278 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25278 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14124 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14124 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25235 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25235 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25235 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 315544 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 315544 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289443 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 289443 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 86831 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 86831 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6198 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6198 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19364 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19364 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 604987 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 604987 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 691818 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 691818 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31738 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28393 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60131 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4148741500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4148741500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5419061500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5419061500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1553984000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1553984000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101488000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101488000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434796500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 434796500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1527000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1527000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9567803000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9567803000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11121787000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11121787000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6274722500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6274722500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5086196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5086196500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11360919000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11360919000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013895 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.209667 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.209667 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017156 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017156 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054322 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015275 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015275 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.017286 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13147.901719 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13147.901719 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18722.378845 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18722.378845 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17896.649814 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16374.314295 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22453.857674 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22453.857674 # average StoreCondReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15552 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25279 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25279 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25279 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25279 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392795 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 392795 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337260 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337260 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106103 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106103 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6700 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6700 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19918 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19918 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 730055 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 730055 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 836158 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 836158 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31819 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60318 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4839458000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6609064500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1736821000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104360500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 487321500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1579000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11448522500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13185343500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629856000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400865000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12030721000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017910 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230832 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050877 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016710 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15814.890237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16076.174659 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 197703.777806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 179135.579192 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188936.139429 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 188936.139429 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 987035 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.323984 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 110724084 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 987547 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 112.120318 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14346160000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.323984 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998680 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998680 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1146899 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120426360 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1147411 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.954859 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 224410836 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 224410836 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 110724084 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 110724084 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 110724084 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 110724084 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 110724084 # number of overall hits -system.cpu0.icache.overall_hits::total 110724084 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 987556 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 987556 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 987556 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 987556 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 987556 # number of overall misses -system.cpu0.icache.overall_misses::total 987556 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10780435500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10780435500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10780435500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10780435500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10780435500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10780435500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 111711640 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 111711640 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 111711640 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 111711640 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 111711640 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008840 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008840 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008840 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008840 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008840 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10916.277659 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10916.277659 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10916.277659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10916.277659 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244294980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244294980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120426360 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120426360 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120426360 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120426360 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 120426360 # number of overall hits +system.cpu0.icache.overall_hits::total 120426360 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1147420 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1147420 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1147420 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1147420 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1147420 # number of overall misses +system.cpu0.icache.overall_misses::total 1147420 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12257879000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12257879000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12257879000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12257879000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12257879000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12257879000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121573780 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121573780 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121573780 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121573780 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121573780 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121573780 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009438 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009438 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009438 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009438 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009438 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009438 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10682.992278 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,236 +849,238 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 987556 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 987556 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 987556 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 987556 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 987556 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 987556 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1146899 # number of writebacks +system.cpu0.icache.writebacks::total 1146899 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147420 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1147420 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147420 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1147420 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147420 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1147420 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10286657500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10286657500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10286657500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10286657500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10286657500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10286657500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11684169000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11684169000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11684169000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11684169000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11684169000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11684169000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.008840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.008840 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.008840 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10416.277659 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10416.277659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10416.277659 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009438 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009438 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009438 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1606259 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1606313 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 46 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935560 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935650 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 209215 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 245604 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16082.851224 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2813687 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 260278 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.810314 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245750 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 273082 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16075.027062 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3061877 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289178 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.588209 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7782.048512 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.435939 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.142248 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4563.552019 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1967.112212 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1769.560295 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.474979 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000027 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278537 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.108005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981619 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13335 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1270 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 259 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1410 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 11666 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.813904 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 52809362 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 52809362 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 5209 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2366 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7575 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 443106 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 443106 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28064 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28064 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1524 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1524 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 197142 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 197142 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 946461 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 317431 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 5209 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2366 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 946461 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 514573 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1468609 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 5209 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2366 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 946461 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 514573 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1468609 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 313 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 217 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 530 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25366 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 25366 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17838 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17838 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 38871 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 38871 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41095 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41095 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 91142 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 91142 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 313 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 217 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41095 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 130013 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 171638 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 313 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 217 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41095 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 130013 # number of overall misses -system.cpu0.l2cache.overall_misses::total 171638 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7197500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4644500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 11842000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 564638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 564638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 375101000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 375101000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1455000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1455000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2573340000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2573340000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3117324500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3117324500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3123622500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3123622500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7197500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4644500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3117324500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5696962500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 8826129000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7197500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4644500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3117324500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5696962500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 8826129000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 5522 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2583 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 8105 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 443106 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 53430 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19362 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 236013 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 236013 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 987556 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 987556 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 408573 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 408573 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 5522 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2583 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 987556 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 644586 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1640247 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 5522 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2583 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 987556 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 644586 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1640247 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.084011 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.065392 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.474752 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.474752 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.921289 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.921289 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.385544 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137322 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1488.094013 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.890162 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090826 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981142 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15022 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 320 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3316 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3838 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.916870 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 62794753 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 62794753 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10867 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4767 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 15634 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 501313 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 501313 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1348863 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1348863 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238469 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 238469 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1100555 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1100555 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411293 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 411293 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10867 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4767 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1100555 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 649762 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1765951 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10867 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4767 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1100555 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 649762 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1765951 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 177 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 76 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 253 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55141 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55141 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19907 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19907 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43650 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43650 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46865 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 46865 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94305 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94305 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 177 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 76 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 46865 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 185073 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 177 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 76 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 46865 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses +system.cpu0.l2cache.overall_misses::total 185073 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4896500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2045000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 6941500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 165758000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 165758000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42773000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42773000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1499992 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1499992 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2791235000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2791235000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3308401000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3308401000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3237666000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3237666000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4896500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2045000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3308401000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028901000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 9344243500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4896500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2045000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3308401000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028901000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 9344243500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11044 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4843 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15887 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 501313 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 501313 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1348863 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1348863 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55141 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55141 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19907 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19907 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282119 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 282119 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147420 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1147420 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505598 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 505598 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11044 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4843 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1147420 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 787717 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1951024 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11044 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4843 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1147420 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 787717 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1951024 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015693 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.015925 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.164699 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.164699 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041613 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041613 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.223074 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.223074 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.084011 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041613 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.201700 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.104642 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.056682 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.084011 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041613 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.201700 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.104642 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21403.225806 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 22343.396226 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22259.638887 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22259.638887 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21028.198229 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21028.198229 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 727500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 727500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66202.052944 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66202.052944 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 75856.539725 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 75856.539725 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34272.042527 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34272.042527 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21403.225806 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 75856.539725 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43818.406621 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 51422.930820 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22995.207668 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21403.225806 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 75856.539725 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43818.406621 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 51422.930820 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154722 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154722 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040844 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040844 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186522 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186522 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015693 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040844 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.175133 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.094859 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015693 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040844 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.175133 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.094859 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26907.894737 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27436.758893 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3006.075334 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3006.075334 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2148.641181 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2148.641181 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 136362.909091 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 136362.909091 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63945.819015 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63945.819015 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 70594.281447 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 70594.281447 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34331.859392 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34331.859392 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 50489.501440 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 50489.501440 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1078,213 +1089,210 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 185810 # number of writebacks -system.cpu0.l2cache.writebacks::total 185810 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1552 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1552 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 49 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 49 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1601 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1601 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1601 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1601 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 313 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 217 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses -system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 7353 # number of CleanEvict MSHR misses -system.cpu0.l2cache.CleanEvict_mshr_misses::total 7353 # number of CleanEvict MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 230762 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 230762 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 25366 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 25366 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17838 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17838 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 37319 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 37319 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 41095 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 41095 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 91093 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 91093 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 313 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 217 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 41095 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 128412 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 170037 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 313 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 217 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 41095 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 128412 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 230762 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 400799 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 231742 # number of writebacks +system.cpu0.l2cache.writebacks::total 231742 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1776 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1776 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 53 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 53 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1829 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1829 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1829 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1829 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 177 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 76 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 265136 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55141 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55141 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19907 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19907 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41874 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41874 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46865 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46865 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94252 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94252 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 177 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 76 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46865 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136126 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 183244 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 177 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 76 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46865 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136126 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 448380 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40760 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28393 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40841 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69153 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3342500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 8662000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 19159534735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 19159534735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 795300000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 795300000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 289164000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 289164000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1167000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1167000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2199161500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2199161500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2870754500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2870754500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2571948500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2571948500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3342500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2870754500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4771110000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 7650526500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5319500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3342500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2870754500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4771110000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19159534735 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 26810061235 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69340 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1589000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5423500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20369501795 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1428543500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1428543500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 338252500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 338252500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1199992 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1199992 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2362760500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2362760500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3027211000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3027211000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2665459000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2665459000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1589000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3027211000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5028219500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8060854000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1589000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3027211000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5028219500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 28430355795 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6020817500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7207029000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4873249000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4873249000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374890500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7561102000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187001000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187001000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10894066500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12080278000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065392 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561891500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12748103000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015925 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.474752 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.474752 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.921289 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.921289 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158123 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158123 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041613 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222954 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.222954 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103665 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.056682 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.084011 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041613 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199216 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148427 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040844 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186417 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093922 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.244353 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 16343.396226 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83027.252039 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31352.992194 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16210.561722 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 583500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58928.736033 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69856.539725 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28234.315480 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44993.304398 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16995.207668 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15403.225806 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 69856.539725 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37154.705168 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83027.252039 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66891.537242 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229818 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189703.746298 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176816.216879 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171635.579192 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 171635.579192 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181172.215662 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 174689.138577 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3288140 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1656034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 25235 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 165607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 165490 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 117 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 54153 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1498300 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 629767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1193646 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 275537 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87023 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42073 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 110674 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 255600 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 251928 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 987556 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 494836 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3354 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2960662 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2239612 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6956 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14519 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5221749 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 63239672 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 73903156 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10332 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22088 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 137175248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 821565 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4077224 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.054943 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.227994 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3903345 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1968246 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 321222 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317069 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4153 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1765403 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 733576 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1348863 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 190188 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312390 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112758 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301102 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297729 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147420 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 574776 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3316 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3438002 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2673168 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11871 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27031 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6150072 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 145478520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101119646 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19372 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 246661714 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 988213 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981714 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.123543 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.333265 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3853328 94.51% 94.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 223779 5.49% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 117 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2617497 87.78% 87.78% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 360064 12.08% 99.86% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4153 0.14% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4077224 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2138731998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981714 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3884130992 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115020156 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115184885 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1490356000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730152000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1049276975 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1265237983 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4373000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8998497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15993487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1315,64 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6206 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6206 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1170 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5036 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6206 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6206 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10147.252747 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9159.943965 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4842.286315 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 42 0.84% 0.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 2213 44.22% 45.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1504 30.05% 75.10% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 1077 21.52% 96.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 52 1.04% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 27 0.54% 98.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 32 0.64% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 42 0.84% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.10% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 7 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5005 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1704519828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1704519828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3865 77.22% 77.22% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1140 22.78% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5005 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6206 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 2355 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2355 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 481 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1874 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2355 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2355 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5695.537695 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1565 91.57% 91.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.90% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1228 71.85% 71.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 481 28.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1709 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2355 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6206 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5005 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1709 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5005 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1709 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4064 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5575996 # DTB read hits -system.cpu1.dtb.read_misses 5233 # DTB read misses -system.cpu1.dtb.write_hits 4889133 # DTB write hits -system.cpu1.dtb.write_misses 973 # DTB write misses +system.cpu1.dtb.read_hits 3323284 # DTB read hits +system.cpu1.dtb.read_misses 1962 # DTB read misses +system.cpu1.dtb.write_hits 2909831 # DTB write hits +system.cpu1.dtb.write_misses 393 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5581229 # DTB read accesses -system.cpu1.dtb.write_accesses 4890106 # DTB write accesses +system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3325246 # DTB read accesses +system.cpu1.dtb.write_accesses 2910224 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10465129 # DTB hits -system.cpu1.dtb.misses 6206 # DTB misses -system.cpu1.dtb.accesses 10471335 # DTB accesses +system.cpu1.dtb.hits 6233115 # DTB hits +system.cpu1.dtb.misses 2355 # DTB misses +system.cpu1.dtb.accesses 6235470 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1402,46 +1403,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2787 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2787 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 249 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2538 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2787 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11234.439834 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9816.231267 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6428.442620 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 752 39.00% 39.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 479 24.84% 63.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 554 28.73% 92.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 71 3.68% 96.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.10% 96.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.78% 97.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 0.88% 98.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.26% 98.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 26 1.35% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.16% 99.79% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.10% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1928 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1705600828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1705600828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1679 87.09% 87.09% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 249 12.91% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1928 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1376 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5169.477869 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 583 71.18% 85.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 72 8.79% 94.14% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.85% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.37% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2787 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1928 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 4715 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 23850368 # ITB inst hits -system.cpu1.itb.inst_misses 2787 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 13877832 # ITB inst hits +system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1450,179 +1449,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1894 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 23853155 # ITB inst accesses -system.cpu1.itb.hits 23850368 # DTB hits -system.cpu1.itb.misses 2787 # DTB misses -system.cpu1.itb.accesses 23853155 # DTB accesses -system.cpu1.numCycles 5742239724 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 13879208 # ITB inst accesses +system.cpu1.itb.hits 13877832 # DTB hits +system.cpu1.itb.misses 1376 # DTB misses +system.cpu1.itb.accesses 13879208 # DTB accesses +system.cpu1.numCycles 5742698802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23084590 # Number of instructions committed -system.cpu1.committedOps 28191246 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 25227117 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1341368 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2715447 # number of instructions that are conditional controls -system.cpu1.num_int_insts 25227117 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 45751310 # number of times the integer registers were read -system.cpu1.num_int_register_writes 17465196 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102291851 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9890204 # number of times the CC registers were written -system.cpu1.num_mem_refs 10752307 # number of memory refs -system.cpu1.num_load_insts 5706058 # Number of load instructions -system.cpu1.num_store_insts 5046249 # Number of store instructions -system.cpu1.num_idle_cycles 5671495056.418025 # Number of idle cycles -system.cpu1.num_busy_cycles 70744667.581975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012320 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987680 # Percentage of idle cycles -system.cpu1.Branches 4219564 # Number of branches fetched -system.cpu1.op_class::No_OpClass 167 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17843088 62.32% 62.32% # Class of executed instruction -system.cpu1.op_class::IntMult 31349 0.11% 62.43% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3702 0.01% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.44% # Class of executed instruction -system.cpu1.op_class::MemRead 5706058 19.93% 82.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 5046249 17.63% 100.00% # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.committedInsts 13679150 # Number of instructions committed +system.cpu1.committedOps 16668513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15113644 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 913162 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1492467 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15113644 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 27463830 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10666857 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 61159895 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5174219 # number of times the CC registers were written +system.cpu1.num_mem_refs 6447631 # number of memory refs +system.cpu1.num_load_insts 3428751 # Number of load instructions +system.cpu1.num_store_insts 3018880 # Number of store instructions +system.cpu1.num_idle_cycles 5696160545.959164 # Number of idle cycles +system.cpu1.num_busy_cycles 46538256.040836 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008104 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991896 # Percentage of idle cycles +system.cpu1.Branches 2456488 # Number of branches fetched +system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10511910 61.88% 61.88% # Class of executed instruction +system.cpu1.op_class::IntMult 24272 0.14% 62.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::MemRead 3428751 20.18% 82.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 3018880 17.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 28630613 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2852 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 292035 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.567308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10109505 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292547 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 34.556858 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 105794397000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.567308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.917124 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 21253597 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 21253597 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5149175 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5149175 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4639914 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4639914 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 67630 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 67630 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103001 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 103001 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95778 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 95778 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9789089 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9789089 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9856719 # number of overall hits -system.cpu1.dcache.overall_hits::total 9856719 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 190277 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 190277 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 126690 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 126690 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 44121 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 44121 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18673 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18673 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23929 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23929 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 316967 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 316967 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 361088 # number of overall misses -system.cpu1.dcache.overall_misses::total 361088 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2557291000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3433917500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339355000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 630190000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5470500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5991208500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5991208500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5991208500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 5339452 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4766604 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 111751 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 121674 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 119707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10106056 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10217807 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035636 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.026579 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.394815 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.153467 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.199896 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031364 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031364 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035339 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035339 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13439.832455 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27104.881995 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18173.566111 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26335.826821 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26335.826821 # average StoreCondReq miss latency +system.cpu1.op_class::total 16987025 # Class of executed instruction +system.cpu1.dcache.tags.replacements 147592 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.392474 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6004450 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 147942 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.586514 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106294932000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.392474 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.914829 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12646180 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12646180 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3055213 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3055213 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2743263 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2743263 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41902 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41902 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69872 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69872 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61606 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61606 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5798476 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5798476 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5840378 # number of overall hits +system.cpu1.dcache.overall_hits::total 5840378 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 112221 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 112221 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 79294 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 79294 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24421 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24421 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16601 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16601 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23085 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23085 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 191515 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 191515 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 215936 # number of overall misses +system.cpu1.dcache.overall_misses::total 215936 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1751790500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2724343500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320772500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 629240500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3762500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4476134000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4476134000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4476134000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3167434 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3167434 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2822557 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2822557 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66323 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66323 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86473 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 86473 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84691 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84691 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5989991 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5989991 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6056314 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6056314 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035430 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035430 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028093 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028093 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368213 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368213 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191979 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272579 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272579 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031973 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031973 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035655 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035655 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18901.679039 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18901.679039 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16592.100818 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16592.100818 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1631,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 180790 # number of writebacks -system.cpu1.dcache.writebacks::total 180790 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 404 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13063 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 404 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 404 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 189873 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 189873 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 126690 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 126690 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 43074 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 43074 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5610 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5610 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23929 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23929 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 316563 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 316563 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 359637 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 359637 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3143 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5663 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2352437000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2352437000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3307227500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3307227500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 648806500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 648806500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97651500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97651500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606310000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606310000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5421500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5659664500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6308471000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 420340500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 296300500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 716641000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035560 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026579 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.385446 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.385446 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.046107 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.046107 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.199896 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.199896 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031324 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031324 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035197 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035197 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12389.528790 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26104.881995 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15062.601569 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17406.684492 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25337.874546 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25337.874546 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 147592 # number of writebacks +system.cpu1.dcache.writebacks::total 147592 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 221 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11676 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 221 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112000 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 112000 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79294 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79294 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23950 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23950 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23085 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 191294 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 191294 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 215244 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 215244 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5504 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1626671000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2645049500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437326000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90573500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606189500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3728500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4271720500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4709046500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439448500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303112500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742561000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035360 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028093 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361112 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056954 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272579 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035540 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17878.477586 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17541.217950 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 133738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117579.563492 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 117579.563492 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126547.942787 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126547.942787 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 622414 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.397194 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 23227437 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 622926 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 37.287634 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 105696892000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.397194 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973432 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973432 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 463636 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.311121 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13413679 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 464148 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 28.899573 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106195496500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311121 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 220 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 48323652 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 48323652 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 23227437 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 23227437 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 23227437 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 23227437 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 23227437 # number of overall hits -system.cpu1.icache.overall_hits::total 23227437 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 622926 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 622926 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 622926 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 622926 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 622926 # number of overall misses -system.cpu1.icache.overall_misses::total 622926 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5716886500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5716886500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5716886500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5716886500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5716886500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5716886500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23850363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23850363 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23850363 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23850363 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23850363 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23850363 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026118 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.026118 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026118 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.026118 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026118 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.026118 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9177.472926 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9177.472926 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9177.472926 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9177.472926 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 28219802 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 28219802 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13413679 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13413679 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13413679 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13413679 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13413679 # number of overall hits +system.cpu1.icache.overall_hits::total 13413679 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 464148 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 464148 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 464148 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 464148 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 464148 # number of overall misses +system.cpu1.icache.overall_misses::total 464148 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4215419500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4215419500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4215419500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4215419500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4215419500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4215419500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13877827 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13877827 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13877827 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13877827 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13877827 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13877827 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033445 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033445 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033445 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033445 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033445 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033445 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.058955 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.058955 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9082.058955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9082.058955 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1780,240 +1778,234 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622926 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622926 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622926 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622926 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622926 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622926 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 463636 # number of writebacks +system.cpu1.icache.writebacks::total 463636 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 464148 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 464148 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 464148 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 464148 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 464148 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5405423500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5405423500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5405423500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5405423500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5405423500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5405423500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23975000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 23975000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026118 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.026118 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026118 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.026118 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8677.472926 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8677.472926 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8677.472926 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 135451.977401 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 135451.977401 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 135451.977401 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3983345500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3983345500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3983345500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3983345500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3983345500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3983345500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033445 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.033445 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.033445 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.058955 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 437692 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 437708 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118078 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 85932 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 65711 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15078.335139 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1680940 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 81927 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.517534 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 50218 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 30957 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14956.632857 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1041724 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 46098 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 22.598030 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8770.071442 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.089565 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.088469 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.092107 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2103.725355 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1007.268201 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.535283 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000189 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.321768 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.084166 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 452.717591 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.885041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000081 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194830 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128401 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.061479 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920309 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1082 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15126 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 297 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 350 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 424 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3207 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7762 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3991 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.066040 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.923218 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 31008240 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 31008240 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5928 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2864 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8792 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 180790 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 180790 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1732 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1732 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1100 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1100 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 58942 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 58942 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 603650 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 603650 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 167802 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 167802 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5928 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2864 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 603650 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 226744 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 839186 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5928 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2864 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 603650 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 226744 # number of overall hits -system.cpu1.l2cache.overall_hits::total 839186 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 209 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 176 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 385 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28345 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28345 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22827 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22827 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 37671 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 37671 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 19276 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 19276 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70755 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 70755 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 209 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 176 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 19276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 108426 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 128087 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 209 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 176 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 19276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 108426 # number of overall misses -system.cpu1.l2cache.overall_misses::total 128087 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 4414000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3881000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 8295000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 586663000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 586663000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 490009500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 490009500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5348000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5348000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1921205500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1921205500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842911500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842911500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1648156000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1648156000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 4414000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3881000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842911500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3569361500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4420568000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 4414000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3881000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842911500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3569361500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4420568000 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6137 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 3040 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9177 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 180790 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 180790 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 30077 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 30077 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23927 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23927 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 96613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 96613 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 622926 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 622926 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 238557 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 238557 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6137 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 3040 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 622926 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 335170 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 967273 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6137 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 3040 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 622926 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 335170 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 967273 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.057895 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.041953 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.942414 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.942414 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.954027 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.954027 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027632 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.912880 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 931 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14173 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 891 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1648 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12129 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056824 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002258 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.865051 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21133576 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21133576 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1470 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 3925 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 91545 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 91545 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 509576 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 509576 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18096 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 18096 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455478 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 455478 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77072 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 77072 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1470 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 455478 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 95168 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 554571 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1470 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 455478 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 95168 # number of overall hits +system.cpu1.l2cache.overall_hits::total 554571 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 642 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28981 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28981 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23084 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23084 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32217 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32217 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8670 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 8670 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63803 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 63803 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 8670 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 96020 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 105332 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 8670 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 96020 # number of overall misses +system.cpu1.l2cache.overall_misses::total 105332 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7035000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5940500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 12975500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 66105500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 66105500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54747500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54747500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3677500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3677500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1649546500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1649546500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 528187000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 528187000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1437865000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1437865000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7035000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5940500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 528187000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3087411500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3628574000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7035000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5940500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 528187000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3087411500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3628574000 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2800 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1767 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 4567 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91545 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 91545 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 509576 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 509576 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28981 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28981 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23084 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23084 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50313 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 50313 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 464148 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 464148 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 140875 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 140875 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2800 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1767 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 464148 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 191188 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 659903 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2800 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1767 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 464148 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 191188 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 659903 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.168081 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.140574 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.389916 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.389916 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.030944 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.030944 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.296596 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.296596 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.057895 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.030944 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.323496 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.132421 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034056 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.057895 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.030944 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.323496 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.132421 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 22051.136364 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21545.454545 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20697.230552 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20697.230552 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21466.224208 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21466.224208 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 2674000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2674000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50999.588543 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50999.588543 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 43728.548454 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 43728.548454 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23293.844958 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23293.844958 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 22051.136364 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 43728.548454 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32919.793223 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34512.229969 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21119.617225 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 22051.136364 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 43728.548454 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32919.793223 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34512.229969 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.640332 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.640332 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018679 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018679 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.452905 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.452905 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.168081 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018679 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502228 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.159617 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.168081 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018679 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502228 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.159617 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20001.683502 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20211.059190 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2280.994445 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2280.994445 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2371.664356 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2371.664356 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3677500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3677500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51201.120526 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51201.120526 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60921.222607 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60921.222607 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22536.009279 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22536.009279 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 34448.923404 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 34448.923404 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2022,217 +2014,214 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 39052 # number of writebacks -system.cpu1.l2cache.writebacks::total 39052 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 295 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 295 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 295 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 295 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 295 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 209 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 176 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 385 # number of ReadReq MSHR misses -system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2890 # number of CleanEvict MSHR misses -system.cpu1.l2cache.CleanEvict_mshr_misses::total 2890 # number of CleanEvict MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 35042 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 35042 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28345 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28345 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22827 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22827 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 37376 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 37376 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 19276 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 19276 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70755 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70755 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 209 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 176 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 19276 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108131 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 127792 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 209 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 176 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 19276 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108131 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 35042 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 162834 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 25761 # number of writebacks +system.cpu1.l2cache.writebacks::total 25761 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 70 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 70 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 70 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 70 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 345 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 297 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 642 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 20837 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28981 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28981 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23084 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23084 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32147 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 32147 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8670 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8670 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63803 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63803 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 345 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 297 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8670 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95950 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 105262 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 345 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 297 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8670 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95950 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 126099 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3143 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3320 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2520 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3258 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5663 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5840 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2825000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 5985000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2001835233 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 631483000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 631483000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 426660000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 426660000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5054000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5054000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1652764500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1652764500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 727255500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 727255500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1223626000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1223626000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2825000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 727255500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2876390500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3609631000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3160000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2825000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 727255500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2876390500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2001835233 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 5611466233 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22647500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 395196500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 417844000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 277400500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 277400500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22647500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 672597000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 695244500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041953 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5681 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4158500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9123500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 915724625 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 582445000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 582445000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432971000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432971000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3473500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3473500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1449025500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1449025500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476167000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476167000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1055047000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1055047000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4158500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476167000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2504072500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2989363000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4158500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476167000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2504072500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3905087625 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414452000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436671000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284931500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284931500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699383500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721602500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140574 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.942414 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.942414 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.954027 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.954027 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.386863 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.386863 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.030944 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.296596 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.296596 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132116 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.034056 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057895 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030944 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.322615 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638940 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638940 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018679 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.452905 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452905 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159511 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168343 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15545.454545 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 57126.740283 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22278.461810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22278.461810 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18691.023788 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18691.023788 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2527000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2527000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44219.940604 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44219.940604 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 37728.548454 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17293.844958 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17293.844958 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28246.142169 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15119.617225 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 16051.136364 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 37728.548454 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26600.979368 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 57126.740283 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34461.268734 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125738.625517 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125856.626506 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 110079.563492 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 110079.563492 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127951.977401 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118770.439696 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 119048.715753 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191087 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3473500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1936586 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 978536 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 13921 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 103851 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 103732 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 19887 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 919525 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 223940 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 770866 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 41722 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 69543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41698 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86819 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 103431 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 101180 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 622926 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 309787 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 46 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1858177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1153867 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8365 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 17379 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3037788 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39867972 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 35780458 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24548 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 75685138 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 354401 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2220337 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.063895 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.244785 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1323663 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668360 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10107 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 169443 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166760 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2683 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652363 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 118404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 509576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86260 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25020 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70278 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57602 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55059 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 464148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1383984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718041 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4385 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7029 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2113439 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58847556 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24276952 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7068 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83142776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 355785 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 998697 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.187513 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.397146 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 2078588 93.62% 93.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141630 6.38% 99.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 119 0.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 814111 81.52% 81.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 181903 18.21% 99.73% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2683 0.27% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2220337 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1156529000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 998697 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1278018500 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80617594 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79432929 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 934566000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696399000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 534214495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 317143500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5325000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11246990 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4229000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31011 # Transaction distribution -system.iobus.trans_dist::ReadResp 31011 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56596 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2253,11 +2242,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71540 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2278,96 +2267,96 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162790 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484054 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40088000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48741500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 93000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 609500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6155500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 165000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 32044000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 119500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186504974 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186329030 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84712000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36780000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36460 # number of replacements -system.iocache.tags.tagsinuse 14.383048 # Cycle average of tags in use +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.380003 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290140338000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.383048 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898940 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898940 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290757542000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380003 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898750 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898750 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328302 # Number of tag accesses -system.iocache.tags.data_accesses 328302 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 254 # number of ReadReq misses -system.iocache.ReadReq_misses::total 254 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 254 # number of demand (read+write) misses -system.iocache.demand_misses::total 254 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 254 # number of overall misses -system.iocache.overall_misses::total 254 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33010877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33010877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717790097 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717790097 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 33010877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 33010877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 33010877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 33010877 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 254 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 254 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32882376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32882376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4738851654 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4738851654 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32882376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32882376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32882376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32882376 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 254 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 254 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 254 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 254 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2376,40 +2365,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129964.082677 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129964.082677 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130239.346759 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130239.346759 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129964.082677 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129964.082677 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128950.494118 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128950.494118 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 99 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3.571429 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.262626 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 254 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 254 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 254 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 254 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 254 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 254 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20310877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20310877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2906590097 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20310877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20310877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20310877 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20132376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20132376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2927651654 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20132376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20132376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20132376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2418,289 +2407,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79964.082677 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79964.082677 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80239.346759 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79964.082677 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79964.082677 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 127982 # number of replacements -system.l2c.tags.tagsinuse 63841.400540 # Cycle average of tags in use -system.l2c.tags.total_refs 386797 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 192628 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.008000 # Average number of references to valid blocks. +system.l2c.tags.replacements 123906 # number of replacements +system.l2c.tags.tagsinuse 62994.829806 # Cycle average of tags in use +system.l2c.tags.total_refs 421817 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 187980 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.243946 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12055.995118 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.047185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7486.510812 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2815.662270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37403.783442 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1406.932882 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 489.801266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2179.617757 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.183960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13459.681359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.946988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.042686 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7381.464495 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2783.395152 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954481 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1451.828957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 405.858901 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1734.111238 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.205378 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.114235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.570736 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31928 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.112632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042471 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.022153 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006193 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961225 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31889 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 74 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27529 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32181 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 26438 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2359 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30054 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.487183 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29385 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.486588 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.499176 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5261289 # Number of tag accesses -system.l2c.tags.data_accesses 5261289 # Number of data accesses -system.l2c.Writeback_hits::writebacks 224862 # number of Writeback hits -system.l2c.Writeback_hits::total 224862 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1507 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1131 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2638 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 177 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3596 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1989 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5585 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 55 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 33 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 23888 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 41259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 41598 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 52 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 64 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 16804 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11932 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 9486 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 145171 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 55 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 23888 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 44855 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 41598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 52 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 64 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13921 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 9486 # number of demand (read+write) hits -system.l2c.demand_hits::total 150756 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 55 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu0.inst 23888 # number of overall hits -system.l2c.overall_hits::cpu0.data 44855 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 41598 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 52 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 64 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16804 # number of overall hits -system.l2c.overall_hits::cpu1.data 13921 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 9486 # number of overall hits -system.l2c.overall_hits::total 150756 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 6940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4223 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11163 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 425 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1268 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1693 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11072 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8126 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19198 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.tags.occ_task_id_percent::1024 0.491043 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5837673 # Number of tag accesses +system.l2c.tags.data_accesses 5837673 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 257503 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 257503 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32214 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1943 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34157 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2130 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 884 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4062 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5386 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 98 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 29368 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 46989 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47574 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 22 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 6299 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 4989 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3377 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 138807 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 98 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51051 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47574 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 22 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6299 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6313 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3377 # number of demand (read+write) hits +system.l2c.demand_hits::total 144193 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 98 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29368 # number of overall hits +system.l2c.overall_hits::cpu0.data 51051 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47574 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 22 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6299 # number of overall hits +system.l2c.overall_hits::cpu1.data 6313 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3377 # number of overall hits +system.l2c.overall_hits::total 144193 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9379 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2248 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11627 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 589 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1277 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1866 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11187 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7836 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19023 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17201 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8649 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 128053 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2469 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1018 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10524 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 167922 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17497 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8847 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2371 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 788 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169546 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17201 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19721 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 128053 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2469 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9144 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 10524 # number of demand (read+write) misses -system.l2c.demand_misses::total 187120 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu0.inst 17497 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20034 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8624 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) misses +system.l2c.demand_misses::total 188569 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17201 # number of overall misses -system.l2c.overall_misses::cpu0.data 19721 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 128053 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2469 # number of overall misses -system.l2c.overall_misses::cpu1.data 9144 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 10524 # number of overall misses -system.l2c.overall_misses::total 187120 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 17802500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 17716000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 35518500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2579000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2637000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 5216000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1610292500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1065510000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2675802500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 810000 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu0.inst 17497 # number of overall misses +system.l2c.overall_misses::cpu0.data 20034 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134641 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses +system.l2c.overall_misses::cpu1.data 8624 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5392 # number of overall misses +system.l2c.overall_misses::total 188569 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 29891000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5943500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 35834500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4589000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1770500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 6359500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1626887000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1026108000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2652995000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 948500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2259930500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1181087500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 329532000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 141154500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 24152577870 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 810000 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2300069500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1205085500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 317997500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 116823500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 24316117308 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 948500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2259930500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2791380000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 329532000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1206664500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26828380370 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 810000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2300069500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2831972500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 317997500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1142931500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 26969112308 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 948500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2259930500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2791380000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18423338040 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 329532000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1206664500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1816453330 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26828380370 # number of overall miss cycles -system.l2c.Writeback_accesses::writebacks 224862 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 224862 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 8447 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5354 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13801 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 560 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1445 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 14668 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10115 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24783 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 61 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 41089 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 49908 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 169651 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 52 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 64 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 19273 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12950 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 20010 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 313093 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 61 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 41089 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 64576 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 169651 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 52 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 19273 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23065 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 20010 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 337876 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 61 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 41089 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 64576 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 169651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 52 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 19273 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23065 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 20010 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 337876 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.821593 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.788756 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.808854 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.758929 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.877509 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.844389 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.754840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.803361 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.774644 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.057143 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.418628 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.173299 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.128107 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078610 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.536333 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.057143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.418628 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.305392 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.128107 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.396445 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.553813 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.098361 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.057143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.418628 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.305392 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.754803 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.128107 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.396445 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.525937 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.553813 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2565.201729 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4195.121951 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3181.805966 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6068.235294 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2079.652997 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3080.921441 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145438.267702 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131123.554024 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 139379.232212 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135000 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu0.inst 2300069500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2831972500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 317997500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1142931500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of overall miss cycles +system.l2c.overall_miss_latency::total 26969112308 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 257503 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 257503 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 41593 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4191 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45784 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2719 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2161 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4880 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9160 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24409 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 105 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 46865 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 55836 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182215 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 23 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 8670 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 5777 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8769 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 308353 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 105 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 46865 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 71085 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 23 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8670 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 14937 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8769 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 332762 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 105 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 46865 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 71085 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 23 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8670 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 14937 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8769 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 332762 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225495 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.536387 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.253953 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.216624 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590930 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.382377 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.733622 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.855459 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.779344 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.373349 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158446 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.273472 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136403 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.549844 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.373349 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281832 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.273472 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.577358 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.566678 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.373349 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281832 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.273472 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.577358 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.566678 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3187.013541 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2643.905694 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3082.007397 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7791.171477 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1386.452623 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3408.092176 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145426.566550 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130947.932619 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 139462.492772 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131383.669554 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136557.694531 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133467.800729 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138658.644401 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 143832.123665 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135000 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131455.078013 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136214.027354 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134119.569802 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 148253.172589 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 143418.997251 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131383.669554 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 141543.532275 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 133467.800729 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131962.434383 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 143375.269186 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 143019.861738 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131383.669554 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 141543.532275 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143872.756124 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 133467.800729 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131962.434383 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 172601.038578 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 143375.269186 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 143019.861738 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2709,258 +2713,271 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 98758 # number of writebacks -system.l2c.writebacks::total 98758 # number of writebacks +system.l2c.writebacks::writebacks 96871 # number of writebacks +system.l2c.writebacks::total 96871 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 18 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 3008 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 3008 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 6940 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4223 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11163 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 425 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1268 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1693 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11072 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8126 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19198 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 2791 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 2791 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 9379 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2248 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11627 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 589 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1277 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1866 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11187 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7836 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19023 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17196 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8649 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2456 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1018 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 167904 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17492 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8847 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2361 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 788 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 169531 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17196 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 19721 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2456 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9144 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 187102 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17492 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20034 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2361 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8624 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 188554 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17196 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 19721 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128053 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2456 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9144 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10524 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 187102 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17492 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20034 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2361 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8624 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 188554 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31738 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3139 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44076 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28393 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2520 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44096 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30922 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60131 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5659 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74989 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 527536000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 312350000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 839886000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 32879500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97434000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 130313500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1499572500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 984250000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2483822500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 750000 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5501 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 75018 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 706950000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 168753500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 875703500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 45541000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97962500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 143503500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1515017000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 947748000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2462765000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 878500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2087455500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1094597500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 303361000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 130974500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 22471411870 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 750000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2124790500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1116615500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 293429500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108943500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 22619490308 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 878500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2087455500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2594170000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 303361000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1115224500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24955234370 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 750000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2124790500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2631632500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 293429500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1056691500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25082255308 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 878500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2087455500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2594170000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 17142808040 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 303361000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1115224500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1711213330 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24955234370 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2124790500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2631632500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 293429500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1056691500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25082255308 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5449526500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19461500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 338634500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6831437500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4390566000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 234560000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4625126000 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5802133000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 358998500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7203979000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702508000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243698500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4946206500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9840092500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19461500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 573194500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11456563500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10504641000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602697000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12150185500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821593 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.788756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.808854 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758929 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.877509 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.844389 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.754840 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.803361 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774644 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.173299 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078610 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.536275 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.553759 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.098361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.057143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.418506 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.305392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.754803 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.127432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.396445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.525937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.553759 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 76013.832853 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73964.006630 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75238.376780 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77363.529412 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76840.694006 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76971.943296 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135438.267702 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121123.554024 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129379.232212 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225495 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.536387 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.253953 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.216624 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590930 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.382377 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733622 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.855459 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.779344 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158446 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136403 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.549795 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.566633 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.566633 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126557.694531 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128658.644401 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133834.881063 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121391.922540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131543.532275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133872.756124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123518.322476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121962.434383 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 162601.038578 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133377.699704 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171703.525742 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107879.738770 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154992.229331 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154635.508752 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 93079.365079 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 149617.507198 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 163644.251717 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109951.977401 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101289.008659 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 152776.587233 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44076 # Transaction distribution -system.membus.trans_dist::ReadResp 212234 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::Writeback 134964 # Transaction distribution -system.membus.trans_dist::CleanEvict 15319 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74839 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40260 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12961 # Transaction distribution -system.membus.trans_dist::ReadExReq 39815 # Transaction distribution -system.membus.trans_dist::ReadExResp 19093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 168158 # Transaction distribution +system.membus.trans_dist::ReadReq 44096 # Transaction distribution +system.membus.trans_dist::ReadResp 213882 # Transaction distribution +system.membus.trans_dist::WriteReq 30922 # Transaction distribution +system.membus.trans_dist::WriteResp 30922 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133077 # Transaction distribution +system.membus.trans_dist::CleanEvict 14603 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73616 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39905 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13581 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 39514 # Transaction distribution +system.membus.trans_dist::ReadExResp 18935 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169786 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664805 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786483 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 895419 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162790 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664049 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108937 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894720 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18323720 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18514046 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27532 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18296972 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18487386 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20832190 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123434 # Total snoops (count) -system.membus.snoop_fanout::samples 584834 # Request fanout histogram +system.membus.pkt_size::total 20805530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121102 # Total snoops (count) +system.membus.snoop_fanout::samples 582015 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 584834 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 582015 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 584834 # Request fanout histogram -system.membus.reqLayer0.occupancy 88258000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 582015 # Request fanout histogram +system.membus.reqLayer0.occupancy 88274000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11355499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11368000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 974246641 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 966740692 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1126274005 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1134075509 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64655929 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64085297 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3003,52 +3020,52 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 910965 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 460102 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 151032 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 21404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 587 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44080 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 476819 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 359850 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 80476 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77372 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40572 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 117944 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 97 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 97 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51046 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 432754 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 961177 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518872 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 139554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20662 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 869 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44099 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 468456 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390602 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 84323 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107685 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42919 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150604 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 84 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50476 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 424372 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1048506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 332828 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1381334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 29760096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6517470 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36277566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449108 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1186895 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.300945 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.459746 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224412 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249093 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1473505 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34296330 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3743120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38039450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438983 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 897187 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337621 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474943 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 830292 69.95% 69.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 356016 30.00% 99.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 587 0.05% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 595147 66.33% 66.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 301171 33.57% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 869 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1186895 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 806375018 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 897187 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 864296758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 359119 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 593704114 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 647366860 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 252660411 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 201908331 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 79e3a7b0a..05fb1382f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909343 # Number of seconds simulated -sim_ticks 2909343316500 # Number of ticks simulated -final_tick 2909343316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909604 # Number of seconds simulated +sim_ticks 2909603958500 # Number of ticks simulated +final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666869 # Simulator instruction rate (inst/s) -host_op_rate 804035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17251437084 # Simulator tick rate (ticks/s) -host_mem_usage 624248 # Number of bytes of host memory used -host_seconds 168.64 # Real time elapsed on the host -sim_insts 112463069 # Number of instructions simulated -sim_ops 135595282 # Number of ops (including micro ops) simulated +host_inst_rate 894735 # Simulator instruction rate (inst/s) +host_op_rate 1078768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23149732072 # Simulator tick rate (ticks/s) +host_mem_usage 579968 # Number of bytes of host memory used +host_seconds 125.69 # Real time elapsed on the host +sim_insts 112455934 # Number of instructions simulated +sim_ops 135586369 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1184996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517376 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534900 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26969 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166592 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117459 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121840 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583874 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583874 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6057217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166592 # Number of read requests accepted -system.physmem.writeReqs 121840 # Number of write requests accepted -system.physmem.readBursts 166592 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121840 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue -system.physmem.bytesWritten 7547776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534900 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40724 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10226 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10496 # Per bank write bursts -system.physmem.perBankRdBursts::4 18505 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10179 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9478 # Per bank write bursts -system.physmem.perBankRdBursts::9 10041 # Per bank write bursts -system.physmem.perBankRdBursts::10 9320 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9424 # Per bank write bursts -system.physmem.perBankRdBursts::13 10229 # Per bank write bursts -system.physmem.perBankRdBursts::14 9340 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7577 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8049 # Per bank write bursts -system.physmem.perBankWrBursts::4 7151 # Per bank write bursts -system.physmem.perBankWrBursts::5 7579 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6810 # Per bank write bursts -system.physmem.perBankWrBursts::11 7097 # Per bank write bursts -system.physmem.perBankWrBursts::12 7200 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6925 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10077 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10695 # Per bank write bursts +system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::4 18797 # Per bank write bursts +system.physmem.perBankRdBursts::5 9659 # Per bank write bursts +system.physmem.perBankRdBursts::6 9665 # Per bank write bursts +system.physmem.perBankRdBursts::7 10488 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9973 # Per bank write bursts +system.physmem.perBankRdBursts::10 9230 # Per bank write bursts +system.physmem.perBankRdBursts::11 8679 # Per bank write bursts +system.physmem.perBankRdBursts::12 9820 # Per bank write bursts +system.physmem.perBankRdBursts::13 10379 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8282 # Per bank write bursts +system.physmem.perBankWrBursts::3 8171 # Per bank write bursts +system.physmem.perBankWrBursts::4 7489 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7662 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6693 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7265 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2909342872000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2909603601500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157020 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 258 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,109 +159,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.682984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.521208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.535953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21321 36.39% 36.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14587 24.90% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6073 10.37% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3205 5.47% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2612 4.46% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1486 2.54% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1112 1.90% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1062 1.81% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7129 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58587 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.870621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 589.954659 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5765 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5766 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.453347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.695263 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.074003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4962 86.06% 86.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 90 1.56% 87.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 174 3.02% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.52% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.62% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.80% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.09% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.29% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.26% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.88% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.14% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.45% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.29% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5766 # Writes before turning the bus around for reads -system.physmem.totQLat 1636363750 # Total ticks spent queuing -system.physmem.totMemAccLat 4757732500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9829.60 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads +system.physmem.totQLat 1626690000 # Total ticks spent queuing +system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28579.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -271,40 +278,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136200 # Number of row buffer hits during reads -system.physmem.writeRowHits 89619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.98 # Row buffer hit rate for writes -system.physmem.avgGap 10086754.84 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229098240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125004000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702764400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392785200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90217297485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666466226750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948157128635 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.621597 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772138232000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 136108 # Number of row buffer hits during reads +system.physmem.writeRowHits 89502 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes +system.physmem.avgGap 10089372.82 # Average gap between requests +system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.620811 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40052866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213819480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116667375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595717200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371427120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190023952560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88066202985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668353151750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947740938470 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478544 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775299661000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97149260000 # Time in different power states +system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479792 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36894247500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -354,55 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9555 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9555 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1270 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8285 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7391 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12962.724936 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10716.855962 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8397.253568 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7386 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7391 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 9546 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9546 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1255 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 1638910500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6168 83.45% 83.45% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1223 16.55% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7391 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.64% 83.64% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1208 16.36% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7382 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9546 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7391 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9546 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7382 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7391 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16946 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24521784 # DTB read hits -system.cpu.dtb.read_misses 8135 # DTB read misses -system.cpu.dtb.write_hits 19607400 # DTB write hits -system.cpu.dtb.write_misses 1420 # DTB write misses +system.cpu.dtb.read_hits 24520223 # DTB read hits +system.cpu.dtb.read_misses 8124 # DTB read misses +system.cpu.dtb.write_hits 19606444 # DTB write hits +system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1651 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24529919 # DTB read accesses -system.cpu.dtb.write_accesses 19608820 # DTB write accesses +system.cpu.dtb.read_accesses 24528347 # DTB read accesses +system.cpu.dtb.write_accesses 19607866 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44129184 # DTB hits -system.cpu.dtb.misses 9555 # DTB misses -system.cpu.dtb.accesses 44138739 # DTB accesses +system.cpu.dtb.hits 44126667 # DTB hits +system.cpu.dtb.misses 9546 # DTB misses +system.cpu.dtb.accesses 44136213 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -440,11 +448,11 @@ system.cpu.itb.walker.walkWaitTime::samples 4763 # system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12663.288288 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10495.066195 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7808.701731 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2418 77.80% 77.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 688 22.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12722.007722 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10527.196882 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7865.701982 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2410 77.54% 77.54% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 696 22.39% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1638383000 # Table walker pending requests distribution @@ -460,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115560644 # ITB inst hits +system.cpu.itb.inst_hits 115553087 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -477,38 +485,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115565407 # ITB inst accesses -system.cpu.itb.hits 115560644 # DTB hits +system.cpu.itb.inst_accesses 115557850 # ITB inst accesses +system.cpu.itb.hits 115553087 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115565407 # DTB accesses -system.cpu.numCycles 5818686633 # number of cpu cycles simulated +system.cpu.itb.accesses 115557850 # DTB accesses +system.cpu.numCycles 5819207917 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112463069 # Number of instructions committed -system.cpu.committedOps 135595282 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119900050 # Number of integer alu accesses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112455934 # Number of instructions committed +system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9893453 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15231190 # number of instructions that are conditional controls -system.cpu.num_int_insts 119900050 # number of integer instructions +system.cpu.num_func_calls 9891908 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls +system.cpu.num_int_insts 119891885 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218076436 # number of times the integer registers were read -system.cpu.num_int_register_writes 82650791 # number of times the integer registers were written +system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read +system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489768723 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51897400 # number of times the CC registers were written -system.cpu.num_mem_refs 45409486 # number of memory refs -system.cpu.num_load_insts 24844046 # Number of load instructions -system.cpu.num_store_insts 20565440 # Number of store instructions -system.cpu.num_idle_cycles 5379802959.980151 # Number of idle cycles -system.cpu.num_busy_cycles 438883673.019849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075427 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924573 # Percentage of idle cycles -system.cpu.Branches 25918657 # Number of branches fetched +system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written +system.cpu.num_mem_refs 45406948 # number of memory refs +system.cpu.num_load_insts 24842511 # Number of load instructions +system.cpu.num_store_insts 20564437 # Number of store instructions +system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles +system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924365 # Percentage of idle cycles +system.cpu.Branches 25916368 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93180998 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114440 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -536,256 +546,254 @@ system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24844046 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20565440 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138715716 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 821347 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702129 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235829 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821859 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.607356 # Average number of references to valid blocks. +system.cpu.op_class::total 138706392 # Class of executed instruction +system.cpu.dcache.tags.replacements 819093 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999418 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177121649 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177121649 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112263 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112263 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18824569 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18824569 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392807 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392807 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443229 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460200 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460200 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329639 # number of overall hits -system.cpu.dcache.overall_hits::total 42329639 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401818 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401818 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298972 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118323 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823942 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823942 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443235 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443235 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460203 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460203 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936587 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936587 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329369 # number of overall hits +system.cpu.dcache.overall_hits::total 42329369 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399856 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399856 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298641 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298641 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118367 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22751 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22751 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 700790 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 700790 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 819113 # number of overall misses -system.cpu.dcache.overall_misses::total 819113 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6512815000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19103648000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19103648000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294606000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294606000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 698497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 816864 # number of overall misses +system.cpu.dcache.overall_misses::total 816864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484051000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6484051000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19116145000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19116145000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294006500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 294006500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25616463000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25616463000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25616463000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25616463000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23514081 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19123541 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511130 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511130 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460202 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42637622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42637622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43148752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43148752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017088 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015634 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231493 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048836 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231570 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048823 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048823 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016436 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016436 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018983 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018983 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16208.370456 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16208.370456 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63897.783070 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63897.783070 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12945.730984 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12945.730984 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016383 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018932 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36553.693689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36553.693689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31273.417709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31273.417709 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 685107 # number of writebacks -system.cpu.dcache.writebacks::total 685107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 939 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 939 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14240 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14240 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 939 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 939 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 939 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 939 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400879 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 400879 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298972 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298972 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116280 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116280 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8517 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8517 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683726 # number of writebacks +system.cpu.dcache.writebacks::total 683726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 924 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14242 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14242 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 924 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 924 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398932 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 398932 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298641 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298641 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116310 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116310 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8509 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8509 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 699851 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 699851 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 816131 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 816131 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 697573 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 697573 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 813883 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 813883 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080968000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18804676000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617499500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115437000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6055510500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6055510500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18817504000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18817504000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617135000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617135000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115280000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115280000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24885644000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24885644000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26503143500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26503143500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5936758500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5936758500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4791465500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4791465500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10728224000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10728224000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017048 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015634 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227496 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018277 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018277 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24873014500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26490149500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279074500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089978000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369052500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018260 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018260 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016414 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018914 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15169.085934 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62897.783070 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13910.384417 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13553.716097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13553.716097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35558.488878 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35558.488878 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32474.129153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32474.129153 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.595992 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173673.039980 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.585199 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.585199 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1696276 # number of replacements -system.cpu.icache.tags.tagsinuse 510.440576 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113863850 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696788 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.105525 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 28967481500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.440576 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1695571 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436867 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113856998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696083 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.129379 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436867 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117257438 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117257438 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113863850 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113863850 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113863850 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113863850 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113863850 # number of overall hits -system.cpu.icache.overall_hits::total 113863850 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1696794 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1696794 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1696794 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1696794 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1696794 # number of overall misses -system.cpu.icache.overall_misses::total 1696794 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24262817500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24262817500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24262817500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24262817500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24262817500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115560644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115560644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115560644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115560644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115560644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014683 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014683 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14299.212220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14299.212220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14299.212220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14299.212220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14299.212220 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117249176 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117249176 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113856998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113856998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113856998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113856998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113856998 # number of overall hits +system.cpu.icache.overall_hits::total 113856998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1696089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1696089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1696089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1696089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1696089 # number of overall misses +system.cpu.icache.overall_misses::total 1696089 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24269708000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24269708000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24269708000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24269708000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24269708000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24269708000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115553087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115553087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115553087 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115553087 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115553087 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115553087 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.218443 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.218443 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.218443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.218443 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,212 +802,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696794 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1696794 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1696794 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1696794 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1696794 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1696794 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1695571 # number of writebacks +system.cpu.icache.writebacks::total 1695571 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696089 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696089 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696089 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696089 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696089 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22566023500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22566023500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22566023500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22566023500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22566023500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22566023500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22573619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22573619000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22573619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22573619000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22573619000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22573619000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 1142541000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014683 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13299.212220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13299.212220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13299.212220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13299.212220 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014678 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87598 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64865.821065 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4548879 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152768 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 29.776386 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87564 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64865.227437 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4544047 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152799 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.738722 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50190.412542 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.801705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9659.374197 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5012.219980 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.765845 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50197.653066 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012653 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.739092 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.023293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765955 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.076480 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40555786 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40555786 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7774 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4032 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11806 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 685107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 685107 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 24 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 167410 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 167410 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678817 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1678817 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513395 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 513395 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4032 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1678817 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 680805 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2371428 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7774 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4032 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1678817 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 680805 # number of overall hits -system.cpu.l2cache.overall_hits::total 2371428 # number of overall hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40507837 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40507837 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7811 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 11850 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 683726 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 683726 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1664804 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1664804 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 166964 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 166964 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678077 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1678077 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511579 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 511579 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7811 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1678077 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 678543 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2368470 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7811 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1678077 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 678543 # number of overall hits +system.cpu.l2cache.overall_hits::total 2368470 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2735 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2735 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128803 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128803 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17954 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17954 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12281 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12281 # number of ReadSharedReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 128914 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 128914 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17979 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17954 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159047 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 17979 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 159074 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17954 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses -system.cpu.l2cache.overall_misses::total 159047 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 929000 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 17979 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses +system.cpu.l2cache.overall_misses::total 159074 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1147500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1195000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1856500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1856500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1413500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16377126500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16377126500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2358568000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2358568000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1624402500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1624402500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 929000 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391193500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16391193500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2350840500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2350840500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1613502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1613502500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1147500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2358568000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18001529000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20361292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 929000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2350840500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18004696000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20356950000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1147500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2358568000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18001529000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20361292000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4034 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 685107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 685107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2759 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 2350840500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18004696000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20356950000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11859 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 683726 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 683726 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1664804 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1664804 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296213 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296213 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696771 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1696771 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525676 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 525676 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7781 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4034 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1696771 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 821889 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530475 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7781 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4034 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1696771 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 821889 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530475 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000900 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000496 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000762 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991301 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295878 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295878 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696056 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1696056 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523751 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 523751 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7818 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1696056 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819629 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527544 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7818 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1696056 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819629 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527544 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.434832 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.434832 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010581 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010581 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023362 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023362 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000900 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000496 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010581 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.171658 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062853 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000900 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000496 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010581 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.171658 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062853 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132714.285714 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435700 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.435700 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010600 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010600 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023240 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023240 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010600 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172134 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062936 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010600 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172134 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062936 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 163928.571429 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 132777.777778 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 678.793419 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 678.793419 # average UpgradeReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 157055.555556 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.641724 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.641724 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131367.271917 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131367.271917 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132269.562739 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132269.562739 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.281025 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.281025 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130754.797263 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130754.797263 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132558.535984 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132558.535984 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 128020.597685 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132714.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127971.572979 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131367.271917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127594.404752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 128020.597685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127971.572979 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,31 +1022,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 81269 # number of writebacks -system.cpu.l2cache.writebacks::total 81269 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks +system.cpu.l2cache.writebacks::total 81185 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2735 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128803 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128803 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17954 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17954 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12281 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12281 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128914 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 128914 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17979 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141084 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159047 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 17979 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159074 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17954 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141084 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159047 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 17979 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159074 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1041,145 +1055,146 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 859000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1077500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1105000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 193639500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 193639500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1323500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15089096500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15089096500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2179028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2179028000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1501592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1501592500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 859000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15102053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15102053500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171050500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171050500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1491782500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1491782500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1077500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2179028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16590689000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18770822000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 859000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171050500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16593836000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18766210000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1077500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2179028000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16590689000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18770822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171050500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16593836000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18766210000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5547532500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6577298500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4474192000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4474192000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5889729000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6919495000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10021724500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11051490500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000762 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991301 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10662303500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11692069500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.434832 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.434832 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010581 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023362 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023362 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062853 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000496 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010581 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.171658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062853 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 122777.777778 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70800.548446 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70800.548446 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.641724 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121367.271917 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122269.562739 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121367.271917 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117594.404752 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118020.597685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178159.563877 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163777.353088 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162173.039980 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162173.039980 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170649.352087 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 163124.038731 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5058225 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539566 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38059 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 583 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 583 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2289899 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 802569 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1801014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696794 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5077168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2580972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25621 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7697011 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108629432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96644509 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205321201 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5294343 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018110 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133351 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175874 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5198460 98.19% 98.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 95883 1.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5294343 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3265837500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2554213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1279146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17840000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17837000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution @@ -1235,63 +1250,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186318027 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.083918 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313622510000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.083918 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067745 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067745 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1305,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28366877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28366877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4697294150 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4697294150 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28366877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28366877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28366877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28366877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1329,19 +1344,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124416.127193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124416.127193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129673.535501 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129673.535501 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124416.127193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124416.127193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1355,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16966877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16966877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2886094150 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16966877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16966877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16966877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,68 +1386,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74416.127193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74416.127193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79673.535501 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74416.127193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74416.127193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70632 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117459 # Transaction distribution -system.membus.trans_dist::CleanEvict 6342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 127038 # Transaction distribution -system.membus.trans_dist::ReadExResp 127038 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30472 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546385 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655279 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15305404 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15468757 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785877 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390004 # Request fanout histogram +system.membus.snoop_fanout::samples 389999 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390004 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390004 # Request fanout histogram -system.membus.reqLayer0.occupancy 90504500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389999 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821932659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952275997 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64458066 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 83f940052..037583e12 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1174884 # Simulator instruction rate (inst/s) -host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22908545755 # Simulator tick rate (ticks/s) -host_mem_usage 623708 # Number of bytes of host memory used -host_seconds 121.52 # Real time elapsed on the host +host_inst_rate 1268879 # Simulator instruction rate (inst/s) +host_op_rate 1544656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24741311872 # Simulator tick rate (ticks/s) +host_mem_usage 623824 # Number of bytes of host memory used +host_seconds 112.52 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -226,6 +226,8 @@ system.cpu0.itb.accesses 74781709 # DT system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.committedInsts 72626333 # Number of instructions committed system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses @@ -283,8 +285,6 @@ system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Cl system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 89742700 # Class of executed instruction -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. @@ -459,6 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks +system.cpu0.icache.writebacks::total 1699214 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -599,6 +601,8 @@ system.cpu1.itb.accesses 72262399 # DT system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.committedInsts 70146546 # Number of instructions committed system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses @@ -656,8 +660,6 @@ system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Cl system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 87477212 # Class of executed instruction -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -801,8 +803,10 @@ system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # nu system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits -system.l2c.Writeback_hits::total 682264 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits @@ -872,8 +876,10 @@ system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) @@ -955,7 +961,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138133 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution system.membus.trans_dist::CleanEvict 7977 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution @@ -1044,8 +1050,9 @@ system.toL2Bus.trans_dist::ReadReq 71244 # Tr system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution @@ -1058,11 +1065,11 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2 system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 182968 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index a4264e923..6e04c32d2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,136 +1,136 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909388 # Number of seconds simulated -sim_ticks 2909387991500 # Number of ticks simulated -final_tick 2909387991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909654 # Number of seconds simulated +sim_ticks 2909653700500 # Number of ticks simulated +final_tick 2909653700500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 670421 # Simulator instruction rate (inst/s) -host_op_rate 808321 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17345176485 # Simulator tick rate (ticks/s) -host_mem_usage 625252 # Number of bytes of host memory used -host_seconds 167.73 # Real time elapsed on the host -sim_insts 112452815 # Number of instructions simulated -sim_ops 135583410 # Number of ops (including micro ops) simulated +host_inst_rate 811232 # Simulator instruction rate (inst/s) +host_op_rate 978087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20990567196 # Simulator tick rate (ticks/s) +host_mem_usage 580224 # Number of bytes of host memory used +host_seconds 138.62 # Real time elapsed on the host +sim_insts 112450652 # Number of instructions simulated +sim_ops 135579653 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 538144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4761988 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 521248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4656256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 646852 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4138720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 665348 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4245540 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10087176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 538144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 646852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1184996 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 8860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8664 # Number of bytes written to this memory -system.physmem.bytes_written::total 7534772 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 521248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 665348 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13696 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 74910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73257 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66353 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2215 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2166 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121838 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 184968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1636766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1600278 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 222333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1422540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 228669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1459122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 184968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 222333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2583790 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2589813 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2583790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3467720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179144 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 228669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2587751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 184968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1639812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1603321 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 222333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1425518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 228669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1462103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6056926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166585 # Number of read requests accepted -system.physmem.writeReqs 121838 # Number of write requests accepted -system.physmem.readBursts 166585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10654272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7548800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10087176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7534772 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.writeReqs 121755 # Number of write requests accepted +system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10658432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 40727 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10228 # Per bank write bursts -system.physmem.perBankRdBursts::1 9700 # Per bank write bursts -system.physmem.perBankRdBursts::2 10356 # Per bank write bursts -system.physmem.perBankRdBursts::3 10495 # Per bank write bursts -system.physmem.perBankRdBursts::4 18506 # Per bank write bursts -system.physmem.perBankRdBursts::5 10022 # Per bank write bursts -system.physmem.perBankRdBursts::6 10178 # Per bank write bursts -system.physmem.perBankRdBursts::7 10614 # Per bank write bursts -system.physmem.perBankRdBursts::8 9477 # Per bank write bursts -system.physmem.perBankRdBursts::9 10047 # Per bank write bursts -system.physmem.perBankRdBursts::10 9317 # Per bank write bursts -system.physmem.perBankRdBursts::11 9342 # Per bank write bursts -system.physmem.perBankRdBursts::12 9423 # Per bank write bursts -system.physmem.perBankRdBursts::13 10228 # Per bank write bursts -system.physmem.perBankRdBursts::14 9339 # Per bank write bursts -system.physmem.perBankRdBursts::15 9201 # Per bank write bursts -system.physmem.perBankWrBursts::0 7595 # Per bank write bursts -system.physmem.perBankWrBursts::1 7036 # Per bank write bursts -system.physmem.perBankWrBursts::2 7887 # Per bank write bursts -system.physmem.perBankWrBursts::3 8047 # Per bank write bursts -system.physmem.perBankWrBursts::4 7152 # Per bank write bursts -system.physmem.perBankWrBursts::5 7580 # Per bank write bursts -system.physmem.perBankWrBursts::6 7566 # Per bank write bursts -system.physmem.perBankWrBursts::7 7770 # Per bank write bursts -system.physmem.perBankWrBursts::8 7275 # Per bank write bursts -system.physmem.perBankWrBursts::9 7619 # Per bank write bursts -system.physmem.perBankWrBursts::10 6806 # Per bank write bursts -system.physmem.perBankWrBursts::11 7096 # Per bank write bursts -system.physmem.perBankWrBursts::12 7204 # Per bank write bursts -system.physmem.perBankWrBursts::13 7753 # Per bank write bursts -system.physmem.perBankWrBursts::14 6924 # Per bank write bursts -system.physmem.perBankWrBursts::15 6640 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 47114 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10080 # Per bank write bursts +system.physmem.perBankRdBursts::1 9979 # Per bank write bursts +system.physmem.perBankRdBursts::2 10697 # Per bank write bursts +system.physmem.perBankRdBursts::3 10658 # Per bank write bursts +system.physmem.perBankRdBursts::4 18793 # Per bank write bursts +system.physmem.perBankRdBursts::5 9660 # Per bank write bursts +system.physmem.perBankRdBursts::6 9676 # Per bank write bursts +system.physmem.perBankRdBursts::7 10492 # Per bank write bursts +system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::9 9982 # Per bank write bursts +system.physmem.perBankRdBursts::10 9231 # Per bank write bursts +system.physmem.perBankRdBursts::11 8678 # Per bank write bursts +system.physmem.perBankRdBursts::12 9823 # Per bank write bursts +system.physmem.perBankRdBursts::13 10380 # Per bank write bursts +system.physmem.perBankRdBursts::14 9720 # Per bank write bursts +system.physmem.perBankRdBursts::15 9413 # Per bank write bursts +system.physmem.perBankWrBursts::0 7393 # Per bank write bursts +system.physmem.perBankWrBursts::1 7263 # Per bank write bursts +system.physmem.perBankWrBursts::2 8284 # Per bank write bursts +system.physmem.perBankWrBursts::3 8168 # Per bank write bursts +system.physmem.perBankWrBursts::4 7485 # Per bank write bursts +system.physmem.perBankWrBursts::5 7265 # Per bank write bursts +system.physmem.perBankWrBursts::6 7108 # Per bank write bursts +system.physmem.perBankWrBursts::7 7667 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 6694 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::12 7527 # Per bank write bursts +system.physmem.perBankWrBursts::13 7859 # Per bank write bursts +system.physmem.perBankWrBursts::14 7261 # Per bank write bursts +system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2909387547000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2909653343500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157013 # Read request sizes (log2) +system.physmem.readPktSize::6 157055 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117457 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 523 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117374 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 617 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,132 +161,137 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 168 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 193 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.902116 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.522866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.172226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21290 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14652 25.03% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6083 10.39% 71.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3178 5.43% 77.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2491 4.25% 81.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 2.67% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.77% 85.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1041 1.78% 87.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7211 12.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.986941 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 548.492879 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5740 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58556 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.810301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.232220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.272692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21388 36.53% 36.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14563 24.87% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6001 10.25% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3238 5.53% 77.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2533 4.33% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1526 2.61% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1009 1.72% 85.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1158 1.98% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7140 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58556 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.151786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.492775 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5709 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5743 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.538046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.602147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.025411 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 27 0.47% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 14 0.24% 0.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 12 0.21% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 14 0.24% 1.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4750 82.71% 83.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 125 2.18% 86.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.43% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 205 3.57% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.56% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 152 2.65% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.89% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.19% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.31% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.16% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 172 2.99% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.37% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.24% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5743 # Writes before turning the bus around for reads -system.physmem.totQLat 1603192250 # Total ticks spent queuing -system.physmem.totMemAccLat 4724561000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9630.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5712 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.629377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.719500 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.211627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 18 0.32% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.19% 0.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4765 83.42% 84.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 125 2.19% 86.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 59 1.03% 87.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 204 3.57% 91.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.56% 91.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 148 2.59% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.89% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.14% 95.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.16% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.30% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.14% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.92% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.11% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 19 0.33% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.05% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 15 0.26% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5712 # Writes before turning the bus around for reads +system.physmem.totQLat 1608810750 # Total ticks spent queuing +system.physmem.totMemAccLat 4731398250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832690000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9660.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28380.34 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28410.32 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -296,40 +301,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.27 # Average write queue length when enqueuing -system.physmem.readRowHits 136293 # Number of row buffer hits during reads -system.physmem.writeRowHits 89580 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10087224.48 # Average gap between requests -system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229158720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125037000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702772200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing +system.physmem.readRowHits 136274 # Number of row buffer hits during reads +system.physmem.writeRowHits 89542 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.97 # Row buffer hit rate for writes +system.physmem.avgGap 10089580.29 # Average gap between requests +system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230519520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125779500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702273000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90369730305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666360544250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948207148235 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.628037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771956641500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_0.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90285662430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666593127500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948374558750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624648 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772342347250 # Time in different power states +system.physmem_0.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40279614750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40149801500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213471720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116477625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 595709400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371414160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190027003920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88357601520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668125569500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947807247845 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.490585 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774916457500 # Time in different power states -system.physmem_1.memoryStateTime::REF 97150820000 # Time in different power states +system.physmem_1.actEnergy 212163840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115764000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370668960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88503009660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668156858000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947999475020 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.495738 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774969217000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97159660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37320566000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37524675500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -379,58 +384,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6929 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6929 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2193 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4735 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6928 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6928 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12939.357499 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11196.384549 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7211.949482 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4588 78.82% 78.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1229 21.11% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5821 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -0.616549 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000461000 161.65% 161.65% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -762972504 -61.65% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1237488496 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3649 62.70% 62.70% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2171 37.30% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5820 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6929 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6385 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6385 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1824 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4559 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7416.349168 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 3990 75.03% 75.03% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1324 24.90% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5318 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean -0.003389 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000434000 100.34% 100.34% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -6756564 -0.34% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1993677436 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3519 66.20% 66.20% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1797 33.80% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5316 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6385 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6929 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5820 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5316 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5820 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11701 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12044488 # DTB read hits -system.cpu0.dtb.read_misses 5975 # DTB read misses -system.cpu0.dtb.write_hits 9654865 # DTB write hits -system.cpu0.dtb.write_misses 954 # DTB write misses +system.cpu0.dtb.read_hits 12043498 # DTB read hits +system.cpu0.dtb.read_misses 5581 # DTB read misses +system.cpu0.dtb.write_hits 9607194 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4388 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3980 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 867 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12050463 # DTB read accesses -system.cpu0.dtb.write_accesses 9655819 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12049079 # DTB read accesses +system.cpu0.dtb.write_accesses 9607998 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21699353 # DTB hits -system.cpu0.dtb.misses 6929 # DTB misses -system.cpu0.dtb.accesses 21706282 # DTB accesses +system.cpu0.dtb.hits 21650692 # DTB hits +system.cpu0.dtb.misses 6385 # DTB misses +system.cpu0.dtb.accesses 21657077 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,256 +465,256 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3426 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3426 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 828 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2598 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3426 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3426 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2558 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12817.630962 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11147.269267 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6399.295854 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 694 27.13% 27.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 823 32.17% 59.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 178 6.96% 66.26% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 343 13.41% 79.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 1 0.04% 79.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 515 20.13% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 4 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2558 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3199 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3199 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2516 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3199 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3199 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2347 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6527.623179 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.56% 25.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 656 27.95% 53.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 193 8.22% 61.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.49% 78.23% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 500 21.30% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2347 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1730 67.63% 67.63% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 828 32.37% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2558 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1664 70.90% 70.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 683 29.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2347 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3426 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3426 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3199 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3199 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2558 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5984 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56823446 # ITB inst hits -system.cpu0.itb.inst_misses 3426 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2347 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5546 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56739503 # ITB inst hits +system.cpu0.itb.inst_misses 3199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2582 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56826872 # ITB inst accesses -system.cpu0.itb.hits 56823446 # DTB hits -system.cpu0.itb.misses 3426 # DTB misses -system.cpu0.itb.accesses 56826872 # DTB accesses -system.cpu0.numCycles 2910048510 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56742702 # ITB inst accesses +system.cpu0.itb.hits 56739503 # DTB hits +system.cpu0.itb.misses 3199 # DTB misses +system.cpu0.itb.accesses 56742702 # DTB accesses +system.cpu0.numCycles 2910044532 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55288600 # Number of instructions committed -system.cpu0.committedOps 66713599 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58931600 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5354 # Number of float alu accesses -system.cpu0.num_func_calls 4809440 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7565706 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58931600 # number of integer instructions -system.cpu0.num_fp_insts 5354 # number of float instructions -system.cpu0.num_int_register_reads 107138015 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40582750 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4124 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1232 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240777875 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25734446 # number of times the CC registers were written -system.cpu0.num_mem_refs 22316238 # number of memory refs -system.cpu0.num_load_insts 12197914 # Number of load instructions -system.cpu0.num_store_insts 10118324 # Number of store instructions -system.cpu0.num_idle_cycles 2666885275.671365 # Number of idle cycles -system.cpu0.num_busy_cycles 243163234.328635 # Number of busy cycles -system.cpu0.not_idle_fraction 0.083560 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.916440 # Percentage of idle cycles -system.cpu0.Branches 12750711 # Number of branches fetched -system.cpu0.op_class::No_OpClass 119 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45844704 67.20% 67.20% # Class of executed instruction -system.cpu0.op_class::IntMult 57827 0.08% 67.28% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3997 0.01% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::MemRead 12197914 17.88% 85.17% # Class of executed instruction -system.cpu0.op_class::MemWrite 10118324 14.83% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68222885 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 821400 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702036 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43232181 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 821912 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.599525 # Average number of references to valid blocks. +system.cpu0.committedInsts 55201459 # Number of instructions committed +system.cpu0.committedOps 66609946 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58847772 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5145 # Number of float alu accesses +system.cpu0.num_func_calls 4820077 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7555989 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58847772 # number of integer instructions +system.cpu0.num_fp_insts 5145 # number of float instructions +system.cpu0.num_int_register_reads 106933475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40499308 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3730 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1418 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240486031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25664833 # number of times the CC registers were written +system.cpu0.num_mem_refs 22274491 # number of memory refs +system.cpu0.num_load_insts 12198391 # Number of load instructions +system.cpu0.num_store_insts 10076100 # Number of store instructions +system.cpu0.num_idle_cycles 2694628360.005429 # Number of idle cycles +system.cpu0.num_busy_cycles 215416171.994570 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074025 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925975 # Percentage of idle cycles +system.cpu0.Branches 12743161 # Number of branches fetched +system.cpu0.op_class::No_OpClass 131 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45792912 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 56104 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::MemRead 12198391 17.91% 85.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 10076100 14.79% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 68127601 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819018 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702192 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43232909 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819530 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.753296 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 174.965504 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 336.736532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.341730 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.657689 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309115 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914830 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177107266 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177107266 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11359748 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11750430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110178 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9271451 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9551716 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823167 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190318 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202376 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392694 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 212739 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 230449 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443188 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 220738 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 239445 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460183 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20631199 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21302146 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41933345 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20821517 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21504522 # number of overall hits -system.cpu0.dcache.overall_hits::total 42326039 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197790 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 204093 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401883 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 151382 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 147597 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298979 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58506 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59775 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118281 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10799 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11977 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22776 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 177098246 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177098246 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11355856 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11755360 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23111216 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9224406 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9598440 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18822846 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190279 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202400 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392679 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213881 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229331 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443212 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221919 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238270 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460189 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20580262 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21353800 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41934062 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20770541 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21556200 # number of overall hits +system.cpu0.dcache.overall_hits::total 42326741 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199428 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 200396 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399824 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149476 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 149150 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298626 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58742 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59581 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10843 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11913 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 349172 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 351690 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 700862 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 407678 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 411465 # number of overall misses -system.cpu0.dcache.overall_misses::total 819143 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3205236500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3305769000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6511005500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10124353500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 8964207000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19088560500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137582000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 157353000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 294935000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 348904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 349546 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 698450 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 407646 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 409127 # number of overall misses +system.cpu0.dcache.overall_misses::total 816773 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3300764500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3177768500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6478533000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9862313500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9244759000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19107072500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137644000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 156454000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 294098000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13329590000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 12269976000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25599566000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13329590000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 12269976000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25599566000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11557538 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11954523 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23512061 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9422833 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9699313 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19122146 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 248824 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 262151 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 510975 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223538 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 242426 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 220738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 239447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20980371 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21653836 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634207 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21229195 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21915987 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43145182 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017114 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017072 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017093 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016065 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015217 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015635 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235130 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.228017 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231481 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048309 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049405 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048879 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu0.data 13163078000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 12422527500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25585605500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 13163078000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 12422527500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25585605500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11555284 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11955756 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23511040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9373882 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9747590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19121472 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249021 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261981 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511002 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224724 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241244 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465968 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221919 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238272 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460191 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 20929166 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21703346 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42632512 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21178187 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21965327 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43143514 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017259 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016761 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015946 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015301 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235892 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231551 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048250 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049382 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016643 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016241 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019204 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018775 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018986 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16205.250518 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16197.365907 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16201.246383 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 66879.506811 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60734.344194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63845.823620 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12740.253727 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13137.931034 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12949.376537 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016671 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016106 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019248 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018626 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16551.158814 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15857.444759 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16203.462023 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65979.244160 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61982.963460 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63983.285112 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12694.272803 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13133.047931 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12923.976094 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38174.853654 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 34888.612130 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36525.829621 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32696.368212 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29820.218002 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31251.644707 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37726.933483 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35539.034920 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36631.978667 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.462804 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30363.499598 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31325.234184 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -718,201 +723,201 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685305 # number of writebacks -system.cpu0.dcache.writebacks::total 685305 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 467 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 450 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 917 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 6966 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7290 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14256 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 467 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 450 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 917 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 467 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 450 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 917 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197323 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 203643 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 400966 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151382 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 147597 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298979 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57401 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58845 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116246 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3833 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4687 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8520 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 683842 # number of writebacks +system.cpu0.dcache.writebacks::total 683842 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 485 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 439 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7005 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7232 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14237 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 485 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 485 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198943 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199957 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 398900 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149476 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 149150 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298626 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57623 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58651 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116274 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3838 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4681 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8519 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 348705 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 351240 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 699945 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 406106 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 410085 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 816191 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15125 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16013 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.demand_mshr_misses::cpu0.data 348419 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 349107 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697526 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 406042 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 407758 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813800 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15006 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16132 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13276 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14313 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13389 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14200 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28401 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30326 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28395 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30332 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2991931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3087967000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6079898500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9972971500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 8816610000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18789581500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 804001000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 810571000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614572000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52152500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63092500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3085102500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2965375000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6050477500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9712837500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9095609000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18808446500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 798019000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 816464500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614483500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52409500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62952500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115362000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12964903000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 11904577000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24869480000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13768904000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12715148000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26484052000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2876770000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3059986500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5936756500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2305348000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2486099500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4791447500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5182118000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5546086000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10728204000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017035 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017054 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016065 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015217 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015635 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230689 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.224470 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227498 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017147 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019334 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018285 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12797940000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12060984000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24858924000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13595959000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12877448500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26473407500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3049211500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229832500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6279044000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2494979500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594954500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089934000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5544191000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824787000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368978000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017217 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016966 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015946 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015301 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231398 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223875 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227541 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017079 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019404 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018282 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016621 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018712 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018917 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15162.609022 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15163.629489 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15163.127298 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 65879.506811 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59734.344194 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62845.823620 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14006.742043 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13774.679242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13889.269308 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13606.183146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13461.169191 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13526.408451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016648 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019173 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018564 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37180.146542 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 33892.999089 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35530.620263 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33904.704683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31006.127998 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32448.350937 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190199.669421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191093.892462 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190659.531762 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173647.785478 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 173695.207154 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173672.387546 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182462.518925 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182882.213282 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182679.244640 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1696133 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.440350 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113853580 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696645 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.105128 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 28968175500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 264.675620 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 245.764730 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.516945 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.480009 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1695285 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436603 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113852008 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1695797 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.137758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.971705 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.464899 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117132 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879814 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996946 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117246882 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117246882 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55981187 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57872393 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113853580 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55981187 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57872393 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113853580 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55981187 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57872393 # number of overall hits -system.cpu0.icache.overall_hits::total 113853580 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 842259 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 854392 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1696651 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 842259 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 854392 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1696651 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 842259 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 854392 # number of overall misses -system.cpu0.icache.overall_misses::total 1696651 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11932408500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12314837000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24247245500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11932408500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12314837000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24247245500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11932408500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12314837000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24247245500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56823446 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58726785 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115550231 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56823446 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58726785 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115550231 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56823446 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58726785 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115550231 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014822 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014549 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014683 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014822 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014549 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014683 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014822 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014549 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014683 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14167.148704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14413.567777 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14291.239330 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14291.239330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14167.148704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14413.567777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14291.239330 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117243614 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117243614 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55899037 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57952971 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113852008 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55899037 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57952971 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113852008 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55899037 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57952971 # number of overall hits +system.cpu0.icache.overall_hits::total 113852008 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 840466 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855337 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1695803 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 840466 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855337 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1695803 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 840466 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855337 # number of overall misses +system.cpu0.icache.overall_misses::total 1695803 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11890019000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12374432000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 24264451000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11890019000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 12374432000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 24264451000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11890019000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 12374432000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 24264451000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56739503 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58808308 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115547811 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56739503 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58808308 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115547811 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56739503 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58808308 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115547811 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014813 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014544 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014813 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014544 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014813 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014544 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14308.531710 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14308.531710 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,54 +926,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 842259 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854392 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1696651 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 842259 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 854392 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1696651 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 842259 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 854392 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1696651 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1695285 # number of writebacks +system.cpu0.icache.writebacks::total 1695285 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840466 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1695803 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 840466 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 855337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1695803 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 840466 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 855337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1695803 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11090149500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11460445000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22550594500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11090149500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11460445000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22550594500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11090149500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11460445000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22550594500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11049553000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11519095000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22568648000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11049553000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11519095000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22568648000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11049553000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11519095000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22568648000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014683 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014822 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014549 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014683 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13291.239330 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13167.148704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13413.567777 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13291.239330 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014676 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014676 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014676 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1005,54 +1012,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6703 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6703 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2138 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4565 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6703 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6703 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5647 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13331.414911 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11611.737502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7443.565061 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5646 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6953 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2226 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4727 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6953 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6953 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5856 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7342.287931 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5855 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5647 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5856 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3534 62.58% 62.58% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2113 37.42% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5647 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6703 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3650 62.33% 62.33% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2206 37.67% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5856 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6703 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5856 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5647 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12350 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5856 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12809 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12475099 # DTB read hits -system.cpu1.dtb.read_misses 5811 # DTB read misses -system.cpu1.dtb.write_hits 9951122 # DTB write hits -system.cpu1.dtb.write_misses 892 # DTB write misses +system.cpu1.dtb.read_misses 5924 # DTB read misses +system.cpu1.dtb.write_hits 9998125 # DTB write hits +system.cpu1.dtb.write_misses 1029 # DTB write misses system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4467 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4683 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 929 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 921 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12480910 # DTB read accesses -system.cpu1.dtb.write_accesses 9952014 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12481023 # DTB read accesses +system.cpu1.dtb.write_accesses 9999154 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22426221 # DTB hits -system.cpu1.dtb.misses 6703 # DTB misses -system.cpu1.dtb.accesses 22432924 # DTB accesses +system.cpu1.dtb.hits 22473224 # DTB hits +system.cpu1.dtb.misses 6953 # DTB misses +system.cpu1.dtb.accesses 22480177 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1082,117 +1089,117 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3400 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3400 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 811 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2589 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3400 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3400 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13798.698814 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12017.058980 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7032.742162 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1945 74.44% 74.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 667 25.53% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3510 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3510 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2664 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3510 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2707 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7184.126564 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1964 72.55% 72.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 742 27.41% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2707 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1802 68.96% 68.96% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 811 31.04% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2613 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1861 68.75% 68.75% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 846 31.25% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2707 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3400 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3510 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2613 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6013 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58726785 # ITB inst hits -system.cpu1.itb.inst_misses 3400 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2707 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58808308 # ITB inst hits +system.cpu1.itb.inst_misses 3510 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2616 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2708 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58730185 # ITB inst accesses -system.cpu1.itb.hits 58726785 # DTB hits -system.cpu1.itb.misses 3400 # DTB misses -system.cpu1.itb.accesses 58730185 # DTB accesses -system.cpu1.numCycles 2908727473 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58811818 # ITB inst accesses +system.cpu1.itb.hits 58808308 # DTB hits +system.cpu1.itb.misses 3510 # DTB misses +system.cpu1.itb.accesses 58811818 # DTB accesses +system.cpu1.numCycles 2909262869 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 57164215 # Number of instructions committed -system.cpu1.committedOps 68869811 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 60957593 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5807 # Number of float alu accesses -system.cpu1.num_func_calls 5082908 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7664467 # number of instructions that are conditional controls -system.cpu1.num_int_insts 60957593 # number of integer instructions -system.cpu1.num_fp_insts 5807 # number of float instructions -system.cpu1.num_int_register_reads 110918664 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42060766 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4325 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1484 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 248948036 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26157973 # number of times the CC registers were written -system.cpu1.num_mem_refs 23089661 # number of memory refs -system.cpu1.num_load_insts 12644031 # Number of load instructions -system.cpu1.num_store_insts 10445630 # Number of store instructions -system.cpu1.num_idle_cycles 2688977301.144567 # Number of idle cycles -system.cpu1.num_busy_cycles 219750171.855433 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075549 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924451 # Percentage of idle cycles -system.cpu1.Branches 13165858 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2218 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47327866 67.15% 67.15% # Class of executed instruction -system.cpu1.op_class::IntMult 56561 0.08% 67.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4450 0.01% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu1.op_class::MemRead 12644031 17.94% 85.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 10445630 14.82% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70480756 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.committedInsts 57249193 # Number of instructions committed +system.cpu1.committedOps 68969707 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61038090 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5951 # Number of float alu accesses +system.cpu1.num_func_calls 5071147 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7673896 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61038090 # number of integer instructions +system.cpu1.num_fp_insts 5951 # number of float instructions +system.cpu1.num_int_register_reads 111115264 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42140927 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4654 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1298 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 249224724 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26227815 # number of times the CC registers were written +system.cpu1.num_mem_refs 23129732 # number of memory refs +system.cpu1.num_load_insts 12642519 # Number of load instructions +system.cpu1.num_store_insts 10487213 # Number of store instructions +system.cpu1.num_idle_cycles 2689871255.481362 # Number of idle cycles +system.cpu1.num_busy_cycles 219391613.518638 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles +system.cpu1.Branches 13171953 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2206 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47377307 67.13% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4478 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction +system.cpu1.op_class::MemRead 12642519 17.91% 85.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 10487213 14.86% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 70572042 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1247,63 +1254,63 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46335000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 644000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6286500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 172500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 36458500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 126500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186329023 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 186202055 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084103 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084308 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313630728000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084103 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067756 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067756 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084308 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067769 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067769 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1317,14 +1324,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28361877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28361877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4696967146 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4696967146 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28361877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28361877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28361877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28361877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28182877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28182877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4712497178 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4712497178 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28182877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28182877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28182877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28182877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1341,19 +1348,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124394.197368 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124394.197368 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129664.508227 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129664.508227 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124394.197368 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124394.197368 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123609.109649 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123609.109649 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.283333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1367,14 +1374,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16961877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16961877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2885767146 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2885767146 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16961877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16961877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16961877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16961877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16782877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16782877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2901297178 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2901297178 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16782877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16782877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16782877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16782877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1383,262 +1390,266 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74394.197368 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74394.197368 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79664.508227 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79664.508227 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74394.197368 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74394.197368 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73609.109649 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73609.109649 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80093.230400 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80093.230400 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73609.109649 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73609.109649 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73609.109649 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73609.109649 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 87592 # number of replacements -system.l2c.tags.tagsinuse 64865.832577 # Cycle average of tags in use -system.l2c.tags.total_refs 4555575 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152761 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.821584 # Average number of references to valid blocks. +system.l2c.tags.replacements 87564 # number of replacements +system.l2c.tags.tagsinuse 64865.205876 # Cycle average of tags in use +system.l2c.tags.total_refs 4550112 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152799 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.778415 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50194.873681 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905171 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4138.424328 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2240.226521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.840428 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000599 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5521.257429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2766.304421 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.765913 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50199.141301 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4090.389058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2504.726247 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5610.428826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2455.776722 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063147 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.034183 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.038219 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.084248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.042210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.085608 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6804 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6848 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56203 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40610992 # Number of tag accesses -system.l2c.tags.data_accesses 40610992 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6231 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3376 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18903 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 685305 # number of Writeback hits -system.l2c.Writeback_hits::total 685305 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80673 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 86743 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167416 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 834184 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 844481 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1678665 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 252476 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 260979 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 513455 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 834184 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 333149 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6231 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3376 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844481 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 347722 # number of demand (read+write) hits -system.l2c.demand_hits::total 2378439 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6164 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3132 # number of overall hits -system.l2c.overall_hits::cpu0.inst 834184 # number of overall hits -system.l2c.overall_hits::cpu0.data 333149 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6231 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3376 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844481 # number of overall hits -system.l2c.overall_hits::cpu1.data 347722 # number of overall hits -system.l2c.overall_hits::total 2378439 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40556804 # Number of tag accesses +system.l2c.tags.data_accesses 40556804 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5806 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3022 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3498 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18686 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683842 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1664516 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1664516 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 80852 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166947 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 832656 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 845134 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1677790 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 253841 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 257681 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511522 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5806 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3022 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 832656 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 334693 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3498 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 845134 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343776 # number of demand (read+write) hits +system.l2c.demand_hits::total 2374945 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5806 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3022 # number of overall hits +system.l2c.overall_hits::cpu0.inst 832656 # number of overall hits +system.l2c.overall_hits::cpu0.data 334693 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3498 # number of overall hits +system.l2c.overall_hits::cpu1.inst 845134 # number of overall hits +system.l2c.overall_hits::cpu1.data 343776 # number of overall hits +system.l2c.overall_hits::total 2374945 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1339 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2745 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1384 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1358 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 69293 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 59501 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128794 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 8056 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 9898 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17954 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6081 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 6196 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12277 # number of ReadSharedReq misses +system.l2c.ReadExReq_misses::cpu0.data 67226 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 61688 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128914 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7792 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10187 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 6563 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5608 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8056 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 75374 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7792 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73789 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9898 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 65697 # number of demand (read+write) misses -system.l2c.demand_misses::total 159033 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10187 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 67296 # number of demand (read+write) misses +system.l2c.demand_misses::total 159072 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8056 # number of overall misses -system.l2c.overall_misses::cpu0.data 75374 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7792 # number of overall misses +system.l2c.overall_misses::cpu0.data 73789 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9898 # number of overall misses -system.l2c.overall_misses::cpu1.data 65697 # number of overall misses -system.l2c.overall_misses::total 159033 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 531000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 412000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 10187 # number of overall misses +system.l2c.overall_misses::cpu1.data 67296 # number of overall misses +system.l2c.overall_misses::total 159072 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 530500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 398500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 133000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1076000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 807500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1049000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1856500 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::total 1062000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1048500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 809000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8785071500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 7576077500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 16361149000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1050880500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1294053500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2344934000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 804079500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 815434500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1619514000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 531000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1050880500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9589151000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 412000 # number of demand (read+write) miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8525926000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 7856246500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 16382172500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1017223000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1332151500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 2349374500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 871059500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 735537500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1606597000 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 530500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1017223000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9396985500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 398500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1294053500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 8391512000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20326673000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 531000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1050880500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9589151000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 412000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1332151500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 8591784000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20339206000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 530500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1017223000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9396985500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 398500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1294053500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 8391512000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20326673000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 6168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6234 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3377 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 18911 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 685305 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 685305 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1416 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1353 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2769 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 1332151500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 8591784000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20339206000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6363 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3499 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 18694 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1664516 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1664516 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1398 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1367 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 149966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 146244 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296210 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 842240 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 854379 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1696619 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 258557 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 267175 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 525732 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 6168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3132 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 842240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 408523 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6234 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3377 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 854379 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 413419 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2537472 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3132 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 842240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 408523 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6234 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3377 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 854379 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 413419 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2537472 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000481 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000296 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992938 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989653 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991333 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 148078 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 147783 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295861 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 840448 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855321 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1695769 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 260404 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 263289 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 523693 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5810 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 840448 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 408482 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3499 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855321 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 411072 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534017 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5810 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 840448 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 408482 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3499 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855321 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 411072 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534017 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000428 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989986 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.993416 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.462058 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.406861 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.434806 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009565 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011585 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010582 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.023519 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.023191 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023352 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.184504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000481 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000296 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011585 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.158911 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062674 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.184504 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000481 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000296 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011585 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.158911 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062674 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 137333.333333 # average ReadReq miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.453990 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.417423 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.435725 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009271 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011910 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010602 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025203 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021300 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023241 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009271 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.180642 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011910 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.163709 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062775 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009271 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.180642 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011910 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.163709 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062775 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 134500 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 574.324324 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 783.420463 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 676.320583 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 132750 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 757.586705 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 595.729013 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 677.425237 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126781.514727 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127326.893666 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127033.472056 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130446.933962 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130738.886644 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 130607.886822 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132228.169709 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131606.601033 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 131914.474220 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 130446.933962 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 127220.938255 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137333.333333 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126824.829679 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127354.534107 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127078.304141 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130547.099589 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130769.755571 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 130673.257690 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132722.763980 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131158.612696 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 132002.054063 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 130547.099589 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 127349.408448 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 130738.886644 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127730.520420 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127814.183220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 130446.933962 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 127220.938255 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 130769.755571 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 127671.540656 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 127861.634983 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 130547.099589 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 127349.408448 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 130738.886644 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127730.520420 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127814.183220 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 130769.755571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 127671.540656 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 127861.634983 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1647,237 +1658,237 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81267 # number of writebacks -system.l2c.writebacks::total 81267 # number of writebacks +system.l2c.writebacks::writebacks 81184 # number of writebacks +system.l2c.writebacks::total 81184 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 8 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1406 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1339 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2745 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1384 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1358 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 69293 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 59501 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128794 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8056 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9898 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 17954 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6081 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6196 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 12277 # number of ReadSharedReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67226 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 61688 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128914 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7792 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10187 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6563 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5608 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 12171 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 75374 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7792 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73789 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9898 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 65697 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 159033 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10187 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 67296 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 159072 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 75374 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7792 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73789 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9898 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 65697 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 159033 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10187 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 67296 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 159072 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15125 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15006 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16013 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16132 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13276 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14313 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13389 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14200 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28401 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28395 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30326 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30332 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 491000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 382000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 490500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 368500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 996000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 99569000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94780500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 194349500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 982000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 98005000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 96151000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 194156000 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8092141500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6981067500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15073209000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 970320500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1195073500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 2165394000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 743269500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 753474500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1496744000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 491000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 970320500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 8835411000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 382000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7853666000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7239366500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15093032500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 939303000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1230281500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 2169584500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 805429500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 679457500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1484887000 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 490500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 939303000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 8659095500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 368500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 1195073500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7734542000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 18736343000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 491000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 970320500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 8835411000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 382000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 1230281500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 7918824000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18748486000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 490500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 939303000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 8659095500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 368500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 1195073500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7734542000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 18736343000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 1230281500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 7918824000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18748486000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 643340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2687706500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2861588500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2859824000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6577648500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2152674000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2321500000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4474174000 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3028128000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6919834500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2340936000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431594500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4772530500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4840380500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5202524500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5181324000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11051822500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.992938 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989653 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991333 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459722500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11692365000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989986 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.993416 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.462058 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.406861 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.434806 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010582 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023519 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023191 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023352 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062674 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009565 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.184504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000481 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011585 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.158911 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062674 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453990 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417423 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435725 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010602 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025203 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021300 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023241 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062775 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062775 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 124500 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70817.211949 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70784.540702 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70801.275046 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116781.514727 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117326.893666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117033.472056 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120607.886822 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122228.169709 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121606.601033 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 121914.474220 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120446.933962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117220.938255 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120738.886644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117730.520420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117814.183220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177699.603306 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178593.892462 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163786.068227 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162147.785478 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162195.207154 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162172.387546 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 170429.932045 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 170854.184528 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 163128.939173 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70627 # Transaction distribution +system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 117457 # Transaction distribution -system.membus.trans_dist::CleanEvict 6338 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution +system.membus.trans_dist::CleanEvict 6393 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 127036 # Transaction distribution -system.membus.trans_dist::ReadExResp 127036 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30467 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::ReadExReq 127159 # Transaction distribution +system.membus.trans_dist::ReadExResp 127159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546371 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546415 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655265 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15304828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15468181 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465557 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17785301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782677 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389991 # Request fanout histogram +system.membus.snoop_fanout::samples 390002 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389991 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390002 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389991 # Request fanout histogram -system.membus.reqLayer0.occupancy 90490000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390002 # Request fanout histogram +system.membus.reqLayer0.occupancy 90453500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 821977659 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823113783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952225245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952221498 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64492032 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64071640 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1920,59 +1931,60 @@ system.realview.realview_io.osc_peripheral.clock 41667 system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5059453 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540884 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 582 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 582 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5052869 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2537534 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38120 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 75104 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2297700 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74671 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2294380 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 802762 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1800707 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2769 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801219 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1664516 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 134433 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2771 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296210 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696651 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 525960 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1695803 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523921 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5076713 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18522 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7711721 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108619704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96660573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205355921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176740 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5302052 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018353 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134225 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5074132 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2573976 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18410 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7701313 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215094328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96414109 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311583213 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176501 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2780821 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021276 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144303 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5204742 98.16% 98.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 97310 1.84% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2721656 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59165 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5302052 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3269894500 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 2780821 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4960265000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553998500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2552726500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1279231000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275647499 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12013000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11889000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22931000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22622000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 838105743..cc979e9fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,55 +4,57 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1349307 # Simulator instruction rate (inst/s) -host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34477807791 # Simulator tick rate (ticks/s) -host_mem_usage 659588 # Number of bytes of host memory used -host_seconds 148.27 # Real time elapsed on the host +host_inst_rate 1265336 # Simulator instruction rate (inst/s) +host_op_rate 2590419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32332152611 # Simulator tick rate (ticks/s) +host_mem_usage 659496 # Number of bytes of host memory used +host_seconds 158.11 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 853568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10615616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11497920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 853568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 853568 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9269440 # Number of bytes written to this memory -system.physmem.bytes_written::total 9269440 # Number of bytes written to this memory +system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory +system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165869 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179655 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144835 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144835 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2076545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2249135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1813217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1813217 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2076545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4062352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224308568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.committedInsts 200066731 # Number of instructions committed system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses @@ -110,8 +112,6 @@ system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 409581402 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 1621902 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. @@ -279,6 +279,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 792216 # number of writebacks +system.cpu.icache.writebacks::total 792216 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use @@ -335,22 +337,22 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 106193 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 106204 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2531.452775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.791178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038627 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.159327 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id @@ -359,52 +361,56 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179780 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179780 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779384 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 779384 # number of ReadCleanReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275199 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1284751 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779384 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454979 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2243915 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779384 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454979 # number of overall hits -system.cpu.l2cache.overall_hits::total 2243915 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits +system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134641 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134641 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13338 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13338 # number of ReadCleanReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32163 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 32169 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13338 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166804 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180148 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13338 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166804 # number of overall misses -system.cpu.l2cache.overall_misses::total 180148 # number of overall misses -system.cpu.l2cache.Writeback_accesses::writebacks 1538777 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538777 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses +system.cpu.l2cache.overall_misses::total 180051 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) @@ -427,24 +433,24 @@ system.cpu.l2cache.overall_accesses::cpu.data 1621783 system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428219 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428219 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024601 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024427 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016826 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102852 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074317 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016826 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102852 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,8 +459,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks -system.cpu.l2cache.writebacks::total 98168 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks +system.cpu.l2cache.writebacks::total 98177 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -466,8 +472,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Tr system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution @@ -479,17 +486,17 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 203459 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 203470 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram @@ -497,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -602,16 +609,16 @@ system.iocache.writebacks::writebacks 46667 # nu system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 13857337 # Transaction distribution -system.membus.trans_dist::ReadResp 13903747 # Transaction distribution +system.membus.trans_dist::ReadResp 13903644 # Transaction distribution system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution -system.membus.trans_dist::Writeback 144835 # Transaction distribution -system.membus.trans_dist::CleanEvict 8392 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution -system.membus.trans_dist::ReadExReq 134360 # Transaction distribution -system.membus.trans_dist::ReadExResp 134355 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 46410 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution +system.membus.trans_dist::CleanEvict 8271 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution +system.membus.trans_dist::ReadExReq 134351 # Transaction distribution +system.membus.trans_dist::ReadExResp 134346 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution system.membus.trans_dist::MessageResp 1696 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution @@ -620,32 +627,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17793920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43218681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14256770 # Request fanout histogram +system.membus.snoop_fanout::samples 14256561 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14256770 # Request fanout histogram +system.membus.snoop_fanout::total 14256561 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 75f6b48c4..8281393dd 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.194921 # Number of seconds simulated -sim_ticks 5194921252500 # Number of ticks simulated -final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194978 # Number of seconds simulated +sim_ticks 5194978362500 # Number of ticks simulated +final_tick 5194978362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 334832 # Simulator instruction rate (inst/s) -host_op_rate 645401 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13521111808 # Simulator tick rate (ticks/s) -host_mem_usage 605972 # Number of bytes of host memory used -host_seconds 384.21 # Real time elapsed on the host -sim_insts 128645145 # Number of instructions simulated -sim_ops 247968363 # Number of ops (including micro ops) simulated +host_inst_rate 1008714 # Simulator instruction rate (inst/s) +host_op_rate 1944281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40800285815 # Simulator tick rate (ticks/s) +host_mem_usage 616472 # Number of bytes of host memory used +host_seconds 127.33 # Real time elapsed on the host +sim_insts 128436556 # Number of instructions simulated +sim_ops 247559471 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 824576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8975232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 821184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9031104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9828480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 824576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 824576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8074432 # Number of bytes written to this memory -system.physmem.bytes_written::total 8074432 # Number of bytes written to this memory +system.physmem.bytes_read::total 9881024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 821184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8151488 # Number of bytes written to this memory +system.physmem.bytes_written::total 8151488 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12884 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140238 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141111 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153570 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126163 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154391 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127367 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1727694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1891940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1554293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1554293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1554293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1902034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1569109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1569109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1569109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1727694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3446234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153570 # Number of read requests accepted -system.physmem.writeReqs 126163 # Number of write requests accepted -system.physmem.readBursts 153570 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 126163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9818304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue -system.physmem.bytesWritten 8073216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9828480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8074432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 3471143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154391 # Number of read requests accepted +system.physmem.writeReqs 127367 # Number of write requests accepted +system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127367 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9871424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 8149376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9881024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8151488 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48373 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9606 # Per bank write bursts -system.physmem.perBankRdBursts::1 9083 # Per bank write bursts -system.physmem.perBankRdBursts::2 10021 # Per bank write bursts -system.physmem.perBankRdBursts::3 9578 # Per bank write bursts -system.physmem.perBankRdBursts::4 9425 # Per bank write bursts -system.physmem.perBankRdBursts::5 9133 # Per bank write bursts -system.physmem.perBankRdBursts::6 9428 # Per bank write bursts -system.physmem.perBankRdBursts::7 9379 # Per bank write bursts -system.physmem.perBankRdBursts::8 9296 # Per bank write bursts -system.physmem.perBankRdBursts::9 9532 # Per bank write bursts -system.physmem.perBankRdBursts::10 9485 # Per bank write bursts -system.physmem.perBankRdBursts::11 9788 # Per bank write bursts -system.physmem.perBankRdBursts::12 9982 # Per bank write bursts -system.physmem.perBankRdBursts::13 10070 # Per bank write bursts -system.physmem.perBankRdBursts::14 9926 # Per bank write bursts -system.physmem.perBankRdBursts::15 9679 # Per bank write bursts -system.physmem.perBankWrBursts::0 8208 # Per bank write bursts -system.physmem.perBankWrBursts::1 7344 # Per bank write bursts -system.physmem.perBankWrBursts::2 8031 # Per bank write bursts -system.physmem.perBankWrBursts::3 7623 # Per bank write bursts -system.physmem.perBankWrBursts::4 7645 # Per bank write bursts -system.physmem.perBankWrBursts::5 7565 # Per bank write bursts -system.physmem.perBankWrBursts::6 7708 # Per bank write bursts -system.physmem.perBankWrBursts::7 7791 # Per bank write bursts -system.physmem.perBankWrBursts::8 7759 # Per bank write bursts -system.physmem.perBankWrBursts::9 7930 # Per bank write bursts -system.physmem.perBankWrBursts::10 7732 # Per bank write bursts -system.physmem.perBankWrBursts::11 7853 # Per bank write bursts -system.physmem.perBankWrBursts::12 8038 # Per bank write bursts -system.physmem.perBankWrBursts::13 8512 # Per bank write bursts -system.physmem.perBankWrBursts::14 8378 # Per bank write bursts -system.physmem.perBankWrBursts::15 8027 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 55287 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10087 # Per bank write bursts +system.physmem.perBankRdBursts::1 9529 # Per bank write bursts +system.physmem.perBankRdBursts::2 9814 # Per bank write bursts +system.physmem.perBankRdBursts::3 9652 # Per bank write bursts +system.physmem.perBankRdBursts::4 10130 # Per bank write bursts +system.physmem.perBankRdBursts::5 9950 # Per bank write bursts +system.physmem.perBankRdBursts::6 9317 # Per bank write bursts +system.physmem.perBankRdBursts::7 9200 # Per bank write bursts +system.physmem.perBankRdBursts::8 8918 # Per bank write bursts +system.physmem.perBankRdBursts::9 9357 # Per bank write bursts +system.physmem.perBankRdBursts::10 9066 # Per bank write bursts +system.physmem.perBankRdBursts::11 9331 # Per bank write bursts +system.physmem.perBankRdBursts::12 9713 # Per bank write bursts +system.physmem.perBankRdBursts::13 9915 # Per bank write bursts +system.physmem.perBankRdBursts::14 10131 # Per bank write bursts +system.physmem.perBankRdBursts::15 10131 # Per bank write bursts +system.physmem.perBankWrBursts::0 8252 # Per bank write bursts +system.physmem.perBankWrBursts::1 7742 # Per bank write bursts +system.physmem.perBankWrBursts::2 7578 # Per bank write bursts +system.physmem.perBankWrBursts::3 7566 # Per bank write bursts +system.physmem.perBankWrBursts::4 7987 # Per bank write bursts +system.physmem.perBankWrBursts::5 8326 # Per bank write bursts +system.physmem.perBankWrBursts::6 7980 # Per bank write bursts +system.physmem.perBankWrBursts::7 7858 # Per bank write bursts +system.physmem.perBankWrBursts::8 7446 # Per bank write bursts +system.physmem.perBankWrBursts::9 8118 # Per bank write bursts +system.physmem.perBankWrBursts::10 7706 # Per bank write bursts +system.physmem.perBankWrBursts::11 7948 # Per bank write bursts +system.physmem.perBankWrBursts::12 8417 # Per bank write bursts +system.physmem.perBankWrBursts::13 8510 # Per bank write bursts +system.physmem.perBankWrBursts::14 8023 # Per bank write bursts +system.physmem.perBankWrBursts::15 7877 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 5194921069000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5194978301500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153570 # Read request sizes (log2) +system.physmem.readPktSize::6 154391 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127367 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -152,190 +156,192 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.678668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.248377 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.031309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19371 34.61% 34.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13720 24.51% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6335 11.32% 70.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3428 6.13% 76.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2404 4.30% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1641 2.93% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1130 2.02% 85.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 964 1.72% 87.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6974 12.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55967 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5838 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.276465 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 626.709863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5837 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.998481 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.316521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20120 35.39% 35.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13756 24.20% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3490 6.14% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2421 4.26% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1596 2.81% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 976 1.72% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6990 12.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 623.896687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5890 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5838 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5838 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.607400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.425561 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.518520 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4794 82.12% 82.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 110 1.88% 84.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 38 0.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 229 3.92% 88.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 28 0.48% 89.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 201 3.44% 92.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 72 1.23% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 93.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.21% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 30 0.51% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.12% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 233 3.99% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 31 0.53% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.27% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5838 # Writes before turning the bus around for reads -system.physmem.totQLat 1519267484 # Total ticks spent queuing -system.physmem.totMemAccLat 4395723734 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 767055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9903.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5891 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.615006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.434725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.404388 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4837 82.11% 82.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 110 1.87% 83.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 36 0.61% 84.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 4.11% 88.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 18 0.31% 89.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 210 3.56% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 69 1.17% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.05% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.22% 94.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.37% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.14% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 244 4.14% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.08% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.46% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 18 0.31% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads +system.physmem.totQLat 1582264251 # Total ticks spent queuing +system.physmem.totMemAccLat 4474283001 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10258.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28653.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.55 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29008.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.23 # Average write queue length when enqueuing -system.physmem.readRowHits 125316 # Number of row buffer hits during reads -system.physmem.writeRowHits 98271 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.89 # Row buffer hit rate for writes -system.physmem.avgGap 18570998.31 # Average gap between requests -system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 205775640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 112278375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136710415665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2997028284750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3474354711990 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.798995 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4985717890976 # Time in different power states -system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 125535 # Number of row buffer hits during reads +system.physmem.writeRowHits 99190 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes +system.physmem.avgGap 18437731.32 # Average gap between requests +system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 210712320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114972000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 137072385045 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2996748141750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474472943475 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.813734 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985245725974 # Time in different power states +system.physmem_0.memoryStateTime::REF 173471480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35728632774 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36261007776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 137303660835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2996507894250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3474476838945 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.822504 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4984854148228 # Time in different power states -system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states +system.physmem_1.actEnergy 219073680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119534250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137522699865 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996353144500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474537370935 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826133 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984581893484 # Time in different power states +system.physmem_1.memoryStateTime::REF 173471480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36597272272 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36924866266 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10389842505 # number of cpu cycles simulated +system.cpu.numCycles 10389956725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.committedInsts 128645145 # Number of instructions committed -system.cpu.committedOps 247968363 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232546069 # Number of integer alu accesses +system.cpu.committedInsts 128436556 # Number of instructions committed +system.cpu.committedOps 247559471 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232158304 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2315361 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls -system.cpu.num_int_insts 232546069 # number of integer instructions +system.cpu.num_func_calls 2315823 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23152915 # number of instructions that are conditional controls +system.cpu.num_int_insts 232158304 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435625855 # number of times the integer registers were read -system.cpu.num_int_register_writes 198317568 # number of times the integer registers were written +system.cpu.num_int_register_reads 434959162 # number of times the integer registers were read +system.cpu.num_int_register_writes 197962951 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133116486 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95666126 # number of times the CC registers were written -system.cpu.num_mem_refs 22339097 # number of memory refs -system.cpu.num_load_insts 13935932 # Number of load instructions -system.cpu.num_store_insts 8403165 # Number of store instructions -system.cpu.num_idle_cycles 9774871371.998117 # Number of idle cycles -system.cpu.num_busy_cycles 614971133.001882 # Number of busy cycles -system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940810 # Percentage of idle cycles -system.cpu.Branches 26367781 # Number of branches fetched -system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225200249 90.82% 90.89% # Class of executed instruction -system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 132872909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95460932 # number of times the CC registers were written +system.cpu.num_mem_refs 22321110 # number of memory refs +system.cpu.num_load_insts 13911495 # Number of load instructions +system.cpu.num_store_insts 8409615 # Number of store instructions +system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles +system.cpu.num_busy_cycles 615961190.913881 # Number of busy cycles +system.cpu.not_idle_fraction 0.059284 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940716 # Percentage of idle cycles +system.cpu.Branches 26327381 # Number of branches fetched +system.cpu.op_class::No_OpClass 172225 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 122811 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -362,213 +368,214 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13930960 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8403165 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Class of executed instruction +system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247969924 # Class of executed instruction -system.cpu.dcache.tags.replacements 1623328 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20131141 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.397244 # Average number of references to valid blocks. +system.cpu.op_class::total 247561007 # Class of executed instruction +system.cpu.dcache.tags.replacements 1623701 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20139430 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624213 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.399501 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88683226 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88683226 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12000892 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12000892 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8069414 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8069414 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58662 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58662 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20070306 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20070306 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20128968 # number of overall hits -system.cpu.dcache.overall_hits::total 20128968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403210 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403210 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1232655 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1232655 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1635865 # number of overall misses -system.cpu.dcache.overall_misses::total 1635865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13550557000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13550557000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18295357977 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18295357977 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31845914977 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31845914977 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31845914977 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31845914977 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12907775 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12907775 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8395186 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8395186 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21302961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21302961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21764833 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21764833 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070259 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070259 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038805 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038805 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872991 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872991 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057863 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057863 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075161 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075161 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14941.902098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14941.902098 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56160.007542 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56160.007542 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25835.221515 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25835.221515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19467.324612 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19467.324612 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15094 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88718098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88718098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12002647 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12002647 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075474 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075474 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20078121 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20078121 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20137213 # number of overall hits +system.cpu.dcache.overall_hits::total 20137213 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326145 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326145 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402797 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402797 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1233455 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1233455 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636252 # number of overall misses +system.cpu.dcache.overall_misses::total 1636252 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562374500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13562374500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18447994471 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18447994471 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32010368971 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32010368971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32010368971 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32010368971 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12909957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12909957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401619 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401619 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461889 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461889 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21311576 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21311576 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21773465 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21773465 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070280 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070280 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038819 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872065 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872065 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057877 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.894876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.894876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56563.781358 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56563.781358 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.793110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25951.793110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.226796 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19563.226796 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 441 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.226757 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540461 # number of writebacks -system.cpu.dcache.writebacks::total 1540461 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 292 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9470 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9470 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9762 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9762 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9762 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9762 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906591 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906591 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316302 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316302 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403174 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 403174 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1222893 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1222893 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626067 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626067 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable +system.cpu.dcache.writebacks::writebacks 1540806 # number of writebacks +system.cpu.dcache.writebacks::total 1540806 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9476 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9476 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9763 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9763 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9763 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9763 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907023 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907023 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316669 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316669 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1223692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1223692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626455 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626455 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12641489000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12641489000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17000944477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17000944477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6508610000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6508610000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29642433477 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29642433477 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36151043477 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36151043477 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684331000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684331000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622740500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622740500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97307071500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97307071500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070236 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070236 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037677 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872913 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872913 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057405 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074711 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074711 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.982457 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.982457 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53749.089405 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53749.089405 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16143.426907 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16143.426907 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24239.596986 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24239.596986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22232.197983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22232.197983 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.427218 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.427218 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188415.265805 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188415.265805 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165805.729168 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165805.729168 # average overall mshr uncacheable latency +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12653263500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12653263500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148578471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148578471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801841971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29801841971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318300471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36318300471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95164003500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95164003500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97950308000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97950308000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13950.322649 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13950.322649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54153.006676 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54153.006676 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16179.387133 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16179.387133 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.038411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.038411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22329.729670 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22329.729670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174182.667211 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174182.667211 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174828.220881 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174828.220881 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7724 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13169 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7738 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.701861 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5166372049500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163389935000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13186 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13186 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13186 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13186 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13186 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13186 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8927 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8927 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8927 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8927 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8927 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8927 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97243000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97243000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97243000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 97243000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97243000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 97243000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22113 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22113 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22113 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22113 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22113 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22113 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403699 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403699 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403699 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403699 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403699 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403699 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10893.133191 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10893.133191 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10893.133191 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10893.133191 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53077 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53077 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13349 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13349 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13349 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13349 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13349 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13349 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8793 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8793 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8793 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8793 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8793 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8793 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96493000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96493000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96493000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 96493000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96493000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 96493000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22142 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22142 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22142 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22142 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22142 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22142 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397119 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397119 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397119 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397119 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397119 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397119 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,86 +584,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2877 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2877 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8927 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8927 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8927 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8927 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8927 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8927 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88316000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88316000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88316000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88316000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88316000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.403699 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.403699 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.403699 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.403699 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9893.133191 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9893.133191 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9893.133191 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8793 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8793 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8793 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8793 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8793 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8793 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87700000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87700000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87700000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87700000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87700000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87700000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397119 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397119 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397119 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9973.842830 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 789867 # number of replacements -system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144930125 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 183.367884 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996513 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 790533 # number of replacements +system.cpu.icache.tags.tagsinuse 510.212427 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144635656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.841249 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164582664500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.212427 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996509 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996509 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146510897 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146510897 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144930125 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144930125 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144930125 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144930125 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144930125 # number of overall hits -system.cpu.icache.overall_hits::total 144930125 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 790386 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 790386 # number of overall misses -system.cpu.icache.overall_misses::total 790386 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11833714500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11833714500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11833714500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11833714500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11833714500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11833714500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145720511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145720511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145720511 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145720511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145720511 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145720511 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005424 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005424 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005424 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14972.069976 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14972.069976 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14972.069976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14972.069976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14972.069976 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146217760 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146217760 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144635656 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144635656 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144635656 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144635656 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144635656 # number of overall hits +system.cpu.icache.overall_hits::total 144635656 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791052 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791052 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791052 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791052 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791052 # number of overall misses +system.cpu.icache.overall_misses::total 791052 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11850841500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11850841500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11850841500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11850841500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11850841500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11850841500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145426708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145426708 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145426708 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145426708 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145426708 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145426708 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.115654 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14981.115654 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14981.115654 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14981.115654 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,88 +672,90 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790386 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 790386 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 790386 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 790386 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 790386 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 790386 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11043328500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11043328500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11043328500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11043328500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11043328500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11043328500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005424 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005424 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005424 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005424 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13972.069976 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13972.069976 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13972.069976 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13972.069976 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 790533 # number of writebacks +system.cpu.icache.writebacks::total 790533 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791052 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791052 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791052 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791052 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791052 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791052 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11059789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11059789500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11059789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11059789500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11059789500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11059789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.115654 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.115654 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3784 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.071212 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7587 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3797 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.998156 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5168596607500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071212 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191951 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191951 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.069439 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5168995728500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069439 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191840 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191840 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29077 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29077 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7587 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7587 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 28685 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28685 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7970 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7970 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7589 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7589 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7589 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7589 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4633 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4633 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4633 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4633 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4633 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4633 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48911500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48911500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48911500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 48911500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48911500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 48911500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7972 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7972 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7972 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7972 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4247 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4247 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4247 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4247 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4247 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4247 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44886000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44886000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.379133 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.379133 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.379071 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.379071 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.379071 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.379071 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10557.198360 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10557.198360 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10557.198360 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10557.198360 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10557.198360 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.347630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.347630 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.347573 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.347573 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.347573 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.347573 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10568.872145 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10568.872145 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10568.872145 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10568.872145 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,169 +764,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 721 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 721 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4633 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4633 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4633 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4633 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4633 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4633 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 44278500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 44278500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 44278500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 44278500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 44278500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 44278500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.379133 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.379133 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.379071 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.379071 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.379071 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9557.198360 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9557.198360 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9557.198360 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40639000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40639000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40639000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40639000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40639000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40639000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.347630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.347630 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.347573 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9568.872145 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 86240 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64592.333945 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4367637 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 150989 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.926856 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87285 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64590.293077 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4366421 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151981 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.730045 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50133.527739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146857 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3457.643805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11001.015544 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.764977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50117.072106 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006346 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146905 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.574017 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.493703 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764726 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167862 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.985601 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64749 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56598 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39213781 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39213781 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1544059 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1544059 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 298 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 298 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 201469 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 201469 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 777488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 777488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6514 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3101 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280565 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1290180 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6514 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3101 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 777488 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1482034 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2269137 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6514 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3101 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 777488 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1482034 # number of overall hits -system.cpu.l2cache.overall_hits::total 2269137 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 112654 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 112654 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12885 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12885 # number of ReadCleanReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.168816 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2800 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56265 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39229745 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39229745 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1544563 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1544563 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 790520 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 790520 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200934 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200934 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 778207 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 778207 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6472 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2856 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280544 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1289872 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6472 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2856 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 778207 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1481478 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2269013 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6472 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2856 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 778207 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1481478 # number of overall hits +system.cpu.l2cache.overall_hits::total 2269013 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113512 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113512 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12832 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12832 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28510 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28515 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28494 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28500 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12885 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141164 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142006 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154844 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12885 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141164 # number of overall misses -system.cpu.l2cache.overall_misses::total 154054 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 55378500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 55378500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14292640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14292640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1690999500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1690999500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 12832 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142006 # number of overall misses +system.cpu.l2cache.overall_misses::total 154844 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 53960000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 53960000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14442230500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14442230500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1691982000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1691982000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 147000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 637500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3736922500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3737560000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3748921500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749706000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 147000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 637500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1690999500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18029562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19721199500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1691982000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18191152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19883918500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 147000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 637500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1690999500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18029562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19721199500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 1544059 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1544059 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1692 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314123 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 790373 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 790373 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 3106 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309075 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1318695 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6514 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3106 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 790373 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1623198 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2423191 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6514 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3106 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 790373 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1623198 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2423191 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823877 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823877 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358630 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.358630 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016302 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016302 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001610 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021779 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021624 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016302 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.086967 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063575 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016302 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.086967 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063575 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39726.327116 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39726.327116 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 126872.015197 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 126872.015197 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131237.834692 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131237.834692 # average ReadCleanReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 1691982000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18191152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19883918500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544563 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1544563 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 790520 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 790520 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1726 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1726 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314446 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314446 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 791039 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 791039 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6473 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2861 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309038 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1318372 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6473 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2861 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 791039 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623484 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423857 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6473 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2861 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791039 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623484 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423857 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.360990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016222 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016222 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001748 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021767 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021618 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001748 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016222 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087470 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063883 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001748 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016222 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087470 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063883 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127230.869864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127230.869864 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131856.452618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131856.452618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147000 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131074.096808 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131073.470103 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131568.803959 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131568.631579 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131237.834692 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127720.683035 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 128014.848689 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 128412.586216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131237.834692 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127720.683035 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 128014.848689 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 128412.586216 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -926,157 +953,170 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 79496 # number of writebacks -system.cpu.l2cache.writebacks::total 79496 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 19 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 19 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1394 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1394 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112654 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 112654 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12885 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12885 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80700 # number of writebacks +system.cpu.l2cache.writebacks::total 80700 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12832 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12832 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 1 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28510 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28515 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28494 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28500 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12885 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12832 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142006 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154844 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12885 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154054 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12832 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142006 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154844 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 586874 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 586874 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 99511500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 99511500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13166100000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13166100000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1562149500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1562149500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100407500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13307110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13307110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1563662000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1563662000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 137000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3451822500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3452410000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3463981500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464706000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 137000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1562149500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16617922500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1563662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16771092000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18335478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 137000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1562149500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16617922500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180659500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462660500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462660500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89985064500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89985064500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1563662000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16771092000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18335478500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88334673500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88334673500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626222500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626222500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90960896000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90960896000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823877 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823877 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358630 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016302 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021624 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063575 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016302 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086967 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063575 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71385.581062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71385.581062 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 116872.015197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 116872.015197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121237.834692 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121237.834692 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016222 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021767 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021618 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063883 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117230.869864 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117230.869864 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121856.452618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121856.452618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121074.096808 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121073.470103 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121568.803959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121568.631579 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121237.834692 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117720.683035 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118014.848689 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.423727 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.423727 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176915.265805 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176915.265805 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.444651 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.444651 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161682.658059 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161682.658059 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162353.053728 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162353.053728 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4854729 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2424193 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1088 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1088 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4855760 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425141 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2686987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2660535 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1670227 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2186 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 790386 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1671932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323668 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2370613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6047740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9205 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19678 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8447236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50583872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204138427 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 601024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255568251 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 188441 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5624579 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.080591 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8396398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 306160808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 189298 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3174836 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5604820 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 14130 0.25% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 5629 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3163102 99.63% 99.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5624579 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4271820500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3174836 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5050069000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 588787 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1185579000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3016848998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2990781992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6949500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13390500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13189500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 226550 # Transaction distribution -system.iobus.trans_dist::ReadResp 226550 # Transaction distribution +system.iobus.trans_dist::ReadReq 216035 # Transaction distribution +system.iobus.trans_dist::ReadResp 216035 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 57726 # Transaction distribution system.iobus.trans_dist::MessageReq 1654 # Transaction distribution @@ -1089,7 +1129,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 429188 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1099,12 +1139,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 571860 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1113,7 +1153,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 214594 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1123,96 +1163,96 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276918 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4013816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 149500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 1094500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 79000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 50500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 214595000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 306124500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 1113000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 24284500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 240989862 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 240815899 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer20.occupancy 1067000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50044000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47511 # number of replacements -system.iocache.tags.tagsinuse 0.108299 # Cycle average of tags in use +system.iocache.tags.replacements 47507 # number of replacements +system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5048321264000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108299 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006769 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5048362105000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428094 # Number of tag accesses -system.iocache.tags.data_accesses 428094 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 846 # number of ReadReq misses +system.iocache.tags.tag_accesses 428058 # Number of tag accesses +system.iocache.tags.data_accesses 428058 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 842 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses -system.iocache.demand_misses::total 846 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses -system.iocache.overall_misses::total 846 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144199688 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144199688 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6059543174 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6059543174 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144199688 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144199688 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144199688 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144199688 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses +system.iocache.demand_misses::total 842 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses +system.iocache.overall_misses::total 842 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141163690 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141163690 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6072614209 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6072614209 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141163690 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141163690 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141163690 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141163690 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1221,40 +1261,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170448.803783 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129699.126156 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129699.126156 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170448.803783 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170448.803783 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170448.803783 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 693 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167652.838480 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167652.838480 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167652.838480 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 694 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 36 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 67 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 19.250000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.358209 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101899688 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3723543174 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3723543174 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101899688 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101899688 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101899688 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 99063690 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3736614209 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3736614209 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 99063690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 99063690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1263,73 +1303,73 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 120448.803783 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79699.126156 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79699.126156 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 120448.803783 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 120448.803783 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 572954 # Transaction distribution -system.membus.trans_dist::ReadResp 615200 # Transaction distribution +system.membus.trans_dist::ReadReq 546346 # Transaction distribution +system.membus.trans_dist::ReadResp 588520 # Transaction distribution system.membus.trans_dist::WriteReq 13920 # Transaction distribution system.membus.trans_dist::WriteResp 13920 # Transaction distribution -system.membus.trans_dist::Writeback 126163 # Transaction distribution -system.membus.trans_dist::CleanEvict 7113 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2165 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1671 # Transaction distribution -system.membus.trans_dist::ReadExReq 112377 # Transaction distribution -system.membus.trans_dist::ReadExResp 112377 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42246 # Transaction distribution +system.membus.trans_dist::WritebackDirty 127367 # Transaction distribution +system.membus.trans_dist::CleanEvict 6933 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution +system.membus.trans_dist::ReadExReq 113266 # Transaction distribution +system.membus.trans_dist::ReadExResp 113266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42174 # Transaction distribution system.membus.trans_dist::MessageReq 1654 # Transaction distribution system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 396961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1570709 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1715783 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 399599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1520131 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1665201 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400653 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14887872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16531515 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586216 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19553171 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1565 # Total snoops (count) -system.membus.snoop_fanout::samples 925791 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001787 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042230 # Request fanout histogram +system.membus.pkt_size::total 19607872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1571 # Total snoops (count) +system.membus.snoop_fanout::samples 901008 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 924137 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::1 899354 99.82% 99.82% # Request fanout histogram system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 925791 # Request fanout histogram -system.membus.reqLayer0.occupancy 359890000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 901008 # Request fanout histogram +system.membus.reqLayer0.occupancy 344294500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527983500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 503567500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 843164843 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 852595093 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2152042345 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1928197366 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85908558 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |