diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/fs/10.linux-boot | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
15 files changed, 3447 insertions, 3437 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 090f52454..b6c3eb879 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -279,7 +279,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -341,7 +341,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -398,7 +398,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 4abaeca9d..e633d965f 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:10 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:09:26 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 562628000 -Exiting @ tick 1957577582000 because m5_exit instruction encountered +info: Launching CPU 1 @ 573593000 +Exiting @ tick 1954209106000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9611b47c5..e64aeb301 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.957578 # Number of seconds simulated -sim_ticks 1957577582000 # Number of ticks simulated -final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954209 # Number of seconds simulated +sim_ticks 1954209106000 # Number of ticks simulated +final_tick 1954209106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1866861 # Simulator instruction rate (inst/s) -host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61595044213 # Simulator tick rate (ticks/s) -host_mem_usage 296940 # Number of bytes of host memory used -host_seconds 31.78 # Real time elapsed on the host -sim_insts 59331415 # Number of instructions simulated -sim_ops 59331415 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory -system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 340832 # number of replacements -system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use -system.l2c.total_refs 2492123 # Total number of references to valid blocks. -system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits -system.l2c.Writeback_hits::total 821051 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 34 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172323 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12709 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185032 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 943723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 46441 # number of demand (read+write) hits -system.l2c.demand_hits::total 1978815 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902441 # number of overall hits -system.l2c.overall_hits::cpu0.data 943723 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86210 # number of overall hits -system.l2c.overall_hits::cpu1.data 46441 # number of overall hits -system.l2c.overall_hits::total 1978815 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12906 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271613 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 596 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 192 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285307 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 486 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2939 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 16 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 72 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 88 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115483 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6047 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121530 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12906 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387096 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 596 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6239 # number of demand (read+write) misses -system.l2c.demand_misses::total 406837 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12906 # number of overall misses -system.l2c.overall_misses::cpu0.data 387096 # number of overall misses -system.l2c.overall_misses::cpu1.inst 596 # number of overall misses -system.l2c.overall_misses::cpu1.data 6239 # number of overall misses -system.l2c.overall_misses::total 406837 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 671157500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14128859000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 30971000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 10024000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14841011500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2088000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 624000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2712000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 260000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 468000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6005389000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 314450000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6319839000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 671157500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20134248000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 30971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 324474000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21160850500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 671157500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20134248000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 30971000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 324474000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21160850500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915347 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1043013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 86806 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 33924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2079090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 821051 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 821051 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2619 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 540 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 30 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 287806 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18756 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915347 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1330819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 86806 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 52680 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2385652 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915347 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1330819 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 86806 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 52680 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2385652 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014100 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.260412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.005660 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137227 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.936617 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.900000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930358 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.533333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.782609 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.721311 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.401253 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.322403 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.396429 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290871 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006866 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.118432 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170535 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290871 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006866 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.118432 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170535 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52017.691469 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 851.202609 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1283.950617 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 922.762845 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16250 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2888.888889 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5318.181818 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.295729 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52013.092467 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52013.092467 # average overall miss latency +host_inst_rate 1820229 # Simulator instruction rate (inst/s) +host_op_rate 1820228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59866957581 # Simulator tick rate (ticks/s) +host_mem_usage 296900 # Number of bytes of host memory used +host_seconds 32.64 # Real time elapsed on the host +sim_insts 59416827 # Number of instructions simulated +sim_ops 59416827 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory +system.physmem.bytes_read::total 28734208 # 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number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7626020806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7626020806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7647034804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7647034804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7647034804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7647034804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183529.572728 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183259.077933 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183259.077933 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7245000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7076 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1023.883550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41531 # number of writebacks +system.iocache.writebacks::total 41531 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465163000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5465163000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5477024000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5477024000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5477024000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5477024000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8630502 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6043026 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14673528 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3852973 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses -system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856844 # ITB accesses +system.cpu0.dtb.read_hits 5733478 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.write_hits 3961950 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.data_hits 9695428 # DTB hits +system.cpu0.dtb.data_misses 8485 # DTB misses +system.cpu0.dtb.data_acv 289 # DTB access violations +system.cpu0.dtb.data_accesses 719860 # DTB accesses +system.cpu0.itb.fetch_hits 3214168 # ITB hits +system.cpu0.itb.fetch_misses 3841 # ITB misses +system.cpu0.itb.fetch_acv 143 # ITB acv +system.cpu0.itb.fetch_accesses 3218009 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,117 +480,118 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3914070794 # number of cpu cycles simulated +system.cpu0.numCycles 3908418212 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54051547 # Number of instructions committed -system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426247 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50023130 # number of integer instructions -system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14719518 # number of memory refs -system.cpu0.num_load_insts 8661793 # Number of load instructions -system.cpu0.num_store_insts 6057725 # Number of store instructions -system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles -system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles +system.cpu0.committedInsts 36160823 # Number of instructions committed +system.cpu0.committedOps 36160823 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33648358 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses +system.cpu0.num_func_calls 874754 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239281 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33648358 # number of integer instructions +system.cpu0.num_fp_insts 143029 # number of float instructions +system.cpu0.num_int_register_reads 46246578 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25142775 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written +system.cpu0.num_mem_refs 9726012 # number of memory refs +system.cpu0.num_load_insts 5755191 # Number of load instructions +system.cpu0.num_store_insts 3970821 # Number of store instructions +system.cpu0.num_idle_cycles 3741416410.998085 # Number of idle cycles +system.cpu0.num_busy_cycles 167001801.001915 # Number of busy cycles +system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 129052 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1971 1.84% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 63918 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107049 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1905787793000 97.52% 97.52% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 88207500 0.00% 97.53% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 590484500 0.03% 97.56% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 47728938000 2.44% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954208250000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.634626 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777812 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 224 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed -system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188201 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101151 88.59% 90.44% # number of callpals executed +system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed +system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 114173 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1229 +system.cpu0.kern.mode_good::user 1230 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.230885 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.375248 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950524029000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3684214000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3895 # number of times the context was actually changed +system.cpu0.kern.swap_context 1960 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -622,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914734 # number of replacements -system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use -system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits -system.cpu0.icache.overall_hits::total 53144779 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses -system.cpu0.icache.overall_misses::total 915368 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.replacements 489211 # number of replacements +system.cpu0.icache.tagsinuse 508.795621 # Cycle average of tags in use +system.cpu0.icache.total_refs 35679745 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 489723 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 72.856993 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.795621 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 35679745 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35679745 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35679745 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35679745 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35679745 # number of overall hits +system.cpu0.icache.overall_hits::total 35679745 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 489853 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 489853 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 489853 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 489853 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 489853 # number of overall misses +system.cpu0.icache.overall_misses::total 489853 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462564000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7462564000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7462564000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7462564000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7462564000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7462564000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169598 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36169598 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36169598 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36169598 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36169598 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36169598 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15234.292737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15234.292737 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,114 +676,114 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 55 # number of writebacks -system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 58 # number of writebacks +system.cpu0.icache.writebacks::total 58 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489853 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 489853 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 489853 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 489853 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 489853 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 489853 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992343500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992343500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992343500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5992343500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992343500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5992343500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits -system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency +system.cpu0.dcache.replacements 817835 # number of replacements +system.cpu0.dcache.tagsinuse 479.881432 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8879650 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 818347 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 10.850715 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 479.881432 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.937268 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.937268 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5008280 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5008280 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3627742 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3627742 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8636022 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636022 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8636022 # number of overall hits +system.cpu0.dcache.overall_hits::total 8636022 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 610615 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 610615 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 207039 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 207039 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 817654 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 817654 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 817654 # number of overall misses +system.cpu0.dcache.overall_misses::total 817654 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940488000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 19940488000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7282919000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7282919000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92852000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92852000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8304000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 8304000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 27223407000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27223407000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 27223407000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27223407000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5618895 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3834781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9453676 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9453676 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9453676 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9453676 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108672 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.108672 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053990 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.053990 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086491 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086491 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086491 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086491 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +792,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks -system.cpu0.dcache.writebacks::total 790358 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # 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mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 359699 # number of writebacks +system.cpu0.dcache.writebacks::total 359699 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610615 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 610615 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207039 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 207039 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 817654 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 817654 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 817654 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817654 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108577524 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108577524 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6661800002 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6661800002 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73166000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73166000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6564000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6564000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24770377526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24770377526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24770377526 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24770377526 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014438500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014438500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615647000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615647000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053990 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053990 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086491 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086491 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +859,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1049963 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651106 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701069 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493400 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494616 # ITB accesses +system.cpu1.dtb.read_hits 3958078 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.write_hits 2742847 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.data_hits 6700925 # DTB hits +system.cpu1.dtb.data_misses 3106 # DTB misses +system.cpu1.dtb.data_acv 84 # DTB access violations +system.cpu1.dtb.data_accesses 302878 # DTB accesses +system.cpu1.itb.fetch_hits 2128502 # ITB hits +system.cpu1.itb.fetch_misses 1246 # ITB misses +system.cpu1.itb.fetch_acv 41 # ITB acv +system.cpu1.itb.fetch_accesses 2129748 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,141 +887,150 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3915155164 # number of cpu cycles simulated +system.cpu1.numCycles 3908222380 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5279868 # Number of instructions committed -system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 157997 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4945263 # number of integer instructions -system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710522 # number of memory refs -system.cpu1.num_load_insts 1055970 # Number of load instructions -system.cpu1.num_store_insts 654552 # Number of store instructions -system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles +system.cpu1.committedInsts 23256004 # Number of instructions committed +system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses +system.cpu1.num_func_calls 709842 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls +system.cpu1.num_int_insts 21401422 # number of integer instructions +system.cpu1.num_fp_insts 186242 # number of float instructions +system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written +system.cpu1.num_mem_refs 6725970 # number of memory refs +system.cpu1.num_load_insts 3973767 # Number of load instructions +system.cpu1.num_store_insts 2752203 # Number of store instructions +system.cpu1.num_idle_cycles 3808684025.637170 # Number of idle cycles +system.cpu1.num_busy_cycles 99538354.362830 # Number of busy cycles +system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1901560823500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 537428500 0.03% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51953872000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954111160000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 102 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed -system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2292 2.22% 2.24% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.01% 2.25% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.26% # number of callpals executed +system.cpu1.kern.callpal::swpipl 94758 91.98% 94.24% # number of callpals executed +system.cpu1.kern.callpal::rdps 2221 2.16% 96.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.41% # number of callpals executed +system.cpu1.kern.callpal::rti 3510 3.41% 99.81% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.16% 99.97% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.03% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29550 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 476 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 103020 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2836 # number of protection mode switches +system.cpu1.kern.mode_switch::user 515 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 568 +system.cpu1.kern.mode_good::user 515 +system.cpu1.kern.mode_good::idle 53 +system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86261 # number of replacements -system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use -system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits -system.cpu1.icache.overall_hits::total 5196422 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses -system.cpu1.icache.overall_misses::total 86809 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016431 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016431 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016431 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14383.399187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14383.399187 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 72316980000 3.70% 3.70% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1607803000 0.08% 3.78% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1879348629000 96.22% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2293 # number of times the context was actually changed +system.cpu1.icache.replacements 513695 # number of replacements +system.cpu1.icache.tagsinuse 501.294136 # Cycle average of tags in use +system.cpu1.icache.total_refs 22744962 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 514207 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 44.233085 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 501.294136 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22744962 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22744962 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22744962 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22744962 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22744962 # number of overall hits +system.cpu1.icache.overall_hits::total 22744962 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 514232 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 514232 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 514232 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 514232 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 514232 # number of overall misses +system.cpu1.icache.overall_misses::total 514232 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551962500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7551962500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7551962500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7551962500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7551962500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7551962500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14685.905389 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14685.905389 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1029,114 +1039,114 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 14 # number of writebacks -system.cpu1.icache.writebacks::total 14 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86809 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 86809 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 86809 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 86809 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 86809 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 86809 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 988145500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 988145500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 988145500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 988145500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 988145500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 988145500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016431 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016431 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11382.984483 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 11 # number of writebacks +system.cpu1.icache.writebacks::total 11 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514232 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 514232 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 514232 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 514232 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 514232 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 514232 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009201500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009201500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009201500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6009201500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009201500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6009201500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 52782 # number of replacements -system.cpu1.dcache.tagsinuse 416.168626 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1644833 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53294 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.863380 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1922770151000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.168626 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.812829 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.812829 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1003125 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1003125 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 616808 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 616808 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11818 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11818 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11519 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11519 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1619933 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1619933 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1619933 # number of overall hits -system.cpu1.dcache.overall_hits::total 1619933 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 36999 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 36999 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 20414 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 20414 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 944 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 944 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 507 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57413 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57413 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57413 # number of overall misses -system.cpu1.dcache.overall_misses::total 57413 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 492506000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 492506000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 549958000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 549958000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 11305000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 11305000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6352000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6352000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1042464000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1042464000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1042464000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1042464000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040124 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1040124 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 637222 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 637222 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12762 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452 # average overall miss latency +system.cpu1.dcache.replacements 642543 # number of replacements +system.cpu1.dcache.tagsinuse 493.349744 # Cycle average of tags in use +system.cpu1.dcache.total_refs 6059288 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 642980 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 9.423758 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 493.349744 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 3370942 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3370942 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2541026 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2541026 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5911968 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5911968 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5911968 # number of overall hits +system.cpu1.dcache.overall_hits::total 5911968 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 513440 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 513440 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 122215 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 122215 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 635655 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 635655 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 635655 # number of overall misses +system.cpu1.dcache.overall_misses::total 635655 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202447500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7202447500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665469000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2665469000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183740000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 183740000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9867916500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9867916500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9867916500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9867916500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045890 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.045890 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1155,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks -system.cpu1.dcache.writebacks::total 30624 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 498964 # number of writebacks +system.cpu1.dcache.writebacks::total 498964 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513440 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 513440 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122215 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 122215 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 635655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 635655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 635655 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 635655 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662112010 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662112010 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298824000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298824000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144431000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144431000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7960936010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7960936010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7960936010 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7960936010 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516397500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516397500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811433000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811433000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045890 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045890 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index d6cd88975..a60709d68 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -186,7 +186,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -248,7 +248,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.physmem.port[0] slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -305,7 +305,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index c4cb3c061..c99186441 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:05 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:09:16 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1915492819000 because m5_exit instruction encountered +Exiting @ tick 1920852274000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index abedba373..8d476d641 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.915493 # Number of seconds simulated -sim_ticks 1915492819000 # Number of ticks simulated -final_tick 1915492819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920852 # Number of seconds simulated +sim_ticks 1920852274000 # Number of ticks simulated +final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1853108 # Simulator instruction rate (inst/s) -host_op_rate 1853107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63179819624 # Simulator tick rate (ticks/s) -host_mem_usage 294892 # Number of bytes of host memory used -host_seconds 30.32 # Real time elapsed on the host -sim_insts 56182681 # Number of instructions simulated -sim_ops 56182681 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24846208 # Number of bytes read from this memory +host_inst_rate 1904642 # Simulator instruction rate (inst/s) +host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65112526106 # Simulator tick rate (ticks/s) +host_mem_usage 294856 # Number of bytes of host memory used +host_seconds 29.50 # Real time elapsed on the host +sim_insts 56187824 # Number of instructions simulated +sim_ops 56187824 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24847552 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28349056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7388480 # Number of bytes written to this memory -system.physmem.bytes_written::total 7388480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388222 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28350592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7389056 # Number of bytes written to this memory +system.physmem.bytes_written::total 7389056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388243 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442954 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115445 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115445 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 444009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12971183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1384684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14799876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 444009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 444009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3857221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3857221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3857221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 444009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12971183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1384684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18657097 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 336041 # number of replacements -system.l2c.tagsinuse 65311.191779 # Cycle average of tags in use -system.l2c.total_refs 2447812 # Total number of references to valid blocks. -system.l2c.sampled_refs 401203 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101181 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5933228000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55666.496606 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4774.109125 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4870.586047 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.849403 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.072847 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.074319 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996570 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 915368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814896 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1730264 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835591 # number of Writeback hits -system.l2c.Writeback_hits::total 835591 # number of Writeback hits +system.physmem.num_reads::total 442978 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 336066 # number of replacements +system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use +system.l2c.total_refs 2448229 # Total number of references to valid blocks. +system.l2c.sampled_refs 401229 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101825 # Average number of references to valid blocks. +system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits +system.l2c.Writeback_hits::total 835223 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187658 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187658 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 915368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002554 # number of demand (read+write) hits -system.l2c.demand_hits::total 1917922 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 915368 # number of overall hits -system.l2c.overall_hits::cpu.data 1002554 # number of overall hits -system.l2c.overall_hits::total 1917922 # number of overall hits -system.l2c.ReadReq_misses::cpu.inst 13289 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 271916 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285205 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116692 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116692 # number of ReadExReq misses -system.l2c.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388608 # number of demand (read+write) misses -system.l2c.demand_misses::total 401897 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.inst 13289 # number of overall misses -system.l2c.overall_misses::cpu.data 388608 # number of overall misses -system.l2c.overall_misses::total 401897 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.inst 691068000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 14144627000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14835695000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6068427000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6068427000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.inst 691068000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20213054000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20904122000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.inst 691068000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20213054000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20904122000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 928657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086812 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2015469 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835591 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835591 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304350 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 928657 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1391162 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2319819 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 928657 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1391162 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2319819 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.014310 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250196 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141508 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.538462 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383414 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.inst 0.014310 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279341 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173245 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.inst 0.014310 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279341 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173245 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52003.010008 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52018.369644 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52017.653968 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.796319 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52003.796319 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52003.010008 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52013.993536 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52013.630358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52003.010008 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52013.993536 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52013.630358 # average overall miss latency +system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits +system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916210 # number of overall hits +system.l2c.overall_hits::cpu.data 1002336 # number of overall hits +system.l2c.overall_hits::total 1918546 # number of overall hits +system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 8 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.340010 # Cycle average of tags in use +system.iocache.tagsinuse 1.356962 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750543570000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.340010 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083751 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083751 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -225,14 +225,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 19939998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 19939998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5720017806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5720017806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5739957804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5739957804 # 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number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -249,19 +249,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115260.104046 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115260.104046 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137659.265643 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137659.265643 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137566.394344 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137566.394344 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137566.394344 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64633068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119497.098266 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183820.413121 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183553.716093 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183553.716093 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7453000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7118 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6169.632302 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1047.063782 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -275,14 +275,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10943998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10943998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559163998 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559163998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570107996 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570107996 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570107996 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570107996 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5477251000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5477251000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5488927000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5488927000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5488927000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5488927000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -291,14 +291,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63260.104046 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63260.104046 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85655.660329 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85655.660329 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85562.803978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85562.803978 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131550.077891 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064877 # DTB read hits -system.cpu.dtb.read_misses 10317 # DTB read misses +system.cpu.dtb.read_hits 9065773 # DTB read hits +system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728824 # DTB read accesses -system.cpu.dtb.write_hits 6356219 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728856 # DTB read accesses +system.cpu.dtb.write_hits 6357048 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15421096 # DTB hits -system.cpu.dtb.data_misses 11457 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15422821 # DTB hits +system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020753 # DTB accesses -system.cpu.itb.fetch_hits 4974034 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020787 # DTB accesses +system.cpu.itb.fetch_hits 4975760 # ITB hits +system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979031 # ITB accesses +system.cpu.itb.fetch_accesses 4980766 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -344,51 +344,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3830985638 # number of cpu cycles simulated +system.cpu.numCycles 3841704548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56182681 # Number of instructions committed -system.cpu.committedOps 56182681 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054721 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483282 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468098 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054721 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71321767 # number of times the integer registers were read -system.cpu.num_int_register_writes 38521612 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15473677 # number of memory refs -system.cpu.num_load_insts 9101706 # Number of load instructions -system.cpu.num_store_insts 6371971 # Number of store instructions -system.cpu.num_idle_cycles 3589415321.998127 # Number of idle cycles -system.cpu.num_busy_cycles 241570316.001874 # Number of busy cycles -system.cpu.not_idle_fraction 0.063057 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.936943 # Percentage of idle cycles +system.cpu.committedInsts 56187824 # Number of instructions committed +system.cpu.committedOps 56187824 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52059470 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483670 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469221 # number of instructions that are conditional controls +system.cpu.num_int_insts 52059470 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71329755 # number of times the integer registers were read +system.cpu.num_int_register_writes 38524240 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15475451 # number of memory refs +system.cpu.num_load_insts 9102635 # Number of load instructions +system.cpu.num_store_insts 6372816 # Number of store instructions +system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles +system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934372 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211976 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74903 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1931 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106219 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73536 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74929 40.88% 40.88% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 131 0.07% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1936 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106285 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183281 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73562 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73536 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149134 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857766748000 96.99% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 79985500 0.00% 96.99% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 554565500 0.03% 97.02% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57090762000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1915492061000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692306 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814121 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692120 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814001 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175965 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 176052 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6837 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5161 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192907 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323559 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 193007 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392153 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45078055000 2.35% 2.35% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5087693000 0.27% 2.62% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1865326311000 97.38% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928006 # number of replacements -system.cpu.icache.tagsinuse 508.737243 # Cycle average of tags in use -system.cpu.icache.total_refs 55265829 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928517 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.520535 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 35693107000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.737243 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.993627 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.993627 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55265829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55265829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55265829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55265829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55265829 # number of overall hits -system.cpu.icache.overall_hits::total 55265829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928677 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928677 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928677 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928677 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928677 # number of overall misses -system.cpu.icache.overall_misses::total 928677 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13560162500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13560162500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13560162500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13560162500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13560162500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13560162500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016526 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200305 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199284 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199284 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15042278 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120375 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120375 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +643,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835506 # number of writebacks -system.cpu.dcache.writebacks::total 835506 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069547 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069547 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304513 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304513 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374060 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374060 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374060 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23187340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23187340000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8250131000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8250131000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193151000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193151000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31437471000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31437471000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31437471000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31437471000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199604500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199604500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062367500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062367500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049461 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086449 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086449 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091356 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091356 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091356 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21679.589583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21679.589583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27092.869598 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27092.869598 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11157.703195 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11157.703195 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22879.256364 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22879.256364 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks +system.cpu.dcache.writebacks::total 835138 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index f78b6a8fb..363bd4c66 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -298,7 +298,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -359,7 +359,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -772,7 +772,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index ccc6b6e90..70032b595 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:37:10 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:21:03 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1169301297000 because m5_exit instruction encountered +Exiting @ tick 1171612619000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index a92b3a054..bf3a52c45 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,320 +1,320 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.169301 # Number of seconds simulated -sim_ticks 1169301297000 # Number of ticks simulated -final_tick 1169301297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.171613 # Number of seconds simulated +sim_ticks 1171612619000 # Number of ticks simulated +final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 971844 # Simulator instruction rate (inst/s) -host_op_rate 1242825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18805861990 # Simulator tick rate (ticks/s) -host_mem_usage 384788 # Number of bytes of host memory used -host_seconds 62.18 # Real time elapsed on the host -sim_insts 60426768 # Number of instructions simulated -sim_ops 77275723 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 639669 # Simulator instruction rate (inst/s) +host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12399663305 # Simulator tick rate (ticks/s) +host_mem_usage 384708 # Number of bytes of host memory used +host_seconds 94.49 # Real time elapsed on the host +sim_insts 60440687 # Number of instructions simulated +sim_ops 77305655 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 394404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4694964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 322780 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4800816 # Number of bytes read from this memory -system.physmem.bytes_read::total 60545060 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 394404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 322780 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4092224 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory +system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7119568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12381 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73431 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75039 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457439 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63941 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820777 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43044208 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 337299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4015188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 276045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4105713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51778836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 337299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 276045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 613344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3499717 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14539 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2574481 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6088737 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3499717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43044208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 337299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4029726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 276045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6680194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57867573 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69045 # number of replacements -system.l2c.tagsinuse 52660.415221 # Cycle average of tags in use -system.l2c.total_refs 1684870 # Total number of references to valid blocks. -system.l2c.sampled_refs 134185 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.556321 # Average number of references to valid blocks. +system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 69306 # number of replacements +system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use +system.l2c.total_refs 1685686 # Total number of references to valid blocks. +system.l2c.sampled_refs 134505 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.532516 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39883.931908 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000281 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001232 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3733.911815 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4222.338805 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.732261 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2761.000373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2056.498545 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608581 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056975 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064428 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728682 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770310 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541912 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577444 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559780 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40027.198780 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40169.925640 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40131.482146 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.329908 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40048.630520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.701540 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40017.699115 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40091.295117 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.158301 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.856544 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40114.530881 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.350086 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40135.003479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.260655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40262.207225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40117.173336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40083.092535 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,10 +498,10 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7070010 # DTB read hits -system.cpu0.dtb.read_misses 3742 # DTB read misses -system.cpu0.dtb.write_hits 5655317 # DTB write hits -system.cpu0.dtb.write_misses 808 # DTB write misses +system.cpu0.dtb.read_hits 7077919 # DTB read hits +system.cpu0.dtb.read_misses 3740 # DTB read misses +system.cpu0.dtb.write_hits 5661726 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7073752 # DTB read accesses -system.cpu0.dtb.write_accesses 5656125 # DTB write accesses +system.cpu0.dtb.read_accesses 7081659 # DTB read accesses +system.cpu0.dtb.write_accesses 5662530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12725327 # DTB hits -system.cpu0.dtb.misses 4550 # DTB misses -system.cpu0.dtb.accesses 12729877 # DTB accesses -system.cpu0.itb.inst_hits 29439174 # ITB inst hits +system.cpu0.dtb.hits 12739645 # DTB hits +system.cpu0.dtb.misses 4544 # DTB misses +system.cpu0.dtb.accesses 12744189 # DTB accesses +system.cpu0.itb.inst_hits 29451654 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29441379 # ITB inst accesses -system.cpu0.itb.hits 29439174 # DTB hits +system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses +system.cpu0.itb.hits 29451654 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29441379 # DTB accesses -system.cpu0.numCycles 2338602594 # number of cpu cycles simulated +system.cpu0.itb.accesses 29453859 # DTB accesses +system.cpu0.numCycles 2343225238 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28746820 # Number of instructions committed -system.cpu0.committedOps 37084824 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33031249 # Number of integer alu accesses +system.cpu0.committedInsts 28759206 # Number of instructions committed +system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241704 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4321371 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33031249 # number of integer instructions +system.cpu0.num_func_calls 1242118 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33058293 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189614137 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36088732 # number of times the integer registers were written +system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13393278 # number of memory refs -system.cpu0.num_load_insts 7407523 # Number of load instructions -system.cpu0.num_store_insts 5985755 # Number of store instructions -system.cpu0.num_idle_cycles 2203295398.340116 # Number of idle cycles -system.cpu0.num_busy_cycles 135307195.659884 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057858 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942142 # Percentage of idle cycles +system.cpu0.num_mem_refs 13408219 # number of memory refs +system.cpu0.num_load_insts 7415624 # Number of load instructions +system.cpu0.num_store_insts 5992595 # Number of store instructions +system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles +system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46685 # number of quiesce instructions executed -system.cpu0.icache.replacements 408143 # number of replacements -system.cpu0.icache.tagsinuse 509.526052 # Cycle average of tags in use -system.cpu0.icache.total_refs 29030502 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408655 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.039145 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74905211000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.526052 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995168 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995168 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29030502 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29030502 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29030502 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29030502 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29030502 # number of overall hits -system.cpu0.icache.overall_hits::total 29030502 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408655 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408655 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408655 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408655 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408655 # number of overall misses -system.cpu0.icache.overall_misses::total 408655 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5965025000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5965025000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5965025000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5965025000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5965025000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5965025000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439157 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29439157 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29439157 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29439157 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29439157 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29439157 # number of overall (read+write) accesses +system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed +system.cpu0.icache.replacements 408292 # number of replacements +system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use +system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits +system.cpu0.icache.overall_hits::total 29042833 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses +system.cpu0.icache.overall_misses::total 408804 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14596.725845 # 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miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029982 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029982 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,62 +739,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306018 # number of writebacks -system.cpu0.dcache.writebacks::total 306018 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227470 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227470 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141496 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141496 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7484 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7484 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368966 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 368966 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 368966 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 368966 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2659287000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2659287000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4452739000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4452739000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70511500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70511500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45688000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45688000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7112026000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7112026000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7112026000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7112026000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10424499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10424499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822589000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822589000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11247088500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11247088500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033316 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033316 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025765 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025765 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059164 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047618 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047618 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029949 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029949 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029949 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11690.715259 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11690.715259 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31469.009725 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31469.009725 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7580.251559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7580.251559 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6104.756815 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6104.756815 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19275.559266 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19275.559266 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks +system.cpu0.dcache.writebacks::total 306522 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -804,26 +804,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311514 # DTB read hits -system.cpu1.dtb.read_misses 3660 # DTB read misses -system.cpu1.dtb.write_hits 5828200 # DTB write hits -system.cpu1.dtb.write_misses 1442 # DTB write misses +system.cpu1.dtb.read_hits 8311872 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5828412 # DTB write hits +system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315174 # DTB read accesses -system.cpu1.dtb.write_accesses 5829642 # DTB write accesses +system.cpu1.dtb.read_accesses 8315535 # DTB read accesses +system.cpu1.dtb.write_accesses 5829848 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14139714 # DTB hits -system.cpu1.dtb.misses 5102 # DTB misses -system.cpu1.dtb.accesses 14144816 # DTB accesses -system.cpu1.itb.inst_hits 32283727 # ITB inst hits +system.cpu1.dtb.hits 14140284 # DTB hits +system.cpu1.dtb.misses 5099 # DTB misses +system.cpu1.dtb.accesses 14145383 # DTB accesses +system.cpu1.itb.inst_hits 32285286 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -840,79 +840,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32285898 # ITB inst accesses -system.cpu1.itb.hits 32283727 # DTB hits +system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses +system.cpu1.itb.hits 32285286 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 32285898 # DTB accesses -system.cpu1.numCycles 2337184534 # number of cpu cycles simulated +system.cpu1.itb.accesses 32287457 # DTB accesses +system.cpu1.numCycles 2341739150 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31679948 # Number of instructions committed -system.cpu1.committedOps 40190899 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 36862651 # Number of integer alu accesses +system.cpu1.committedInsts 31681481 # Number of instructions committed +system.cpu1.committedOps 40192806 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36864445 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962114 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3486829 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36862651 # number of integer instructions +system.cpu1.num_func_calls 962202 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36864445 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210732518 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38542658 # number of times the integer registers were written +system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14677413 # number of memory refs -system.cpu1.num_load_insts 8633313 # Number of load instructions -system.cpu1.num_store_insts 6044100 # Number of store instructions -system.cpu1.num_idle_cycles 1859139408.190032 # Number of idle cycles -system.cpu1.num_busy_cycles 478045125.809968 # Number of busy cycles -system.cpu1.not_idle_fraction 0.204539 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.795461 # Percentage of idle cycles +system.cpu1.num_mem_refs 14678127 # number of memory refs +system.cpu1.num_load_insts 8633777 # Number of load instructions +system.cpu1.num_store_insts 6044350 # Number of store instructions +system.cpu1.num_idle_cycles 1858809543.114650 # Number of idle cycles +system.cpu1.num_busy_cycles 482929606.885350 # Number of busy cycles +system.cpu1.not_idle_fraction 0.206227 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.793773 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43902 # number of quiesce instructions executed -system.cpu1.icache.replacements 454250 # number of replacements -system.cpu1.icache.tagsinuse 478.426272 # Cycle average of tags in use -system.cpu1.icache.total_refs 31828961 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 454762 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.990371 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 91827158000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.426272 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.934426 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.934426 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 31828961 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 31828961 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31828961 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31828961 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31828961 # number of overall hits -system.cpu1.icache.overall_hits::total 31828961 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454762 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454762 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454762 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454762 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454762 # number of overall misses -system.cpu1.icache.overall_misses::total 454762 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6579254500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6579254500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6579254500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6579254500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6579254500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6579254500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32283723 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32283723 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32283723 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32283723 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32283723 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32283723 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014086 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014086 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014086 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014086 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014086 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014086 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.467598 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14467.467598 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14467.467598 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14467.467598 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14467.467598 # average overall miss latency +system.cpu1.kern.inst.quiesce 43917 # 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number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7509385000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7117845 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7117845 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978027 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4978027 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92912 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92912 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92835 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92835 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12095872 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12095872 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12095872 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12095872 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023970 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023970 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030151 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030151 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119446 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119446 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108224 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13881.139662 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13881.139662 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34253.193063 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34253.193063 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9575.644260 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9575.644260 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8691.350652 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8691.350652 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23415.387446 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23415.387446 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23415.387446 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,66 +1045,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 265856 # number of writebacks -system.cpu1.dcache.writebacks::total 265856 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170577 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 170577 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150060 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150060 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11061 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11061 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10033 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10033 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 320637 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 320637 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320637 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320637 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1781497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1781497000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4669562000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4669562000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 68967000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68967000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 45286000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 45286000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6451059000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6451059000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6451059000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6451059000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136551200000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136551200000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714194000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176265394000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176265394000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023966 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023966 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030146 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119094 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119094 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108106 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108106 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026509 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026509 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026509 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10443.946136 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10443.946136 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31117.966147 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31117.966147 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6235.150529 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6235.150529 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4513.704774 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4513.704774 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20119.508977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20119.508977 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 266082 # number of writebacks +system.cpu1.dcache.writebacks::total 266082 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170612 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170612 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150091 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150091 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11098 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11098 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10038 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10038 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320703 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320703 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320703 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320703 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855824122 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855824122 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4690597670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4690597670 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72957002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72957002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57198010 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57198010 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6546421792 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6546421792 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6546421792 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6546421792 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136480079000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136480079000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39677118500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39677118500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176157197500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176157197500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023970 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023970 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030151 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030151 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119446 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119446 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108127 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108127 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10877.453649 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10877.453649 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31251.691774 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31251.691774 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6573.887367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6573.887367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5698.148037 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5698.148037 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20412.723897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20412.723897 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1126,10 +1122,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550273882646 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550273882646 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550273882646 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550273882646 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index d41ee2fc6..b0e885f8a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -187,7 +187,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -248,7 +248,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -661,7 +661,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 4f563f8f5..a0fa03c1d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:36:57 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:20:44 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2591087067000 because m5_exit instruction encountered +Exiting @ tick 2593402521000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index f1beadd55..5473fafb1 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,54 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.591087 # Number of seconds simulated -sim_ticks 2591087067000 # Number of ticks simulated -final_tick 2591087067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.593403 # Number of seconds simulated +sim_ticks 2593402521000 # Number of ticks simulated +final_tick 2593402521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 814871 # Simulator instruction rate (inst/s) -host_op_rate 1040723 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35675794467 # Simulator tick rate (ticks/s) -host_mem_usage 385812 # Number of bytes of host memory used -host_seconds 72.63 # Real time elapsed on the host -sim_insts 59182970 # Number of instructions simulated -sim_ops 75586355 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 706144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9051344 # Number of bytes read from this memory -system.physmem.bytes_read::total 132441392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 706144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 706144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3678592 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6694664 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17236 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141461 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494129 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57478 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811496 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47348232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 272528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3493261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51114219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 272528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 272528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1419710 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1164018 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2583728 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1419710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47348232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 272528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4657279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53697947 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 766927 # Simulator instruction rate (inst/s) +host_op_rate 979485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33608362861 # Simulator tick rate (ticks/s) +host_mem_usage 384708 # Number of bytes of host memory used +host_seconds 77.17 # Real time elapsed on the host +sim_insts 59180230 # Number of instructions simulated +sim_ops 75582343 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,141 +23,179 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 61946 # number of replacements -system.l2c.tagsinuse 50741.194054 # Cycle average of tags in use -system.l2c.total_refs 1730603 # Total number of references to valid blocks. -system.l2c.sampled_refs 127327 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.591799 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2543210574000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37737.574743 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 3.884961 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.001325 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6978.831431 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6020.901593 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575830 # Average percentage of cache occupancy +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9067536 # Number of bytes read from this memory +system.physmem.bytes_read::total 132455600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704224 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3695808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6711880 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141714 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494351 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57747 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811765 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47305958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 271544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3496386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51074062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 271544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271544 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1425081 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1162979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2588059 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1425081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47305958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 271544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4659365 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53662121 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 62163 # number of replacements +system.l2c.tagsinuse 51413.022429 # Cycle average of tags in use +system.l2c.total_refs 1730961 # Total number of references to valid blocks. +system.l2c.sampled_refs 127547 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.571162 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2544159444000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 38018.047073 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 3.884744 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000558 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7004.232123 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6386.857931 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.580109 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.106489 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.091872 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.774249 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8734 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 843850 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 367763 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1223899 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 646100 # number of Writeback hits -system.l2c.Writeback_hits::total 646100 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.106876 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.097456 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784500 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8759 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 843511 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 367799 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1223613 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 646378 # number of Writeback hits +system.l2c.Writeback_hits::total 646378 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 114412 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114412 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 8734 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 843850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 482175 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338311 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 8734 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3552 # number of overall hits -system.l2c.overall_hits::cpu.inst 843850 # number of overall hits -system.l2c.overall_hits::cpu.data 482175 # number of overall hits -system.l2c.overall_hits::total 1338311 # number of overall hits +system.l2c.ReadExReq_hits::cpu.data 114402 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114402 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 8759 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3544 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 843511 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 482201 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338015 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 8759 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3544 # number of overall hits +system.l2c.overall_hits::cpu.inst 843511 # number of overall hits +system.l2c.overall_hits::cpu.data 482201 # number of overall hits +system.l2c.overall_hits::total 1338015 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 10620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 9861 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20489 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2867 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2867 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133208 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133208 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 10590 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10247 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20844 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2881 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2881 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133061 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133061 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 10620 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143069 # number of demand (read+write) misses -system.l2c.demand_misses::total 153697 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10590 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143308 # number of demand (read+write) misses +system.l2c.demand_misses::total 153905 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu.inst 10620 # number of overall misses -system.l2c.overall_misses::cpu.data 143069 # number of overall misses -system.l2c.overall_misses::total 153697 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 260000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 156000 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.103014 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000572 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.228821 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.103014 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162603193000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162868033000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027105 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016749 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991056 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537701 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537701 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.229106 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.103159 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.229106 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.103159 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40175.800377 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40066.524693 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40123.139245 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40057.202651 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40057.202651 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40140.366945 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40140.366945 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40144.381492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40070.362057 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40107.944732 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.618188 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.618188 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.807893 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40041.807893 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40175.800377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40135.277384 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40138.070359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,26 +307,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996145 # DTB read hits -system.cpu.dtb.read_misses 7343 # DTB read misses -system.cpu.dtb.write_hits 11231074 # DTB write hits -system.cpu.dtb.write_misses 2209 # DTB write misses +system.cpu.dtb.read_hits 14995175 # DTB read hits +system.cpu.dtb.read_misses 7360 # DTB read misses +system.cpu.dtb.write_hits 11229808 # DTB write hits +system.cpu.dtb.write_misses 2205 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003488 # DTB read accesses -system.cpu.dtb.write_accesses 11233283 # DTB write accesses +system.cpu.dtb.read_accesses 15002535 # DTB read accesses +system.cpu.dtb.write_accesses 11232013 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26227219 # DTB hits -system.cpu.dtb.misses 9552 # DTB misses -system.cpu.dtb.accesses 26236771 # DTB accesses -system.cpu.itb.inst_hits 60464772 # ITB inst hits +system.cpu.dtb.hits 26224983 # DTB hits +system.cpu.dtb.misses 9565 # DTB misses +system.cpu.dtb.accesses 26234548 # DTB accesses +system.cpu.itb.inst_hits 60461981 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60469243 # ITB inst accesses -system.cpu.itb.hits 60464772 # DTB hits +system.cpu.itb.inst_accesses 60466452 # ITB inst accesses +system.cpu.itb.hits 60461981 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60469243 # DTB accesses -system.cpu.numCycles 5182174134 # number of cpu cycles simulated +system.cpu.itb.accesses 60466452 # DTB accesses +system.cpu.numCycles 5186805042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59182970 # Number of instructions committed -system.cpu.committedOps 75586355 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68355817 # Number of integer alu accesses +system.cpu.committedInsts 59180230 # Number of instructions committed +system.cpu.committedOps 75582343 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68351784 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139775 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7653714 # number of instructions that are conditional controls -system.cpu.num_int_insts 68355817 # number of integer instructions +system.cpu.num_func_calls 2139562 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7653493 # number of instructions that are conditional controls +system.cpu.num_int_insts 68351784 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 391424329 # number of times the integer registers were read -system.cpu.num_int_register_writes 73137723 # number of times the integer registers were written +system.cpu.num_int_register_reads 391402858 # number of times the integer registers were read +system.cpu.num_int_register_writes 73137157 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394520 # number of memory refs -system.cpu.num_load_insts 15660068 # Number of load instructions -system.cpu.num_store_insts 11734452 # Number of store instructions -system.cpu.num_idle_cycles 4574883884.570234 # Number of idle cycles -system.cpu.num_busy_cycles 607290249.429766 # Number of busy cycles -system.cpu.not_idle_fraction 0.117188 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.882812 # Percentage of idle cycles +system.cpu.num_mem_refs 27392171 # number of memory refs +system.cpu.num_load_insts 15659029 # Number of load instructions +system.cpu.num_store_insts 11733142 # Number of store instructions +system.cpu.num_idle_cycles 4570470450.554237 # Number of idle cycles +system.cpu.num_busy_cycles 616334591.445762 # Number of busy cycles +system.cpu.not_idle_fraction 0.118827 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.881173 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed -system.cpu.icache.replacements 855597 # number of replacements -system.cpu.icache.tagsinuse 510.944278 # Cycle average of tags in use -system.cpu.icache.total_refs 59608663 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856109 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.627422 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18496284000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.944278 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59608663 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59608663 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59608663 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59608663 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59608663 # number of overall hits -system.cpu.icache.overall_hits::total 59608663 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856109 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856109 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856109 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856109 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856109 # number of overall misses -system.cpu.icache.overall_misses::total 856109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422495000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12422495000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12422495000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12422495000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12422495000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12422495000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60464772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60464772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60464772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60464772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60464772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60464772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014159 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014159 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014159 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014159 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014159 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014159 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14510.412810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14510.412810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14510.412810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14510.412810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14510.412810 # average overall miss latency +system.cpu.kern.inst.quiesce 82989 # number of quiesce instructions executed +system.cpu.icache.replacements 855209 # number of replacements +system.cpu.icache.tagsinuse 510.928777 # Cycle average of tags in use +system.cpu.icache.total_refs 59606260 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855721 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.656185 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18855254000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.928777 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997908 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997908 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59606260 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59606260 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59606260 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59606260 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59606260 # number of overall hits +system.cpu.icache.overall_hits::total 59606260 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855721 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855721 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855721 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855721 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855721 # number of overall misses +system.cpu.icache.overall_misses::total 855721 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12570164500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12570164500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12570164500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12570164500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12570164500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12570164500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60461981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60461981 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60461981 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60461981 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60461981 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60461981 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14689.559448 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14689.559448 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14689.559448 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14689.559448 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,114 +424,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 50189 # number of writebacks -system.cpu.icache.writebacks::total 50189 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856109 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856109 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856109 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856109 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856109 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856109 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9851777000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9851777000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9851777000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9851777000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9851777000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9851777000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 50294 # number of writebacks +system.cpu.icache.writebacks::total 50294 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12931137500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146935431000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146935431000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367480000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367480000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187302911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187302911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027177 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027177 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045950 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045950 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026028 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026028 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12055.674762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12055.674762 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33878.167999 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33878.167999 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11580.258303 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11580.258303 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20885.171541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20885.171541 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596084 # number of writebacks +system.cpu.dcache.writebacks::total 596084 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368861 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368861 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250370 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250370 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11572 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11572 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619231 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619231 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619231 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619231 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4614667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4614667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480868000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480868000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137416000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137416000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13095535500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13095535500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13095535500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13095535500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146835601000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146835601000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40324843500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40324843500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027195 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046725 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046725 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +609,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1341944663355 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341944663355 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1341944663355 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341484384445 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 8437cb6eb..04a12f8a0 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -604,7 +604,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master @@ -666,7 +666,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master @@ -1146,7 +1146,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index d9a666d01..66f0cf496 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:04:41 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:41:46 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5187414160000 because m5_exit instruction encountered +Exiting @ tick 5191766314000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 78491477d..b0d3b38b0 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.187414 # Number of seconds simulated -sim_ticks 5187414160000 # Number of ticks simulated -final_tick 5187414160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.191766 # Number of seconds simulated +sim_ticks 5191766314000 # Number of ticks simulated +final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1218225 # Simulator instruction rate (inst/s) -host_op_rate 2338274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45751964384 # Simulator tick rate (ticks/s) -host_mem_usage 354108 # Number of bytes of host memory used -host_seconds 113.38 # Real time elapsed on the host -sim_insts 138123832 # Number of instructions simulated -sim_ops 265116381 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2873600 # Number of bytes read from this memory +host_inst_rate 843973 # Simulator instruction rate (inst/s) +host_op_rate 1619974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31713438762 # Simulator tick rate (ticks/s) +host_mem_usage 354068 # Number of bytes of host memory used +host_seconds 163.71 # Real time elapsed on the host +sim_insts 138165779 # Number of instructions simulated +sim_ops 265203823 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9013056 # Number of bytes read from this memory -system.physmem.bytes_read::total 12710848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8119168 # Number of bytes written to this memory -system.physmem.bytes_written::total 8119168 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44900 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory +system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8080768 # Number of bytes written to this memory +system.physmem.bytes_written::total 8080768 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45173 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12873 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198607 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126862 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126862 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 553956 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139677 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197687 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126262 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126262 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 556857 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1737485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2450324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158821 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1565167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1565167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 553956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1721828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2436929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1556458 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1556458 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1737485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4015491 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 87121 # number of replacements -system.l2c.tagsinuse 64744.373482 # Cycle average of tags in use -system.l2c.total_refs 3489902 # Total number of references to valid blocks. -system.l2c.sampled_refs 151833 # Sample count of references to valid blocks. -system.l2c.avg_refs 22.985135 # Average number of references to valid blocks. +system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 86221 # number of replacements +system.l2c.tagsinuse 64766.656106 # Cycle average of tags in use +system.l2c.total_refs 3491041 # Total number of references to valid blocks. +system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.127594 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50159.542434 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.140418 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3477.361346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11107.329284 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765374 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50170.355132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3484.481213 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11111.678563 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.053060 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.169484 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.987921 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 6932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 2996 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 775163 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1280771 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2065862 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1543668 # number of Writeback hits -system.l2c.Writeback_hits::total 1543668 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 305 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 199243 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 199243 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 6932 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 2996 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 775163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1480014 # number of demand (read+write) hits -system.l2c.demand_hits::total 2265105 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 6932 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 2996 # number of overall hits -system.l2c.overall_hits::cpu.inst 775163 # number of overall hits -system.l2c.overall_hits::cpu.data 1480014 # number of overall hits -system.l2c.overall_hits::total 2265105 # number of overall hits +system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1279350 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2065978 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1542134 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1218002000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269790000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 57269790000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001666 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016337 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021624 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.019547 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.820694 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.820694 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.362738 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.362738 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001666 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016337 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.087388 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063892 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001666 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016337 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.087388 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu.inst 513944000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5641599000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6155743000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56050191064 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 56050191064 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1204378000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1204378000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 57254569064 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 57254569064 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.021696 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019557 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.808408 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.808408 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.358938 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.358938 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063411 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.086773 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063411 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40011.418363 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40452.804861 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40314.783791 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40260.744986 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40260.744986 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.131732 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.131732 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40011.418363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40094.552639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40087.626699 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40011.418363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40094.552639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40087.626699 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40116.672966 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -251,14 +251,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47504 # number of replacements -system.iocache.tagsinuse 0.096008 # Cycle average of tags in use +system.iocache.tagsinuse 0.108710 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5048726357000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.096008 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.006001 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.006001 # Average percentage of cache occupancy +system.iocache.warmup_cycle 5048944307000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.108710 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.006794 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.006794 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses system.iocache.ReadReq_misses::total 839 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -267,14 +267,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47559 system.iocache.demand_misses::total 47559 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 47559 # number of overall misses system.iocache.overall_misses::total 47559 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 105990932 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 105990932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391870160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6391870160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6497861092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6497861092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6497861092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6497861092 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128944932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 128944932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 7159405160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7159405160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7288350092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7288350092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 7288350092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7288350092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -291,19 +291,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126330.073897 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126330.073897 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136812.289384 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 136812.289384 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 136627.370046 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136627.370046 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 136627.370046 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 69487644 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 153688.834327 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 153240.692637 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 153248.598415 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 153248.598415 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 372008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 11303 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 38 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6147.716889 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9789.684211 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -317,14 +317,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47559 system.iocache.demand_mshr_misses::total 47559 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47559 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47559 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62341978 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 62341978 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3962173996 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3962173996 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024515974 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 4024515974 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024515974 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 4024515974 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 85286000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 85286000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4729709976 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4729709976 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4814995976 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4814995976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4814995976 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74305.098927 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74305.098927 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84806.806421 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 84806.806421 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84621.543220 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 84621.543220 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 101242.582392 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10374828320 # number of cpu cycles simulated +system.cpu.numCycles 10383532628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 138123832 # Number of instructions committed -system.cpu.committedOps 265116381 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 249524959 # Number of integer alu accesses +system.cpu.committedInsts 138165779 # Number of instructions committed +system.cpu.committedOps 265203823 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 249613018 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 24879442 # number of instructions that are conditional controls -system.cpu.num_int_insts 249524959 # number of integer instructions +system.cpu.num_conditional_control_insts 24887740 # number of instructions that are conditional controls +system.cpu.num_int_insts 249613018 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 777989618 # number of times the integer registers were read -system.cpu.num_int_register_writes 422868687 # number of times the integer registers were written +system.cpu.num_int_register_reads 778264797 # number of times the integer registers were read +system.cpu.num_int_register_writes 423017345 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 23163323 # number of memory refs -system.cpu.num_load_insts 14806608 # Number of load instructions -system.cpu.num_store_insts 8356715 # Number of store instructions -system.cpu.num_idle_cycles 9773126970.350117 # Number of idle cycles -system.cpu.num_busy_cycles 601701349.649884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057996 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942004 # Percentage of idle cycles +system.cpu.num_mem_refs 23180618 # number of memory refs +system.cpu.num_load_insts 14822217 # Number of load instructions +system.cpu.num_store_insts 8358401 # Number of store instructions +system.cpu.num_idle_cycles 9771874940.286118 # Number of idle cycles +system.cpu.num_busy_cycles 611657687.713882 # Number of busy cycles +system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941093 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 787531 # number of replacements -system.cpu.icache.tagsinuse 510.360069 # Cycle average of tags in use -system.cpu.icache.total_refs 158416168 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 788043 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 201.024777 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 159962400000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.360069 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996797 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996797 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 158416168 # 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miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.004950 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.004950 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.004950 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.004950 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.004950 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14687.523634 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14687.523634 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14687.523634 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14687.523634 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14687.523634 # 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number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 158472874 # number of overall hits +system.cpu.icache.overall_hits::total 158472874 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses +system.cpu.icache.overall_misses::total 790411 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780929500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11780929500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11780929500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11780929500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11780929500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11780929500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 159263285 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159263285 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 159263285 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159263285 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 159263285 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 159263285 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # 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Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8060 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8060 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7430 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7430 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7430 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7430 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4796 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4796 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4796 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4796 # 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number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12226 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12226 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.392343 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.392343 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.392279 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.392279 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.392279 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.392279 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10675.354462 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10675.354462 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10675.354462 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10675.354462 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10675.354462 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12328 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12328 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12328 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12328 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346098 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346098 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346042 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.346042 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346042 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.346042 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,78 +515,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 763 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 763 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4796 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4796 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4796 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4796 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4796 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4796 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36811000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36811000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36811000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36811000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36811000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36811000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.392343 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.392343 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.392279 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.392279 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.392279 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7675.354462 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7675.354462 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7675.354462 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 726 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 726 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4266 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4266 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4266 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4266 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4266 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4266 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37620000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37620000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37620000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37620000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37620000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37620000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346098 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346098 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346042 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346042 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346042 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8818.565401 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 8715 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.044713 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 12138 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 8729 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.390537 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5162053528000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.044713 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315295 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.315295 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12140 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12140 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12140 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12140 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12140 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12140 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9925 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9925 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9925 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9925 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9925 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9925 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112013000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112013000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112013000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 112013000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112013000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 112013000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22065 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22065 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22065 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22065 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22065 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22065 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.449807 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.449807 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.449807 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.449807 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.449807 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.449807 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11285.944584 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11285.944584 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11285.944584 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11285.944584 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11285.944584 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 7529 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5161009068000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13332 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13332 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13332 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13332 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13332 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13332 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8729 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8729 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8729 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8729 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8729 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8729 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 112265000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 112265000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 112265000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 112265000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 112265000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 112265000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22061 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22061 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22061 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22061 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22061 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22061 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395676 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395676 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395676 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395676 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395676 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395676 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -595,90 +595,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2933 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2933 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9925 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9925 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9925 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9925 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9925 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9925 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 82238000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 82238000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 82238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 82238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 82238000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 82238000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.449807 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.449807 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.449807 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.449807 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8285.944584 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8285.944584 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8285.944584 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2916 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2916 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8729 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8729 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8729 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8729 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8729 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8729 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 86078000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 86078000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 86078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 86078000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 86078000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 86078000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395676 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395676 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395676 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395676 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9861.152480 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621962 # number of replacements -system.cpu.dcache.tagsinuse 511.997374 # Cycle average of tags in use -system.cpu.dcache.total_refs 20006252 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1622474 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.330707 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997374 # Average occupied blocks per requestor +system.cpu.dcache.replacements 1620697 # number of replacements +system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use +system.cpu.dcache.total_refs 20024819 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621209 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.351781 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11972224 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11972224 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8031812 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8031812 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20004036 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20004036 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20004036 # number of overall hits -system.cpu.dcache.overall_hits::total 20004036 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1309841 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1309841 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314876 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314876 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28758464500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13282065 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13282065 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8346688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8346688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21628753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21628753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21628753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21628753 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037725 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037725 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.075118 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.075118 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075118 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14912.283628 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14912.283628 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29299.610005 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29299.610005 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17700.599243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17700.599243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17700.599243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17700.599243 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 11989145 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11989145 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8033493 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8033493 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20022638 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20022638 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20022638 # number of overall hits +system.cpu.dcache.overall_hits::total 20022638 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308549 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308549 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623421 # number of overall misses +system.cpu.dcache.overall_misses::total 1623421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872658500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19872658500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327760500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9327760500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29200419000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29200419000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29200419000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29200419000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13297694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13297694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8348365 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8348365 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21646059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21646059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21646059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21646059 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098404 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098404 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.789719 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.789719 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.975774 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.975774 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17986.966412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17986.966412 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -687,46 +687,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1538945 # number of writebacks -system.cpu.dcache.writebacks::total 1538945 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309841 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1309841 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314876 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314876 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1624717 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1624717 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1624717 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1624717 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15603157000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15603157000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8281105000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8281105000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23884262000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23884262000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23884262000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23884262000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379632500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379632500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77304960000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 77304960000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037725 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037725 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.075118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11912.252709 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11912.252709 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26299.575071 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26299.575071 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14700.567545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14700.567545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14700.567545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14700.567545 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537686 # number of writebacks +system.cpu.dcache.writebacks::total 1537686 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308549 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308549 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24330102003 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330102003 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24330102003 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1366040500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77290441000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 77290441000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.751128 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.751128 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.964662 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.964662 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |