all: Update stats for memory per master and total fix.

28 files changed, 1144 insertions, 276 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 631fa3b25..08fd1ccfb 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -282,9 +282,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=true
@@ -344,10 +343,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -403,9 +401,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 8c9800a70..06d87b670 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:36:56
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:39:49
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index b34633a17..b45122ce6 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,23 +4,50 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1989571                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1989570                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            58921958204                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 298304                       # Number of bytes of host memory used
-host_seconds                                    31.74                       # Real time elapsed on the host
+host_inst_rate                                2870976                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2870973                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            85025108641                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 298608                       # Number of bytes of host memory used
+host_seconds                                    22.00                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    72297472                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 995008                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10452352                       # Number of bytes written to this memory
-system.physmem.num_reads                      1129648                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      163318                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       38654814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    531994                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5588490                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      44243304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.inst           855168                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         67882688                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           139840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           770176                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             72297472                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       855168                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       139840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          995008                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10452352                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10452352                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13362                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data           1060667                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              2185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             12034                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1129648                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          163318                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               163318                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              457227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            36294391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1416644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               74767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              411785                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                38654814                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         457227                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          74767                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             531994                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5588490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5588490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5588490                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             457227                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           36294391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1416644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              74767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             411785                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               44243304                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                       1051788                       # number of replacements
 system.l2c.tagsinuse                     34117.721410                       # Cycle average of tags in use
 system.l2c.total_refs                         2341203                       # Total number of references to valid blocks.
@@ -118,20 +145,26 @@ system.l2c.ReadReq_miss_rate::cpu0.inst      0.015099                       # mi
 system.l2c.ReadReq_miss_rate::cpu0.data      0.557511                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.021085                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.061193                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.353588                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.947961                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.935644                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.945615                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.812500                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.918182                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.873684                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.416750                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.410237                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.416240                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.015099                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.537413                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.021085                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.196117                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.359923                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.015099                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.537413                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.021085                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.196117                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.359923                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -169,9 +202,13 @@ system.iocache.demand_accesses::total           41727                       # nu
 system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -275,6 +312,7 @@ system.cpu0.kern.ipl_used::21                       1                       # fr
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::31                0.684617                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808753                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.65%      2.65% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.41%     11.06% # number of syscalls executed
 system.cpu0.kern.syscall::4                         2      0.88%     11.95% # number of syscalls executed
@@ -333,7 +371,7 @@ system.cpu0.kern.mode_good::idle                    0
 system.cpu0.kern.mode_switch_good::kernel     0.163165                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.280640                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks::kernel      1869378305000     99.95%     99.95% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user           957009000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
@@ -397,8 +435,11 @@ system.cpu0.icache.demand_accesses::total     57230132                       # n
 system.cpu0.icache.overall_accesses::cpu0.inst     57230132                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015464                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.015464                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015464                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.015464                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015464                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.015464                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -456,11 +497,17 @@ system.cpu0.dcache.demand_accesses::total     14729930                       # n
 system.cpu0.dcache.overall_accesses::cpu0.data     14729930                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.187444                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.187444                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.049753                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085817                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085817                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003753                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003753                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.133711                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.133711                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.133711                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.133711                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -548,6 +595,7 @@ system.cpu1.kern.ipl_used::0                 0.999032                       # fr
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::31                0.551247                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.730422                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::2                         2      2.00%      2.00% # number of syscalls executed
 system.cpu1.kern.syscall::3                        11     11.00%     13.00% # number of syscalls executed
 system.cpu1.kern.syscall::4                         2      2.00%     15.00% # number of syscalls executed
@@ -593,7 +641,7 @@ system.cpu1.kern.mode_good::idle                   32
 system.cpu1.kern.mode_switch_good::kernel     0.592449                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.015640                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.608089                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.334518                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_ticks::kernel        1373917500      0.07%      0.07% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle        1868002549000     99.90%    100.00% # number of ticks spent at the given mode
@@ -626,8 +674,11 @@ system.cpu1.icache.demand_accesses::total      5935766                       # n
 system.cpu1.icache.overall_accesses::cpu1.inst      5935766                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017459                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.017459                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.017459                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.017459                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.017459                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.017459                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -685,11 +736,17 @@ system.cpu1.dcache.demand_accesses::total      1884270                       # n
 system.cpu1.dcache.overall_accesses::cpu1.data      1884270                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036187                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.036187                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035266                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.035266                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078511                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.078511                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.044784                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035829                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.035829                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035829                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.035829                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 3d4adbd35..3950ce4a4 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -185,9 +185,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=true
@@ -247,10 +246,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -306,9 +304,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index f348f1381..92dc7ad3d 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:42:39
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:07:23
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 1b6d7ca40..4492aa0b0 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,23 +4,40 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1921293                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1921291                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            58540553267                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295828                       # Number of bytes of host memory used
-host_seconds                                    31.25                       # Real time elapsed on the host
+host_inst_rate                                2878195                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2878193                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            87696777763                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296144                       # Number of bytes of host memory used
+host_seconds                                    20.86                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    71650816                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 955904                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10156864                       # Number of bytes written to this memory
-system.physmem.num_reads                      1119544                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      158701                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       39167743                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    522543                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5552225                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      44719968                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            955904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          68042304                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652608                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             71650816                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       955904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          955904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10156864                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10156864                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              14936                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1063161                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1119544                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          158701                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               158701                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               522543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             37195159                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1450042                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                39167743                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          522543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             522543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5552225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5552225                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5552225                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              522543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            37195159                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1450042                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               44719968                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                       1045877                       # number of replacements
 system.l2c.tagsinuse                     33807.015903                       # Cycle average of tags in use
 system.l2c.total_refs                         2291835                       # Total number of references to valid blocks.
@@ -79,12 +96,17 @@ system.l2c.overall_accesses::cpu.data         2043063                       # nu
 system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.016231                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.543295                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.360895                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.923077                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.923077                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.390673                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.390673                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.inst        0.016231                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.520567                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.363952                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.inst       0.016231                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.520567                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.363952                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -122,9 +144,13 @@ system.iocache.demand_accesses::total           41726                       # nu
 system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -224,6 +250,7 @@ system.cpu.kern.ipl_used::0                  0.981732                       # fr
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -281,7 +308,7 @@ system.cpu.kern.mode_good::idle                   171
 system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.402439                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::idle         1801032773000     98.45%    100.00% # number of ticks spent at the given mode
@@ -345,8 +372,11 @@ system.cpu.icache.demand_accesses::total     60050143                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     60050143                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -402,10 +432,15 @@ system.cpu.dcache.demand_accesses::total     15682061                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     15682061                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180671                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180671                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.129196                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129196                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.129196                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129196                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 6299f010e..090f52454 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -274,9 +274,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=true
@@ -336,10 +335,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -395,9 +393,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index dc632ce62..b3456c80f 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:41:25
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 13:42:45
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 7ab3bb0af..e92359043 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,23 +4,50 @@ sim_seconds                                  1.958647                       # Nu
 sim_ticks                                1958647095000                       # Number of ticks simulated
 final_tick                               1958647095000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 669282                       # Simulator instruction rate (inst/s)
-host_op_rate                                   669282                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22085281308                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 295084                       # Number of bytes of host memory used
-host_seconds                                    88.69                       # Real time elapsed on the host
+host_inst_rate                                1245422                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1245421                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            41097010927                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295412                       # Number of bytes of host memory used
+host_seconds                                    47.66                       # Real time elapsed on the host
 sim_insts                                    59355643                       # Number of instructions simulated
 sim_ops                                      59355643                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    30050624                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 971200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10333120                       # Number of bytes written to this memory
-system.physmem.num_reads                       469541                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      161455                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       15342541                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    495852                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5275642                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      20618183                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0.inst           919744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         25960192                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            51456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           468416                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             30050624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       919744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        51456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          971200                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10333120                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10333120                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             14371                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            405628                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              7319                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                469541                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          161455                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               161455                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              469581                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            13254145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1353391                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               26271                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              239153                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15342541                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         469581                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          26271                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             495852                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5275642                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5275642                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5275642                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             469581                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           13254145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1353391                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              26271                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             239153                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               20618183                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        393576                       # number of replacements
 system.l2c.tagsinuse                     34487.800710                       # Cycle average of tags in use
 system.l2c.total_refs                         2371449                       # Total number of references to valid blocks.
@@ -142,38 +169,50 @@ system.l2c.ReadReq_miss_rate::cpu0.inst      0.015693                       # mi
 system.l2c.ReadReq_miss_rate::cpu0.data      0.275649                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.009368                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.033331                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.146292                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.934476                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.903285                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.929089                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.454545                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.795699                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.706349                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.408381                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.330189                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.403596                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.015693                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.304282                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.009368                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.138621                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.179301                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.015693                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.304282                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.009368                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.138621                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.179301                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52016.667760                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   914.798206                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1575.757576                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1025.780190                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6933.333333                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4216.216216                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  4674.157303                       # average SCUpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52002.375911                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52012.540780                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52012.540780                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -251,44 +290,59 @@ system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015693
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.275649                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.033331                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.146287                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.934476                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.903285                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.929089                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.454545                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.795699                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.706349                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.408381                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.330189                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.403596                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.179296                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.179296                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40012.576107                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40012.576107                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41694                       # number of replacements
 system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
@@ -324,13 +378,21 @@ system.iocache.demand_accesses::total           41726                       # nu
 system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 115247.114943                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 137701.766606                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 137608.129320                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 137608.129320                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
@@ -358,13 +420,21 @@ system.iocache.demand_mshr_miss_latency::total   3571932998
 system.iocache.overall_mshr_miss_latency::tsunami.ide   3571932998                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   3571932998                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 85604.491157                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 85604.491157                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -458,6 +528,7 @@ system.cpu0.kern.ipl_used::21                       1                       # fr
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::31                0.684822                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808938                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         8      3.60%      3.60% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.56%     12.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         4      1.80%     13.96% # number of syscalls executed
@@ -515,7 +586,7 @@ system.cpu0.kern.mode_good::idle                    0
 system.cpu0.kern.mode_switch_good::kernel     0.175705                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total          nan                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total     0.298893                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks::kernel      1954355762000     99.83%     99.83% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::user          3390072000      0.17%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
@@ -585,11 +656,17 @@ system.cpu0.icache.demand_accesses::total     54081252                       # n
 system.cpu0.icache.overall_accesses::cpu0.inst     54081252                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016933                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.016933                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016933                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.016933                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016933                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.016933                       # miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944                       # average ReadReq miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14664.130944                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14664.130944                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -613,11 +690,17 @@ system.cpu0.icache.demand_mshr_miss_latency::total  10681093500
 system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10681093500                       # number of overall MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_latency::total  10681093500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016933                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.016933                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.016933                       # mshr miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937                       # average ReadReq mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements               1338438                       # number of replacements
 system.cpu0.dcache.tagsinuse               503.524900                       # Cycle average of tags in use
@@ -677,17 +760,29 @@ system.cpu0.dcache.demand_accesses::total     14308776                       # n
 system.cpu0.dcache.overall_accesses::cpu0.data     14308776                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122512                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.122512                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049821                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.049821                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.085698                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002134                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002134                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092785                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.092785                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092785                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.092785                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161                       # average WriteReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7251.219512                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  7251.219512                       # average StoreCondReq miss latency
 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -729,20 +824,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1242107000
 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2126577000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2126577000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122512                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122512                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049821                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049821                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085698                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085698                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002134                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002134                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.092785                       # mshr miss rate for demand accesses
 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.092785                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161                       # average WriteReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4251.219512                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  4251.219512                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -820,6 +930,7 @@ system.cpu1.kern.ipl_used::0                 0.998923                       # fr
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::31                0.523674                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.710351                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::3                        11     10.58%     10.58% # number of syscalls executed
 system.cpu1.kern.syscall::6                        10      9.62%     20.19% # number of syscalls executed
 system.cpu1.kern.syscall::15                        1      0.96%     21.15% # number of syscalls executed
@@ -860,7 +971,7 @@ system.cpu1.kern.mode_good::idle                   13
 system.cpu1.kern.mode_switch_good::kernel     0.593284                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::idle      0.006298                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     1.599582                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.286315                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_ticks::kernel        3571416000      0.18%      0.18% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::user          1745054000      0.09%      0.27% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle        1953329865000     99.73%    100.00% # number of ticks spent at the given mode
@@ -899,11 +1010,17 @@ system.cpu1.icache.demand_accesses::total      5286354                       # n
 system.cpu1.icache.overall_accesses::cpu1.inst      5286354                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016458                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.016458                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016458                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.016458                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016458                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.016458                       # miss rate for overall accesses
 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683                       # average ReadReq miss latency
 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14488.908683                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14488.908683                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -927,11 +1044,17 @@ system.cpu1.icache.demand_mshr_miss_latency::total    999558500
 system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    999558500                       # number of overall MSHR miss cycles
 system.cpu1.icache.overall_mshr_miss_latency::total    999558500                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016458                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.016458                       # mshr miss rate for demand accesses
 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.016458                       # mshr miss rate for overall accesses
 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901                       # average ReadReq mshr miss latency
 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                 52960                       # number of replacements
 system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
@@ -991,17 +1114,29 @@ system.cpu1.dcache.demand_accesses::total      1677594                       # n
 system.cpu1.dcache.overall_accesses::cpu1.data      1677594                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035676                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.035676                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032042                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.032042                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.076923                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.041975                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.041975                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034296                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.034296                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034296                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.034296                       # miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778                       # average WriteReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271                       # average LoadLockedReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495                       # average StoreCondReq miss latency
 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1043,20 +1178,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    298050500
 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    309464000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_latency::total    309464000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035676                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035676                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032042                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.032042                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.076923                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.076923                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.041975                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.041975                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.034296                       # mshr miss rate for demand accesses
 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.034296                       # mshr miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778                       # average WriteReq mshr miss latency
 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271                       # average LoadLockedReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9704.950495                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  9704.950495                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index d5815e263..d6cd88975 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -181,9 +181,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=true
@@ -243,10 +242,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -302,9 +300,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index 7b3033c70..33fb3404f 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May  8 2012 15:36:31
-gem5 started May  8 2012 15:37:07
-gem5 executing on piton
+gem5 compiled Jun  4 2012 11:50:11
+gem5 started Jun  4 2012 14:23:20
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index d0852c317..42fcfede1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,23 +4,40 @@ sim_seconds                                  1.915549                       # Nu
 sim_ticks                                1915548867000                       # Number of ticks simulated
 final_tick                               1915548867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 646342                       # Simulator instruction rate (inst/s)
-host_op_rate                                   646342                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22054916762                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292620                       # Number of bytes of host memory used
-host_seconds                                    86.85                       # Real time elapsed on the host
+host_inst_rate                                1238015                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1238014                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            42244373047                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292960                       # Number of bytes of host memory used
+host_seconds                                    45.34                       # Real time elapsed on the host
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_ops                                      56137087                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    29663360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 943040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10122368                       # Number of bytes written to this memory
-system.physmem.num_reads                       463490                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      158162                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       15485567                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    492308                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5284317                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      20769884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            943040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          26067904                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652416                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             29663360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       943040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          943040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10122368                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10122368                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              14735                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             407311                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41444                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                463490                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          158162                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               158162                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               492308                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13608582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1384677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15485567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          492308                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             492308                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5284317                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5284317                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5284317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              492308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13608582                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1384677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               20769884                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        389289                       # number of replacements
 system.l2c.tagsinuse                     34352.038344                       # Cycle average of tags in use
 system.l2c.total_refs                         2311163                       # Total number of references to valid blocks.
@@ -92,20 +109,30 @@ system.l2c.overall_accesses::cpu.data         1390437                       # nu
 system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.015873                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.266420                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.150967                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.538462                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.538462                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.388905                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.388905                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.inst        0.015873                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.293215                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.182179                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.inst       0.015873                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.293215                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.182179                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52016.540189                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52003.930884                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52013.009194                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52013.009194                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -150,23 +177,36 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data   1856492500
 system.l2c.overall_mshr_uncacheable_latency::total   1856492500                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.266420                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.150967                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.538462                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.538462                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.388905                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.388905                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.182179                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.182179                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40012.996175                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40012.996175                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
@@ -202,13 +242,21 @@ system.iocache.demand_accesses::total           41725                       # nu
 system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 115265.884393                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 137714.208847                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 137621.133709                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 137621.133709                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
@@ -236,13 +284,21 @@ system.iocache.demand_mshr_miss_latency::total   3572392988
 system.iocache.overall_mshr_miss_latency::tsunami.ide   3572392988                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   3572392988                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 85617.567118                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 85617.567118                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -332,6 +388,7 @@ system.cpu.kern.ipl_used::0                  0.981746                       # fr
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::31                 0.692298                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814116                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -389,7 +446,7 @@ system.cpu.kern.mode_good::idle                   168
 system.cpu.kern.mode_switch_good::kernel     0.322887                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.403193                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.391657                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks::kernel        45253274000      2.36%      2.36% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::user           5124228000      0.27%      2.63% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::idle         1865170605000     97.37%    100.00% # number of ticks spent at the given mode
@@ -459,11 +516,17 @@ system.cpu.icache.demand_accesses::total     56148907                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     56148907                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016534                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016534                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.016534                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016534                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.016534                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016534                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14667.218001                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14667.218001                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -487,11 +550,17 @@ system.cpu.icache.demand_mshr_miss_latency::total  10830625500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10830625500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total  10830625500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016534                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016534                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016534                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1390115                       # number of replacements
 system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
@@ -547,15 +616,25 @@ system.cpu.dcache.demand_accesses::total     15029535                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120441                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120441                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049462                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049462                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085908                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.091383                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091383                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.091383                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091383                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26466.589124                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26466.589124                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -593,18 +672,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1199607500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2062370500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total   2062370500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120441                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120441                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049462                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049462                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085908                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085908                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091383                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091383                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index b18e2b725..31269f9bd 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+early_kernel_symbols=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
@@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 midr_regval=890224640
 num_work_ids=16
 readfile=tests/halt.sh
@@ -299,9 +300,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -360,10 +360,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -775,9 +774,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 17a6394ef..be4dcf157 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 10 2012 12:36:36
-gem5 started May 10 2012 12:36:42
-gem5 executing on u200540-lin
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:25:17
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 911653589000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 96669edc4..002831edb 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,32 +4,90 @@ sim_seconds                                  0.911654                       # Nu
 sim_ticks                                911653589000                       # Number of ticks simulated
 final_tick                               911653589000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1682178                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2174115                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25299801897                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379752                       # Number of bytes of host memory used
-host_seconds                                    36.03                       # Real time elapsed on the host
+host_inst_rate                                1520101                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1964640                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            22862175544                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382804                       # Number of bytes of host memory used
+host_seconds                                    39.88                       # Real time elapsed on the host
 sim_insts                                    60615585                       # Number of instructions simulated
 sim_ops                                      78342060                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    50963556                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1003776                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10224784                       # Number of bytes written to this memory
-system.physmem.num_reads                      5103504                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      869236                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       55902326                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                   1101050                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                      11215646                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      67117972                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      75                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 75                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     75                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           22                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           53                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               75                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           22                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           53                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           75                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           22                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           53                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              75                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          512                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           661924                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          6760756                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           341852                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          3873968                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             50963556                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       661924                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       341852                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1003776                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7197696                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010088                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10224784                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       4915200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            8                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             16561                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            105709                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             60557                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               5103504                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          112464                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752522                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               869236                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43132173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           562                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              726070                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             7415926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker          1123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker          1264                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              374980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4249386                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                55902326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         726070                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         374980                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1101050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           7895209                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              18647                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            3301789                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               11215646                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           7895209                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43132173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          842                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          562                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             726070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            7434574                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker         1123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker         1264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             374980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7551175                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               67117972                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        127935                       # number of replacements
 system.l2c.tagsinuse                     26245.835103                       # Cycle average of tags in use
 system.l2c.total_refs                         1477463                       # Total number of references to valid blocks.
@@ -175,12 +233,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.014612                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.073080                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.027957                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.882345                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.805848                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.855220                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.845087                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.655949                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.765972                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.590549                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.604811                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.595343                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.002262                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.003625                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.020038                       # miss rate for demand accesses
@@ -189,6 +251,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.demand_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.014612                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.274157                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.123526                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.002262                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.003625                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.020038                       # miss rate for overall accesses
@@ -197,6 +260,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker     0.003715
 system.l2c.overall_miss_rate::cpu1.itb.walker     0.011465                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.014612                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.274157                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.123526                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -308,8 +372,11 @@ system.cpu0.icache.demand_accesses::total     34685670                       # n
 system.cpu0.icache.overall_accesses::cpu0.inst     34685670                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     34685670                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.014349                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.014349                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.014349                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.014349                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.014349                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.014349                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -367,11 +434,17 @@ system.cpu0.dcache.demand_accesses::total     14721592                       # n
 system.cpu0.dcache.overall_accesses::cpu0.data     14721592                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14721592                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.030010                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.030010                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.027741                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.027741                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.054599                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.054599                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.040342                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.040342                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028976                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.028976                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028976                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.028976                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -477,8 +550,11 @@ system.cpu1.icache.demand_accesses::total     26945412                       # n
 system.cpu1.icache.overall_accesses::cpu1.inst     26945412                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total     26945412                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013596                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.013596                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013596                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.013596                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013596                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.013596                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -536,11 +612,17 @@ system.cpu1.dcache.demand_accesses::total      9644704                       # n
 system.cpu1.dcache.overall_accesses::cpu1.data      9644704                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      9644704                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.027294                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.027294                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.029093                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.029093                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.158141                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.158141                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.149298                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.149298                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027992                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.027992                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027992                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.027992                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 720edf3cb..99dc32f6e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+early_kernel_symbols=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
@@ -184,9 +185,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -245,10 +245,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -660,9 +659,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 4b3b38463..f08c091ef 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 10 2012 12:36:36
-gem5 started May 10 2012 12:36:42
-gem5 executing on u200540-lin
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:24:24
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2332330037000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index e1058fc4f..154c8ff44 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,32 +4,63 @@ sim_seconds                                  2.332330                       # Nu
 sim_ticks                                2332330037000                       # Number of ticks simulated
 final_tick                               2332330037000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1538399                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1985816                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            60412799239                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379756                       # Number of bytes of host memory used
-host_seconds                                    38.61                       # Real time elapsed on the host
+host_inst_rate                                1412842                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1823742                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            55482154888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382804                       # Number of bytes of host memory used
+host_seconds                                    42.04                       # Real time elapsed on the host
 sim_insts                                    59392246                       # Number of instructions simulated
 sim_ops                                      76665494                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                   122661296                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 941920                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  9590216                       # Number of bytes written to this memory
-system.physmem.num_reads                     14137091                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      856679                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       52591740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    403854                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       4111861                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      56703601                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                       9                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                  9                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                      9                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            941920                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10043536                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            122661296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       941920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          941920                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6574400                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9590216                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           24                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           15                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              20920                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             156964                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              14137091                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          102725                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               856679                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47880592                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            412                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               403854                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4306224                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52591740                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          403854                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             403854                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2818812                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1293049                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4111861                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2818812                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47880592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              403854                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5599273                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               56703601                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        117012                       # number of replacements
 system.l2c.tagsinuse                     24288.656748                       # Cycle average of tags in use
 system.l2c.total_refs                         1527554                       # Total number of references to valid blocks.
@@ -112,16 +143,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.003183
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.004756                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.016837                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.046592                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.025753                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.991168                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991168                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.570577                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.570577                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.003183                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.004756                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.016837                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.254824                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.116613                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.003183                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.004756                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.016837                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.254824                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.116613                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -233,8 +269,11 @@ system.cpu.icache.demand_accesses::total     60406063                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     60406063                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60406063                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014090                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014090                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014090                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014090                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.014090                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014090                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -290,10 +329,15 @@ system.cpu.dcache.demand_accesses::total     23757776                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     23757776                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     23757776                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026980                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045255                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045255                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index e58e54e5c..08257cec9 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+early_kernel_symbols=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
@@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 midr_regval=890224640
 num_work_ids=16
 readfile=tests/halt.sh
@@ -291,9 +292,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -352,10 +352,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -767,9 +766,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index d6c8fa18c..dc9f6d387 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 10 2012 12:36:36
-gem5 started May 10 2012 12:36:42
-gem5 executing on u200540-lin
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:26:08
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1169707043000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 4dc707863..c1f17df29 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -4,32 +4,90 @@ sim_seconds                                  1.169707                       # Nu
 sim_ticks                                1169707043000                       # Number of ticks simulated
 final_tick                               1169707043000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 754175                       # Simulator instruction rate (inst/s)
-host_op_rate                                   964493                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            14598169556                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379804                       # Number of bytes of host memory used
-host_seconds                                    80.13                       # Real time elapsed on the host
+host_inst_rate                                 657704                       # Simulator instruction rate (inst/s)
+host_op_rate                                   841119                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12730829062                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382856                       # Number of bytes of host memory used
+host_seconds                                    91.88                       # Real time elapsed on the host
 sim_insts                                    60429704                       # Number of instructions simulated
 sim_ops                                      77281862                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    61898788                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1004992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10078928                       # Number of bytes written to this memory
-system.physmem.num_reads                      6478591                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      867017                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       52918197                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    859183                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       8616626                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      61534823                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read                   68                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              68                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                    17                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                      58                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                 58                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                     58                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           41                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               58                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           41                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           58                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              58                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           534756                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          5211316                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker          320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           470236                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5348464                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61898788                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       534756                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       470236                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1004992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7051584                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10078928                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             14574                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             81499                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            5                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              7429                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             83596                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6478591                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          110181                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               867017                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43029277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           547                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           219                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              457171                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             4455232                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           985                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker           274                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              402012                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             4572482                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52918197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         457171                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         402012                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             859183                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           6028504                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14534                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2573588                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8616626                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           6028504                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43029277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          547                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             457171                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            4469765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          985                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker          274                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             402012                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            7146070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               61534823                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        125934                       # number of replacements
 system.l2c.tagsinuse                     27532.100282                       # Cycle average of tags in use
 system.l2c.total_refs                         1500548                       # Total number of references to valid blocks.
@@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.002559                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.016188                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.055681                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.028163                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.797203                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data     0.868377                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.826789                       # miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.717722                       # miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.700775                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.710105                       # miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data     0.569136                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data     0.605340                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.587311                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu0.dtb.walker     0.002435                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.itb.walker     0.002264                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.inst       0.019500                       # miss rate for demand accesses
@@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.demand_miss_rate::cpu1.itb.walker     0.002559                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.016188                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.307390                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.122213                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu0.dtb.walker     0.002435                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.itb.walker     0.002264                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.inst      0.019500                       # miss rate for overall accesses
@@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.overall_miss_rate::cpu1.itb.walker     0.002559                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.016188                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.307390                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.122213                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52125                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010                       # average ReadReq miss latency
@@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222
 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52152.561534                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6548.352589                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  8411.374931                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  7361.740598                       # average UpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  7160.493827                       # average SCUpgradeReq miss latency
 system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  8935.230618                       # average SCUpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52082.720239                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52125                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010                       # average overall miss latency
@@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222
 system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52096.107637                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52125                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010                       # average overall miss latency
@@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222
 system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52096.107637                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -372,12 +442,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.002559                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.016188                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.055681                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.028163                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.797203                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.868377                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.826789                       # mshr miss rate for UpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.717722                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.700775                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.710105                       # mshr miss rate for SCUpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569136                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.605340                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.587311                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.002435                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.002264                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.inst     0.019497                       # mshr miss rate for demand accesses
@@ -386,6 +460,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.002559                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.016188                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.307390                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.122213                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.002435                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.002264                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.inst     0.019497                       # mshr miss rate for overall accesses
@@ -394,6 +469,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.003159
 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.002559                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.016188                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.307390                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.122213                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184                       # average ReadReq mshr miss latency
@@ -402,12 +478,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40153.009531                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40051.711668                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40039.254171                       # average SCUpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40082.720239                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184                       # average overall mshr miss latency
@@ -416,6 +496,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222
 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40096.193198                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184                       # average overall mshr miss latency
@@ -424,16 +505,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222
 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40096.193198                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -541,11 +626,17 @@ system.cpu0.icache.demand_accesses::total     29439615                       # n
 system.cpu0.icache.overall_accesses::cpu0.inst     29439615                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     29439615                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013882                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013882                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013882                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013882                       # miss rate for demand accesses
 system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013882                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013882                       # miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14826.735750                       # average ReadReq miss latency
 system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14826.735750                       # average overall miss latency
 system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14826.735750                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -573,13 +664,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    351814000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013882                       # mshr miss rate for ReadReq accesses
 system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013882                       # mshr miss rate for demand accesses
 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013882                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013882                       # mshr miss rate for overall accesses
 system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11823.686947                       # average ReadReq mshr miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11823.686947                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11823.686947                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                335831                       # number of replacements
 system.cpu0.dcache.tagsinuse               404.122879                       # Cycle average of tags in use
@@ -639,17 +738,29 @@ system.cpu0.dcache.demand_accesses::total     12319714                       # n
 system.cpu0.dcache.overall_accesses::cpu0.data     12319714                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     12319714                       # number of overall (read+write) accesses
 system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033860                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033860                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025969                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025969                       # miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.060456                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.060456                       # miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047493                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047493                       # miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_miss_rate::cpu0.data     0.030342                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.030342                       # miss rate for demand accesses
 system.cpu0.dcache.overall_miss_rate::cpu0.data     0.030342                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.030342                       # miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15320.382890                       # average ReadReq miss latency
 system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35592.072418                       # average WriteReq miss latency
 system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11039.558127                       # average LoadLockedReq miss latency
 system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9145.766345                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9145.766345                       # average StoreCondReq miss latency
 system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 23054.541807                       # average overall miss latency
 system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23054.541807                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -691,20 +802,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    822757000
 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11246505000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11246505000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033860                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033860                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025969                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025969                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.060456                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.060456                       # mshr miss rate for LoadLockedReq accesses
 system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047474                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047474                       # mshr miss rate for StoreCondReq accesses
 system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.030342                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.030342                       # mshr miss rate for demand accesses
 system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.030342                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.030342                       # mshr miss rate for overall accesses
 system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12319.946018                       # average ReadReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32591.360717                       # average WriteReq mshr miss latency
 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  8039.558127                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8039.558127                       # average LoadLockedReq mshr miss latency
 system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6149.443774                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6149.443774                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20054.000080                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20054.000080                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
@@ -806,11 +932,17 @@ system.cpu1.icache.demand_accesses::total     32286236                       # n
 system.cpu1.icache.overall_accesses::cpu1.inst     32286236                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total     32286236                       # number of overall (read+write) accesses
 system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.014087                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.014087                       # miss rate for ReadReq accesses
 system.cpu1.icache.demand_miss_rate::cpu1.inst     0.014087                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.014087                       # miss rate for demand accesses
 system.cpu1.icache.overall_miss_rate::cpu1.inst     0.014087                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.014087                       # miss rate for overall accesses
 system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14686.743809                       # average ReadReq miss latency
 system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14686.743809                       # average overall miss latency
 system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14686.743809                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -838,13 +970,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.014087                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.014087                       # mshr miss rate for ReadReq accesses
 system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.014087                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.014087                       # mshr miss rate for demand accesses
 system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.014087                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.014087                       # mshr miss rate for overall accesses
 system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11684.088965                       # average ReadReq mshr miss latency
 system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11684.088965                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11684.088965                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                294642                       # number of replacements
 system.cpu1.dcache.tagsinuse               457.752328                       # Cycle average of tags in use
@@ -904,17 +1044,29 @@ system.cpu1.dcache.demand_accesses::total     12098117                       # n
 system.cpu1.dcache.overall_accesses::cpu1.data     12098117                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total     12098117                       # number of overall (read+write) accesses
 system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.024175                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.024175                       # miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030209                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030209                       # miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119732                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119732                       # miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.104658                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.104658                       # miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026659                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026659                       # miss rate for demand accesses
 system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026659                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026659                       # miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14503.858110                       # average ReadReq miss latency
 system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 35153.999575                       # average WriteReq miss latency
 system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11199.721298                       # average LoadLockedReq miss latency
 system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7579.207411                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  7579.207411                       # average StoreCondReq miss latency
 system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 24134.585035                       # average overall miss latency
 system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24134.585035                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -956,20 +1108,35 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39714562000
 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024175                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.024175                       # mshr miss rate for ReadReq accesses
 system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030209                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030209                       # mshr miss rate for WriteReq accesses
 system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119732                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119732                       # mshr miss rate for LoadLockedReq accesses
 system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.104604                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.104604                       # mshr miss rate for StoreCondReq accesses
 system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026659                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026659                       # mshr miss rate for demand accesses
 system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026659                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026659                       # mshr miss rate for overall accesses
 system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11503.175387                       # average ReadReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32153.756914                       # average WriteReq mshr miss latency
 system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8199.721298                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8199.721298                       # average LoadLockedReq mshr miss latency
 system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4583.110196                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  4583.110196                       # average StoreCondReq mshr miss latency
 system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21134.107546                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21134.107546                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -990,7 +1157,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273
 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_latency::total 550616164273                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index bdfa88421..6a942652a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
+early_kernel_symbols=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
@@ -180,9 +181,8 @@ type=IntrControl
 sys=system
 
 [system.iobus]
-type=Bus
+type=NoncoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -241,10 +241,9 @@ cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
-type=Bus
+type=CoherentBus
 children=badaddr_responder
 block_size=64
-bus_id=1
 clock=1000
 header_cycles=1
 use_default_range=false
@@ -656,9 +655,8 @@ output=true
 port=3456
 
 [system.toL2Bus]
-type=Bus
+type=CoherentBus
 block_size=64
-bus_id=0
 clock=1000
 header_cycles=1
 use_default_range=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index db3a98367..b6cf436ae 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled May 10 2012 12:36:36
-gem5 started May 10 2012 12:36:42
-gem5 executing on u200540-lin
+gem5 compiled Jun  4 2012 12:14:06
+gem5 started Jun  4 2012 17:25:42
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2591419000000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index c192aecc6..20ffbfc50 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,32 +4,63 @@ sim_seconds                                  2.591419                       # Nu
 sim_ticks                                2591419000000                       # Number of ticks simulated
 final_tick                               2591419000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 632591                       # Simulator instruction rate (inst/s)
-host_op_rate                                   807921                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            27699122939                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380048                       # Number of bytes of host memory used
-host_seconds                                    93.56                       # Real time elapsed on the host
+host_inst_rate                                 555808                       # Simulator instruction rate (inst/s)
+host_op_rate                                   709857                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            24337050134                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383104                       # Number of bytes of host memory used
+host_seconds                                   106.48                       # Real time elapsed on the host
 sim_insts                                    59182652                       # Number of instructions simulated
 sim_ops                                      75585847                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                   133632176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 955744                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                  9600072                       # Number of bytes written to this memory
-system.physmem.num_reads                     15512735                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      856893                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       51567182                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    368811                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       3704562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      55271744                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bytes_read                   20                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read              20                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_written                 0                       # Number of bytes written to this memory
-system.realview.nvmem.num_reads                     5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_writes                    0                       # Number of write requests responded to by this memory
-system.realview.nvmem.num_other                     0                       # Number of other requests responded to by this memory
-system.realview.nvmem.bw_read                       8                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read                  8                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total                      8                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1408                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          768                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            955744                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9990864                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            133632176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       955744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          955744                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6584000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9600072                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           22                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           12                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              21136                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             156141                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15512735                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          102875                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               856893                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47342167                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            296                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               368811                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3855364                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51567182                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          368811                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             368811                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2540693                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1163869                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3704562                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2540693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47342167                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           296                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              368811                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5019233                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               55271744                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst             8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        117210                       # number of replacements
 system.l2c.tagsinuse                     24850.634634                       # Cycle average of tags in use
 system.l2c.total_refs                         1536782                       # Total number of references to valid blocks.
@@ -131,30 +162,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.002518
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003377                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.016996                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.044928                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.025341                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.991025                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.991025                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.568473                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.568473                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.002518                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.003377                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.016996                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.252085                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.115451                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.002518                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.003377                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.016996                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.252085                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.115451                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52203.925620                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52113.632350                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52155.074026                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data   362.243121                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   362.243121                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52071.302204                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52071.302204                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52203.925620                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52075.861413                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52086.639310                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52203.925620                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52075.861413                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52086.639310                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -215,35 +256,48 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.002518
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.003377                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016996                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.044928                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.025341                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991025                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.991025                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.568473                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.568473                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.002518                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.003377                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.016996                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.252085                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.115451                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.002518                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.003377                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.016996                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.252085                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.115451                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40203.512397                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40113.602920                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40154.867958                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.684779                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40054.684779                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40071.298651                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40071.298651                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40086.598680                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40086.598680                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -351,11 +405,17 @@ system.cpu.icache.demand_accesses::total     60464458                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     60464458                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60464458                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014156                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014156                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.014156                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014156                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.014156                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014156                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14703.491239                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14703.491239                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14703.491239                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -383,13 +443,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014156                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014156                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014156                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014156                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014156                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014156                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11700.697734                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11700.697734                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11700.697734                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 627094                       # number of replacements
 system.cpu.dcache.tagsinuse                511.875591                       # Cycle average of tags in use
@@ -445,15 +513,25 @@ system.cpu.dcache.demand_accesses::total     23787844                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     23787844                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     23787844                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027178                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027178                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024500                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024500                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045914                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045914                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.026027                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026027                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.026027                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026027                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15831.273549                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38111.071410                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16292.930625                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24845.068079                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24845.068079                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -491,18 +569,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40368528500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027178                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027178                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024500                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024500                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.045914                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.045914                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026027                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026027                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026027                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12830.916839                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35110.897746                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13292.930625                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21844.785425                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21844.785425                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -523,7 +614,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263
 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263                       # number of overall MSHR uncacheable cycles
 system.iocache.overall_mshr_uncacheable_latency::total 1342278175263                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index a62c40c07..0d2987eae 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:59
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:04:41
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 344f40088..82168f91d 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,23 +4,48 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 704165                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1441828                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            18015373871                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378116                       # Number of bytes of host memory used
-host_seconds                                   283.76                       # Real time elapsed on the host
+host_inst_rate                                1304311                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2670670                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            33369516688                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 357276                       # Number of bytes of host memory used
+host_seconds                                   153.20                       # Real time elapsed on the host
 sim_insts                                   199813913                       # Number of instructions simulated
 sim_ops                                     409133277                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 972736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 12232896                       # Number of bytes written to this memory
-system.physmem.num_reads                       243261                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      191139                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        3045495                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    190283                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2392956                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       5438452                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::pc.south_bridge.ide      2786624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         1024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          704                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            972736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          11807616                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             15568704                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       972736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          972736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     12232896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          12232896                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        43541                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           16                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           11                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              15199                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             184494                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                243261                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          191139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               191139                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       545110                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            200                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            138                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               190283                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2309764                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3045495                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          190283                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             190283                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2392956                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2392956                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2392956                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       545110                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           200                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           138                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              190283                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2309764                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5438452                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        164044                       # number of replacements
 system.l2c.tagsinuse                     36842.944085                       # Cycle average of tags in use
 system.l2c.total_refs                         3332458                       # Total number of references to valid blocks.
@@ -103,16 +128,21 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.002372
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003901                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.019209                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.031181                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.026559                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.982995                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.982995                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.461240                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.461240                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.002372                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.003901                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.019209                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.114368                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.082838                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.002372                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.003901                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.019209                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.114368                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.082838                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -150,9 +180,13 @@ system.iocache.demand_accesses::total           47625                       # nu
 system.iocache.overall_accesses::pc.south_bridge.ide        47625                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47625                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -228,8 +262,11 @@ system.cpu.icache.demand_accesses::total    244157091                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    244157091                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    244157091                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003241                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.003241                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.003241                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.003241                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.003241                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.003241                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -273,8 +310,11 @@ system.cpu.itb_walker_cache.demand_accesses::total        12227
 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.349939                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.349939                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.349881                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.349881                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.349881                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.349881                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -314,8 +354,11 @@ system.cpu.dtb_walker_cache.demand_accesses::total        21808
 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21808                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21808                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.409620                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.409620                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.409620                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -361,9 +404,13 @@ system.cpu.dcache.demand_accesses::total     21764019                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     21764019                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21764019                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.097881                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.097881                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037607                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037607                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.074621                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074621                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.074621                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074621                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 70b899ba9..d30404a01 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  3 2012 13:30:44
-gem5 started Jun  3 2012 13:30:59
-gem5 executing on burrito
+gem5 compiled Jun  4 2012 13:44:28
+gem5 started Jun  4 2012 15:05:12
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 92c083c66..9cc951eb3 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,23 +4,48 @@ sim_seconds                                  5.195470                       # Nu
 sim_ticks                                5195470393000                       # Number of ticks simulated
 final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 435377                       # Simulator instruction rate (inst/s)
-host_op_rate                                   835677                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            16374771456                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 374904                       # Number of bytes of host memory used
-host_seconds                                   317.29                       # Real time elapsed on the host
+host_inst_rate                                 792632                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1521406                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            29811367673                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354100                       # Number of bytes of host memory used
+host_seconds                                   174.28                       # Real time elapsed on the host
 sim_insts                                   138138472                       # Number of instructions simulated
 sim_ops                                     265147881                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 974400                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10427072                       # Number of bytes written to this memory
-system.physmem.num_reads                       215064                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      162923                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                        2649249                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    187548                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       2006954                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                       4656204                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::pc.south_bridge.ide      2876352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            974400                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9911872                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13764096                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       974400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          974400                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10427072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10427072                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        44943                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           13                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker           10                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              15225                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             154873                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                215064                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          162923                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               162923                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       553627                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            160                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker            123                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               187548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1907791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2649249                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          187548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             187548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           2006954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2006954                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           2006954                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       553627                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           160                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              187548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1907791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4656204                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        136133                       # number of replacements
 system.l2c.tagsinuse                     31389.895470                       # Cycle average of tags in use
 system.l2c.total_refs                         3363370                       # Total number of references to valid blocks.
@@ -122,30 +147,40 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001987
 system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003286                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.019307                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.027160                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.024110                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.810539                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.810539                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.383769                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383769                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.itb.walker     0.003286                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.inst        0.019307                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.095954                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.070620                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.itb.walker     0.003286                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.inst       0.019307                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.095954                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.070620                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52255.016722                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24673.484295                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52004.897310                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52079.246541                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52079.246541                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -204,33 +239,46 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001987
 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.027160                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.024110                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.810539                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.810539                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383769                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383769                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.070620                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.070620                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40254.652764                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40254.930606                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40004.868185                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40079.117884                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40079.117884                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47510                       # number of replacements
 system.iocache.tagsinuse                     0.120586                       # Cycle average of tags in use
@@ -266,13 +314,21 @@ system.iocache.demand_accesses::total           47564                       # nu
 system.iocache.overall_accesses::pc.south_bridge.ide        47564                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 126274.800948                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 136801.779966                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 136614.983853                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 136614.983853                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      69564644                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                11299                       # number of cycles access was blocked
@@ -300,13 +356,21 @@ system.iocache.demand_mshr_miss_latency::total   4024343976
 system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4024343976                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   4024343976                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 74249.973934                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 84796.168622                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 84609.031536                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 84609.031536                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -378,11 +442,17 @@ system.cpu.icache.demand_accesses::total    159222590                       # nu
 system.cpu.icache.overall_accesses::cpu.inst    159222590                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004953                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.004953                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.004953                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.004953                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.004953                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.004953                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14812.203135                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14812.203135                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14812.203135                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -406,11 +476,17 @@ system.cpu.icache.demand_mshr_miss_latency::total   9314744000
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9314744000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total   9314744000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.004953                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.004953                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.004953                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11810.878733                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11810.878733                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11810.878733                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3754                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.070606                       # Cycle average of tags in use
@@ -450,11 +526,17 @@ system.cpu.itb_walker_cache.demand_accesses::total        12223
 system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.376565                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.376565                       # miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.376503                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.376503                       # miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.376503                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.376503                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11042.372881                       # average ReadReq miss latency
 system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11042.372881                       # average overall miss latency
 system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11042.372881                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -478,11 +560,17 @@ system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37011000
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37011000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37011000                       # number of overall MSHR miss cycles
 system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.376565                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.376565                       # mshr miss rate for ReadReq accesses
 system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.376503                       # mshr miss rate for demand accesses
 system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.376503                       # mshr miss rate for overall accesses
 system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8042.372881                       # average ReadReq mshr miss latency
 system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8042.372881                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8042.372881                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements         7704                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse        5.052403                       # Cycle average of tags in use
@@ -518,11 +606,17 @@ system.cpu.dtb_walker_cache.demand_accesses::total        21947
 system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.405340                       # miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.405340                       # miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.405340                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 11678.900629                       # average ReadReq miss latency
 system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 11678.900629                       # average overall miss latency
 system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 11678.900629                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -546,11 +640,17 @@ system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     77207000
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     77207000                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     77207000                       # number of overall MSHR miss cycles
 system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.405340                       # mshr miss rate for ReadReq accesses
 system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.405340                       # mshr miss rate for demand accesses
 system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.405340                       # mshr miss rate for overall accesses
 system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8678.844424                       # average ReadReq mshr miss latency
 system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  8678.844424                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  8678.844424                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1623424                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997312                       # Cycle average of tags in use
@@ -594,13 +694,21 @@ system.cpu.dcache.demand_accesses::total     21635359                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098647                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098647                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037778                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037778                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.075163                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.075163                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.075163                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075163                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15144.526649                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30172.881044                       # average WriteReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 18058.802043                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 18058.802043                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -634,16 +742,27 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1379728500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77305053000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total  77305053000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098647                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098647                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037778                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037778                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.075163                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.075163                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12144.494227                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27172.847747                       # average WriteReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15058.769451                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15058.769451                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------