diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
| commit | 1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch) | |
| tree | dd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/quick/fs/10.linux-boot | |
| parent | 8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff) | |
| download | gem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz | |
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
13 files changed, 2027 insertions, 1528 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index c53360e80..ee9b56ccf 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -84,9 +84,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -217,9 +214,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -393,7 +387,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -474,11 +468,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -539,10 +534,11 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -611,6 +607,7 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -1066,6 +1063,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 23c1b6367..3f9a7bd5f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -84,9 +84,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -224,10 +221,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -306,7 +304,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -352,11 +350,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -478,6 +477,7 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -933,6 +933,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 39f3dd971..f7c4e30f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -379,7 +379,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -460,11 +460,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -492,8 +493,33 @@ pio=system.membus.default [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -502,6 +528,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -515,19 +542,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 @@ -555,10 +589,11 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -627,6 +662,7 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -1082,6 +1118,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index dfa1ea355..e05c30aba 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -217,10 +217,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -299,7 +300,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -345,11 +346,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -377,8 +379,33 @@ pio=system.membus.default [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -387,6 +414,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -400,19 +428,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 @@ -501,6 +536,7 @@ HeaderType=0 InterruptLine=30 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -956,6 +992,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 9cd433cc2..2198282f2 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -37,7 +37,7 @@ load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -124,9 +124,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -143,14 +140,14 @@ icache_port=system.cpu0.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -158,15 +155,15 @@ sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu0.toL2Bus.slave[1] [system.cpu0.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -196,7 +193,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -213,40 +210,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu0.toL2Bus.slave[0] [system.cpu0.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -305,7 +302,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -322,7 +319,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -330,7 +391,7 @@ eventq_index=0 [system.cpu1] type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -355,9 +416,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -374,14 +432,14 @@ icache_port=system.cpu1.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -389,15 +447,15 @@ sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[7] +mem_side=system.cpu1.toL2Bus.slave[1] [system.cpu1.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -427,7 +485,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[11] +port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -444,40 +502,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[9] +port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[6] +mem_side=system.cpu1.toL2Bus.slave[0] [system.cpu1.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -536,7 +594,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[10] +port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -553,7 +611,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[8] +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -581,13 +703,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -612,7 +734,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -661,11 +783,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -706,12 +829,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -766,6 +889,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -850,6 +974,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain @@ -1168,15 +1302,16 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 33ea68a30..77c7c4efb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -124,9 +124,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -360,10 +357,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -396,13 +394,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -427,7 +425,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -441,11 +439,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -486,12 +485,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -546,6 +545,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -630,6 +630,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index bfa4aa6e3..a2ee5f35a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -37,7 +37,7 @@ load_offset=0 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -99,7 +99,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -136,14 +136,14 @@ icache_port=system.cpu0.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -151,15 +151,15 @@ sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu0.toL2Bus.slave[1] [system.cpu0.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -189,7 +189,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -206,40 +206,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu0.toL2Bus.slave[0] [system.cpu0.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -298,7 +298,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -315,7 +315,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -323,7 +387,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer branchPred=Null checker=Null clk_domain=system.cpu_clk_domain @@ -360,14 +424,14 @@ icache_port=system.cpu1.icache.cpu_side type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -375,15 +439,15 @@ sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[7] +mem_side=system.cpu1.toL2Bus.slave[1] [system.cpu1.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -413,7 +477,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[11] +port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -430,40 +494,40 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[9] +port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[6] +mem_side=system.cpu1.toL2Bus.slave[0] [system.cpu1.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -522,7 +586,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[10] +port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -539,7 +603,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[8] +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -567,13 +695,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -598,7 +726,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -647,11 +775,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -679,8 +808,33 @@ pio=system.membus.default [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -689,6 +843,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -702,19 +857,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 @@ -722,12 +884,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -782,6 +944,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -866,6 +1029,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain @@ -1184,15 +1357,16 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side [system.vncserver] type=VncServer diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 04e6b79a5..2c07f27f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -353,10 +353,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -389,13 +390,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -420,7 +421,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -434,11 +435,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -466,8 +468,33 @@ pio=system.membus.default [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -476,6 +503,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -489,19 +517,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 @@ -509,12 +544,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -569,6 +604,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -653,6 +689,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index a17b68bb8..3b28bd981 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -37,7 +37,7 @@ load_offset=0 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -124,9 +124,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -355,9 +352,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -501,13 +495,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -532,7 +526,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -581,11 +575,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -626,12 +621,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -686,6 +681,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -770,6 +766,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain @@ -1088,10 +1094,11 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 607c8b43e..9627624a2 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -75,7 +75,7 @@ type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 +ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -114,9 +114,6 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 -simpoint_interval=100000000 -simpoint_profile=false -simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false @@ -357,10 +354,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -389,8 +387,8 @@ transition_latency=100000000 [system.e820_table] type=X86E820Table -children=entries0 entries1 entries2 entries3 -entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +children=entries0 entries1 entries2 entries3 entries4 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4 eventq_index=0 [system.e820_table.entries0] @@ -416,6 +414,13 @@ size=133169152 [system.e820_table.entries3] type=X86E820Entry +addr=134217728 +eventq_index=0 +range_type=2 +size=3087007744 + +[system.e820_table.entries4] +type=X86E820Entry addr=4294901760 eventq_index=0 range_type=2 @@ -464,13 +469,13 @@ version=17 [system.intel_mp_table.base_entries02] type=X86IntelMPBus bus_id=0 -bus_type=ISA +bus_type=PCI eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 -bus_type=PCI +bus_type=ISA eventq_index=0 [system.intel_mp_table.base_entries04] @@ -480,7 +485,7 @@ dest_io_apic_intin=16 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=1 +source_bus_id=0 source_bus_irq=16 trigger=ConformTrigger @@ -491,7 +496,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=0 trigger=ConformTrigger @@ -502,7 +507,7 @@ dest_io_apic_intin=2 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=0 trigger=ConformTrigger @@ -513,7 +518,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=1 trigger=ConformTrigger @@ -524,7 +529,7 @@ dest_io_apic_intin=1 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=1 trigger=ConformTrigger @@ -535,7 +540,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=3 trigger=ConformTrigger @@ -546,7 +551,7 @@ dest_io_apic_intin=3 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=3 trigger=ConformTrigger @@ -557,7 +562,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=4 trigger=ConformTrigger @@ -568,7 +573,7 @@ dest_io_apic_intin=4 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=4 trigger=ConformTrigger @@ -579,7 +584,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=5 trigger=ConformTrigger @@ -590,7 +595,7 @@ dest_io_apic_intin=5 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=5 trigger=ConformTrigger @@ -601,7 +606,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=6 trigger=ConformTrigger @@ -612,7 +617,7 @@ dest_io_apic_intin=6 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=6 trigger=ConformTrigger @@ -623,7 +628,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=7 trigger=ConformTrigger @@ -634,7 +639,7 @@ dest_io_apic_intin=7 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=7 trigger=ConformTrigger @@ -645,7 +650,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=8 trigger=ConformTrigger @@ -656,7 +661,7 @@ dest_io_apic_intin=8 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=8 trigger=ConformTrigger @@ -667,7 +672,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=9 trigger=ConformTrigger @@ -678,7 +683,7 @@ dest_io_apic_intin=9 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=9 trigger=ConformTrigger @@ -689,7 +694,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=10 trigger=ConformTrigger @@ -700,7 +705,7 @@ dest_io_apic_intin=10 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=10 trigger=ConformTrigger @@ -711,7 +716,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=11 trigger=ConformTrigger @@ -722,7 +727,7 @@ dest_io_apic_intin=11 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=11 trigger=ConformTrigger @@ -733,7 +738,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=12 trigger=ConformTrigger @@ -744,7 +749,7 @@ dest_io_apic_intin=12 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=12 trigger=ConformTrigger @@ -755,7 +760,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=13 trigger=ConformTrigger @@ -766,7 +771,7 @@ dest_io_apic_intin=13 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=13 trigger=ConformTrigger @@ -777,7 +782,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=14 trigger=ConformTrigger @@ -788,15 +793,15 @@ dest_io_apic_intin=14 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=14 trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy -bus_id=0 +bus_id=1 eventq_index=0 -parent_bus=1 +parent_bus=0 subtractive_decode=true [system.intrctrl] @@ -805,7 +810,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -851,11 +856,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -1100,6 +1106,7 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=9223372036854775808 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index ec6df0068..52d540f15 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112127 # Number of seconds simulated -sim_ticks 5112126720000 # Number of ticks simulated -final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112155 # Number of seconds simulated +sim_ticks 5112155173500 # Number of ticks simulated +final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1627732 # Simulator instruction rate (inst/s) -host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41616843658 # Simulator tick rate (ticks/s) -host_mem_usage 647148 # Number of bytes of host memory used -host_seconds 122.84 # Real time elapsed on the host -sim_insts 199947158 # Number of instructions simulated -sim_ops 409371517 # Number of ops (including micro ops) simulated +host_inst_rate 1096092 # Simulator instruction rate (inst/s) +host_op_rate 2244090 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28012193632 # Simulator tick rate (ticks/s) +host_mem_usage 637772 # Number of bytes of host memory used +host_seconds 182.50 # Real time elapsed on the host +sim_insts 200033988 # Number of instructions simulated +sim_ops 409540726 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory -system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory +system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory +system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory +system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 13903648 # Transaction distribution -system.membus.trans_dist::ReadResp 13903648 # Transaction distribution -system.membus.trans_dist::WriteReq 13796 # Transaction distribution -system.membus.trans_dist::WriteResp 13796 # Transaction distribution -system.membus.trans_dist::Writeback 98213 # Transaction distribution +system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 13903768 # Transaction distribution +system.membus.trans_dist::ReadResp 13903768 # Transaction distribution +system.membus.trans_dist::WriteReq 13911 # Transaction distribution +system.membus.trans_dist::WriteResp 13911 # Transaction distribution +system.membus.trans_dist::Writeback 98349 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution -system.membus.trans_dist::ReadExReq 134490 # Transaction distribution -system.membus.trans_dist::ReadExResp 134485 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution +system.membus.trans_dist::ReadExReq 134620 # Transaction distribution +system.membus.trans_dist::ReadExResp 134615 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution system.membus.trans_dist::MessageResp 1696 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 328402 # Request fanout histogram +system.membus.snoop_fanout::samples 328677 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 328402 # Request fanout histogram +system.membus.snoop_fanout::total 328677 # Request fanout histogram system.iocache.tags.replacements 47573 # number of replacements system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy @@ -151,10 +151,10 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution -system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution -system.iobus.trans_dist::WriteReq 57577 # Transaction distribution -system.iobus.trans_dist::WriteResp 10857 # Transaction distribution +system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution +system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution +system.iobus.trans_dist::WriteReq 57692 # Transaction distribution +system.iobus.trans_dist::WriteResp 10972 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.iobus.trans_dist::MessageReq 1696 # Transaction distribution system.iobus.trans_dist::MessageResp 1696 # Transaction distribution @@ -170,18 +170,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) @@ -194,49 +194,49 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224257410 # number of cpu cycles simulated +system.cpu.numCycles 10224314318 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199947158 # Number of instructions committed -system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses +system.cpu.committedInsts 200033988 # Number of instructions committed +system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307997 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls -system.cpu.num_int_insts 374392167 # number of integer instructions +system.cpu.num_func_calls 2308777 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls +system.cpu.num_int_insts 374550150 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read -system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written +system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read +system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written -system.cpu.num_mem_refs 35671209 # number of memory refs -system.cpu.num_load_insts 27243676 # Number of load instructions -system.cpu.num_store_insts 8427533 # Number of store instructions -system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles -system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles -system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955619 # Percentage of idle cycles -system.cpu.Branches 43128209 # Number of branches fetched -system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction -system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction +system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written +system.cpu.num_mem_refs 35680563 # number of memory refs +system.cpu.num_load_insts 27249389 # Number of load instructions +system.cpu.num_store_insts 8431174 # Number of store instructions +system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles +system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles +system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955601 # Percentage of idle cycles +system.cpu.Branches 43145769 # Number of branches fetched +system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction @@ -263,54 +263,54 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409372552 # Class of executed instruction +system.cpu.op_class::total 409541761 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 791918 # number of replacements -system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 791952 # number of replacements +system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits -system.cpu.icache.overall_hits::total 243546972 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses -system.cpu.icache.overall_misses::total 792437 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits +system.cpu.icache.overall_hits::total 243645979 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses +system.cpu.icache.overall_misses::total 792471 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -321,12 +321,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id @@ -376,13 +376,13 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id @@ -390,32 +390,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428199 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,14 +424,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1623316 # number of replacements +system.cpu.dcache.tags.replacements 1623441 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -441,48 +441,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20123101 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20123101 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20182000 # number of overall hits -system.cpu.dcache.overall_hits::total 20182000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905995 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1223040 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1626101 # number of overall misses -system.cpu.dcache.overall_misses::total 1626101 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12928863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8417278 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461960 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21346141 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21346141 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21808101 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21808101 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070075 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070075 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037666 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037666 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872502 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057296 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057296 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074564 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits +system.cpu.dcache.overall_hits::total 20190999 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses +system.cpu.dcache.overall_misses::total 1626230 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -491,59 +491,59 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks -system.cpu.dcache.writebacks::total 1536734 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks +system.cpu.dcache.writebacks::total 1536849 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279540499 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 48008 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4020451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108195 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3972823 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram -system.cpu.l2cache.tags.replacements 106060 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks. +system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram +system.cpu.l2cache.tags.replacements 106197 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.551712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792069 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.159032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989107 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id @@ -551,88 +551,88 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32243624 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32243624 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7334 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1276189 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065966 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1540333 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1540333 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 180012 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 180012 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7334 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779106 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1456201 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2245978 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7334 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779106 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1456201 # number of overall hits -system.cpu.l2cache.overall_hits::total 2245978 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits +system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32226 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45550 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1809 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1809 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134768 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134768 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166994 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13318 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166994 # number of overall misses -system.cpu.l2cache.overall_misses::total 180318 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7335 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses +system.cpu.l2cache.overall_misses::total 180453 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792424 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks -system.cpu.l2cache.writebacks::total 98213 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks +system.cpu.l2cache.writebacks::total 98349 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 59e823df9..2bc3edd20 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -75,7 +75,7 @@ type=Bridge clk_domain=system.clk_domain delay=50000 eventq_index=0 -ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 +ranges=3221225472:4294901760 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -350,10 +350,11 @@ sequential_access=false size=4194304 [system.cpu.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=32 @@ -382,8 +383,8 @@ transition_latency=100000000 [system.e820_table] type=X86E820Table -children=entries0 entries1 entries2 entries3 -entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 +children=entries0 entries1 entries2 entries3 entries4 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 system.e820_table.entries4 eventq_index=0 [system.e820_table.entries0] @@ -409,6 +410,13 @@ size=133169152 [system.e820_table.entries3] type=X86E820Entry +addr=134217728 +eventq_index=0 +range_type=2 +size=3087007744 + +[system.e820_table.entries4] +type=X86E820Entry addr=4294901760 eventq_index=0 range_type=2 @@ -457,13 +465,13 @@ version=17 [system.intel_mp_table.base_entries02] type=X86IntelMPBus bus_id=0 -bus_type=ISA +bus_type=PCI eventq_index=0 [system.intel_mp_table.base_entries03] type=X86IntelMPBus bus_id=1 -bus_type=PCI +bus_type=ISA eventq_index=0 [system.intel_mp_table.base_entries04] @@ -473,7 +481,7 @@ dest_io_apic_intin=16 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=1 +source_bus_id=0 source_bus_irq=16 trigger=ConformTrigger @@ -484,7 +492,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=0 trigger=ConformTrigger @@ -495,7 +503,7 @@ dest_io_apic_intin=2 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=0 trigger=ConformTrigger @@ -506,7 +514,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=1 trigger=ConformTrigger @@ -517,7 +525,7 @@ dest_io_apic_intin=1 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=1 trigger=ConformTrigger @@ -528,7 +536,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=3 trigger=ConformTrigger @@ -539,7 +547,7 @@ dest_io_apic_intin=3 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=3 trigger=ConformTrigger @@ -550,7 +558,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=4 trigger=ConformTrigger @@ -561,7 +569,7 @@ dest_io_apic_intin=4 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=4 trigger=ConformTrigger @@ -572,7 +580,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=5 trigger=ConformTrigger @@ -583,7 +591,7 @@ dest_io_apic_intin=5 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=5 trigger=ConformTrigger @@ -594,7 +602,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=6 trigger=ConformTrigger @@ -605,7 +613,7 @@ dest_io_apic_intin=6 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=6 trigger=ConformTrigger @@ -616,7 +624,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=7 trigger=ConformTrigger @@ -627,7 +635,7 @@ dest_io_apic_intin=7 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=7 trigger=ConformTrigger @@ -638,7 +646,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=8 trigger=ConformTrigger @@ -649,7 +657,7 @@ dest_io_apic_intin=8 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=8 trigger=ConformTrigger @@ -660,7 +668,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=9 trigger=ConformTrigger @@ -671,7 +679,7 @@ dest_io_apic_intin=9 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=9 trigger=ConformTrigger @@ -682,7 +690,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=10 trigger=ConformTrigger @@ -693,7 +701,7 @@ dest_io_apic_intin=10 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=10 trigger=ConformTrigger @@ -704,7 +712,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=11 trigger=ConformTrigger @@ -715,7 +723,7 @@ dest_io_apic_intin=11 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=11 trigger=ConformTrigger @@ -726,7 +734,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=12 trigger=ConformTrigger @@ -737,7 +745,7 @@ dest_io_apic_intin=12 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=12 trigger=ConformTrigger @@ -748,7 +756,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=13 trigger=ConformTrigger @@ -759,7 +767,7 @@ dest_io_apic_intin=13 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=13 trigger=ConformTrigger @@ -770,7 +778,7 @@ dest_io_apic_intin=0 eventq_index=0 interrupt_type=ExtInt polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=14 trigger=ConformTrigger @@ -781,15 +789,15 @@ dest_io_apic_intin=14 eventq_index=0 interrupt_type=INT polarity=ConformPolarity -source_bus_id=0 +source_bus_id=1 source_bus_irq=14 trigger=ConformTrigger [system.intel_mp_table.ext_entries] type=X86IntelMPBusHierarchy -bus_id=0 +bus_id=1 eventq_index=0 -parent_bus=1 +parent_bus=0 subtractive_decode=true [system.intrctrl] @@ -798,7 +806,7 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 @@ -844,11 +852,12 @@ sequential_access=false size=1024 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -1093,6 +1102,7 @@ HeaderType=0 InterruptLine=14 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=9223372036854775808 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -1383,8 +1393,33 @@ pio=system.iobus.master[9] [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -1393,6 +1428,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -1406,19 +1442,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index c82f08e25..89c62f3e3 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.192511 # Number of seconds simulated -sim_ticks 5192511044000 # Number of ticks simulated -final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194411 # Number of seconds simulated +sim_ticks 5194410635000 # Number of ticks simulated +final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1399863 # Simulator instruction rate (inst/s) -host_op_rate 2698503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56649883486 # Simulator tick rate (ticks/s) -host_mem_usage 595716 # Number of bytes of host memory used -host_seconds 91.66 # Real time elapsed on the host -sim_insts 128310974 # Number of instructions simulated -sim_ops 247343919 # Number of ops (including micro ops) simulated +host_inst_rate 693425 # Simulator instruction rate (inst/s) +host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28047460404 # Simulator tick rate (ticks/s) +host_mem_usage 637768 # Number of bytes of host memory used +host_seconds 185.20 # Real time elapsed on the host +sim_insts 128422722 # Number of instructions simulated +sim_ops 247557000 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory -system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory +system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory +system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155196 # Number of read requests accepted -system.physmem.writeReqs 127063 # Number of write requests accepted -system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue -system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 155585 # Number of read requests accepted +system.physmem.writeReqs 127186 # Number of write requests accepted +system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue +system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10479 # Per bank write bursts -system.physmem.perBankRdBursts::1 9637 # Per bank write bursts -system.physmem.perBankRdBursts::2 10137 # Per bank write bursts -system.physmem.perBankRdBursts::3 9789 # Per bank write bursts -system.physmem.perBankRdBursts::4 9555 # Per bank write bursts -system.physmem.perBankRdBursts::5 9513 # Per bank write bursts -system.physmem.perBankRdBursts::6 9351 # Per bank write bursts -system.physmem.perBankRdBursts::7 9512 # Per bank write bursts -system.physmem.perBankRdBursts::8 9073 # Per bank write bursts -system.physmem.perBankRdBursts::9 8991 # Per bank write bursts -system.physmem.perBankRdBursts::10 9630 # Per bank write bursts -system.physmem.perBankRdBursts::11 9438 # Per bank write bursts -system.physmem.perBankRdBursts::12 9550 # Per bank write bursts -system.physmem.perBankRdBursts::13 10095 # Per bank write bursts -system.physmem.perBankRdBursts::14 10146 # Per bank write bursts -system.physmem.perBankRdBursts::15 10025 # Per bank write bursts -system.physmem.perBankWrBursts::0 8301 # Per bank write bursts -system.physmem.perBankWrBursts::1 8002 # Per bank write bursts -system.physmem.perBankWrBursts::2 8301 # Per bank write bursts -system.physmem.perBankWrBursts::3 8212 # Per bank write bursts -system.physmem.perBankWrBursts::4 7990 # Per bank write bursts -system.physmem.perBankWrBursts::5 7535 # Per bank write bursts -system.physmem.perBankWrBursts::6 7392 # Per bank write bursts -system.physmem.perBankWrBursts::7 7734 # Per bank write bursts -system.physmem.perBankWrBursts::8 7444 # Per bank write bursts -system.physmem.perBankWrBursts::9 7612 # Per bank write bursts -system.physmem.perBankWrBursts::10 7970 # Per bank write bursts -system.physmem.perBankWrBursts::11 7896 # Per bank write bursts -system.physmem.perBankWrBursts::12 8102 # Per bank write bursts -system.physmem.perBankWrBursts::13 8416 # Per bank write bursts -system.physmem.perBankWrBursts::14 8297 # Per bank write bursts -system.physmem.perBankWrBursts::15 7835 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10087 # Per bank write bursts +system.physmem.perBankRdBursts::1 9924 # Per bank write bursts +system.physmem.perBankRdBursts::2 10111 # Per bank write bursts +system.physmem.perBankRdBursts::3 9612 # Per bank write bursts +system.physmem.perBankRdBursts::4 10046 # Per bank write bursts +system.physmem.perBankRdBursts::5 9507 # Per bank write bursts +system.physmem.perBankRdBursts::6 9544 # Per bank write bursts +system.physmem.perBankRdBursts::7 9545 # Per bank write bursts +system.physmem.perBankRdBursts::8 9177 # Per bank write bursts +system.physmem.perBankRdBursts::9 9299 # Per bank write bursts +system.physmem.perBankRdBursts::10 9268 # Per bank write bursts +system.physmem.perBankRdBursts::11 9485 # Per bank write bursts +system.physmem.perBankRdBursts::12 9621 # Per bank write bursts +system.physmem.perBankRdBursts::13 9970 # Per bank write bursts +system.physmem.perBankRdBursts::14 10158 # Per bank write bursts +system.physmem.perBankRdBursts::15 10001 # Per bank write bursts +system.physmem.perBankWrBursts::0 8060 # Per bank write bursts +system.physmem.perBankWrBursts::1 7801 # Per bank write bursts +system.physmem.perBankWrBursts::2 7998 # Per bank write bursts +system.physmem.perBankWrBursts::3 7765 # Per bank write bursts +system.physmem.perBankWrBursts::4 8116 # Per bank write bursts +system.physmem.perBankWrBursts::5 7896 # Per bank write bursts +system.physmem.perBankWrBursts::6 7662 # Per bank write bursts +system.physmem.perBankWrBursts::7 7717 # Per bank write bursts +system.physmem.perBankWrBursts::8 7519 # Per bank write bursts +system.physmem.perBankWrBursts::9 7838 # Per bank write bursts +system.physmem.perBankWrBursts::10 7675 # Per bank write bursts +system.physmem.perBankWrBursts::11 7654 # Per bank write bursts +system.physmem.perBankWrBursts::12 8493 # Per bank write bursts +system.physmem.perBankWrBursts::13 8626 # Per bank write bursts +system.physmem.perBankWrBursts::14 8402 # Per bank write bursts +system.physmem.perBankWrBursts::15 7944 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 5192510980500 # Total gap between requests +system.physmem.totGap 5194410571500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155196 # Read request sizes (log2) +system.physmem.readPktSize::6 155585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127063 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127186 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see @@ -159,259 +159,261 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# What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see 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# What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads -system.physmem.totQLat 1558594500 # Total ticks spent queuing -system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads +system.physmem.totQLat 1472209750 # Total ticks spent queuing +system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing -system.physmem.readRowHits 125976 # Number of row buffer hits during reads -system.physmem.writeRowHits 98691 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes -system.physmem.avgGap 18396263.65 # Average gap between requests -system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states -system.physmem.memoryStateTime::REF 173389320000 # Time in different power states +system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing +system.physmem.readRowHits 127796 # Number of row buffer hits during reads +system.physmem.writeRowHits 98753 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes +system.physmem.avgGap 18369672.18 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states +system.physmem.memoryStateTime::REF 173452760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states +system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 214242840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 218884680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 116898375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 119431125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 608189400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 600186600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 411266160 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 411946560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 339149509920 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 339149509920 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 134171647065 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 134426407995 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 2997811704000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2997588229500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3472483457760 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3472514596380 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.748507 # Core power per rank (mW) -system.physmem.averagePower::1 668.754504 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 623858 # Transaction distribution -system.membus.trans_dist::ReadResp 623858 # Transaction distribution -system.membus.trans_dist::WriteReq 13773 # Transaction distribution -system.membus.trans_dist::WriteResp 13773 # Transaction distribution -system.membus.trans_dist::Writeback 80343 # Transaction distribution +system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.751736 # Core power per rank (mW) +system.physmem.averagePower::1 668.747452 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 624009 # Transaction distribution +system.membus.trans_dist::ReadResp 624009 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 80466 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution -system.membus.trans_dist::ReadExReq 113180 # Transaction distribution -system.membus.trans_dist::ReadExResp 113180 # Transaction distribution -system.membus.trans_dist::MessageReq 1654 # Transaction distribution -system.membus.trans_dist::MessageResp 1654 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution +system.membus.trans_dist::ReadExReq 113541 # Transaction distribution +system.membus.trans_dist::ReadExResp 113541 # Transaction distribution +system.membus.trans_dist::MessageReq 1655 # Transaction distribution +system.membus.trans_dist::MessageResp 1655 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 948 # Total snoops (count) -system.membus.snoop_fanout::samples 284802 # Request fanout histogram +system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 943 # Total snoops (count) +system.membus.snoop_fanout::samples 285344 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 284802 # Request fanout histogram -system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 285344 # Request fanout histogram +system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47504 # number of replacements -system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use +system.iocache.tags.replacements 47512 # number of replacements +system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428031 # Number of tag accesses -system.iocache.tags.data_accesses 428031 # Number of data accesses +system.iocache.tags.tag_accesses 428111 # Number of tag accesses +system.iocache.tags.data_accesses 428111 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 839 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses -system.iocache.demand_misses::total 839 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses -system.iocache.overall_misses::total 839 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles -system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses +system.iocache.ReadReq_misses::total 847 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses +system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses +system.iocache.demand_misses::total 847 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses +system.iocache.overall_misses::total 847 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles +system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked @@ -420,38 +422,38 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -465,12 +467,13 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 230144 # Transaction distribution -system.iobus.trans_dist::ReadResp 230144 # Transaction distribution -system.iobus.trans_dist::WriteReq 57579 # Transaction distribution -system.iobus.trans_dist::WriteResp 57579 # Transaction distribution -system.iobus.trans_dist::MessageReq 1654 # Transaction distribution -system.iobus.trans_dist::MessageResp 1654 # Transaction distribution +system.iobus.trans_dist::ReadReq 230267 # Transaction distribution +system.iobus.trans_dist::ReadResp 230267 # Transaction distribution +system.iobus.trans_dist::WriteReq 57693 # Transaction distribution +system.iobus.trans_dist::WriteResp 57694 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution +system.iobus.trans_dist::MessageReq 1655 # Transaction distribution +system.iobus.trans_dist::MessageResp 1655 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -483,18 +486,18 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -507,19 +510,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -545,7 +548,7 @@ system.iobus.reqLayer11.occupancy 170000 # La system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -555,47 +558,47 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10385022088 # number of cpu cycles simulated +system.cpu.numCycles 10388821270 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128310974 # Number of instructions committed -system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses +system.cpu.committedInsts 128422722 # Number of instructions committed +system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299885 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls -system.cpu.num_int_insts 231936467 # number of integer instructions +system.cpu.num_func_calls 2301199 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls +system.cpu.num_int_insts 232138334 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read -system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written +system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read +system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written -system.cpu.num_mem_refs 22243286 # number of memory refs -system.cpu.num_load_insts 13879256 # Number of load instructions -system.cpu.num_store_insts 8364030 # Number of store instructions -system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles -system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942550 # Percentage of idle cycles -system.cpu.Branches 26299942 # Number of branches fetched -system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction +system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written +system.cpu.num_mem_refs 22258678 # number of memory refs +system.cpu.num_load_insts 13887993 # Number of load instructions +system.cpu.num_store_insts 8370685 # Number of store instructions +system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles +system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942533 # Percentage of idle cycles +system.cpu.Branches 26323220 # Number of branches fetched +system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction +system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction @@ -622,66 +625,66 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247345414 # Class of executed instruction +system.cpu.op_class::total 247558577 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790109 # number of replacements -system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 791372 # number of replacements +system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits -system.cpu.icache.overall_hits::total 144545821 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses -system.cpu.icache.overall_misses::total 790628 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits +system.cpu.icache.overall_hits::total 144679417 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses +system.cpu.icache.overall_misses::total 791891 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -690,87 +693,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -779,86 +783,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 825 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 825 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4623 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4623 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4623 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4623 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4623 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38257250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38257250 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38257250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -867,169 +870,170 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1621218 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1622351 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits -system.cpu.dcache.overall_hits::total 20022219 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses -system.cpu.dcache.overall_misses::total 1633563 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses +system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits +system.cpu.dcache.overall_hits::total 20036172 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses +system.cpu.dcache.overall_misses::total 1634692 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks -system.cpu.dcache.writebacks::total 1537872 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks +system.cpu.dcache.writebacks::total 1538923 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1037,196 +1041,196 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53135 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 52938 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 87289 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87384 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141629 # Average occupied blocks per requestor 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