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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
commit8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch)
tree446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick/fs/10.linux-boot
parentfc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff)
downloadgem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt2772
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt1511
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt1342
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt410
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt4460
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt1799
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt760
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt2202
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt861
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt5179
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt2190
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt1399
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt1994
13 files changed, 13365 insertions, 13514 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 7159169af..4c75131c1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,118 +1,118 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.962843 # Number of seconds simulated
-sim_ticks 1962842856000 # Number of ticks simulated
-final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.962613 # Number of seconds simulated
+sim_ticks 1962612686500 # Number of ticks simulated
+final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1228880 # Simulator instruction rate (inst/s)
-host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39594262798 # Simulator tick rate (ticks/s)
-host_mem_usage 373652 # Number of bytes of host memory used
-host_seconds 49.57 # Real time elapsed on the host
-sim_insts 60920382 # Number of instructions simulated
-sim_ops 60920382 # Number of ops (including micro ops) simulated
+host_inst_rate 1121045 # Simulator instruction rate (inst/s)
+host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36128483856 # Simulator tick rate (ticks/s)
+host_mem_usage 373592 # Number of bytes of host memory used
+host_seconds 54.32 # Real time elapsed on the host
+sim_insts 60898638 # Number of instructions simulated
+sim_ops 60898638 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 408371 # Number of read requests accepted
-system.physmem.writeReqs 162787 # Number of write requests accepted
-system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
-system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 25705 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25985 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25737 # Per bank write bursts
-system.physmem.perBankRdBursts::3 25534 # Per bank write bursts
-system.physmem.perBankRdBursts::4 24847 # Per bank write bursts
-system.physmem.perBankRdBursts::5 24754 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25534 # Per bank write bursts
-system.physmem.perBankRdBursts::7 25489 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25150 # Per bank write bursts
-system.physmem.perBankRdBursts::9 25518 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25462 # Per bank write bursts
-system.physmem.perBankRdBursts::11 25296 # Per bank write bursts
-system.physmem.perBankRdBursts::12 25577 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25454 # Per bank write bursts
-system.physmem.perBankRdBursts::14 26241 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25977 # Per bank write bursts
-system.physmem.perBankWrBursts::0 10598 # Per bank write bursts
-system.physmem.perBankWrBursts::1 10761 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9727 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9433 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8910 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9140 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9908 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9771 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9710 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9867 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9923 # Per bank write bursts
-system.physmem.perBankWrBursts::11 10306 # Per bank write bursts
-system.physmem.perBankWrBursts::12 10733 # Per bank write bursts
-system.physmem.perBankWrBursts::13 10678 # Per bank write bursts
-system.physmem.perBankWrBursts::14 10553 # Per bank write bursts
-system.physmem.perBankWrBursts::15 10567 # Per bank write bursts
+system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 406851 # Number of read requests accepted
+system.physmem.writeReqs 161902 # Number of write requests accepted
+system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 25141 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25398 # Per bank write bursts
+system.physmem.perBankRdBursts::2 25524 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24918 # Per bank write bursts
+system.physmem.perBankRdBursts::4 25169 # Per bank write bursts
+system.physmem.perBankRdBursts::5 25258 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25808 # Per bank write bursts
+system.physmem.perBankRdBursts::7 25541 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25675 # Per bank write bursts
+system.physmem.perBankRdBursts::9 25330 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25284 # Per bank write bursts
+system.physmem.perBankRdBursts::11 25615 # Per bank write bursts
+system.physmem.perBankRdBursts::12 25647 # Per bank write bursts
+system.physmem.perBankRdBursts::13 25653 # Per bank write bursts
+system.physmem.perBankRdBursts::14 25754 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25033 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8965 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8625 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8456 # Per bank write bursts
+system.physmem.perBankWrBursts::3 7799 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8065 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8041 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8610 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8172 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8465 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8053 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8222 # Per bank write bursts
+system.physmem.perBankWrBursts::11 8481 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8850 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9510 # Per bank write bursts
+system.physmem.perBankWrBursts::14 9309 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8651 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1962837817500 # Total gap between requests
+system.physmem.numWrRetry 56 # Number of times write queue was full causing retry
+system.physmem.totGap 1962566141500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 408371 # Read request sizes (log2)
+system.physmem.readPktSize::6 406851 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 162787 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 161902 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
@@ -158,185 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads
-system.physmem.totQLat 2189518000 # Total ticks spent queuing
-system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads
+system.physmem.totQLat 2137453500 # Total ticks spent queuing
+system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing
-system.physmem.readRowHits 365775 # Number of row buffer hits during reads
-system.physmem.writeRowHits 133752 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes
-system.physmem.avgGap 3436593.41 # Average gap between requests
-system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ)
-system.physmem_0.averagePower 670.687203 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states
+system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 364433 # Number of row buffer hits during reads
+system.physmem.writeRowHits 110956 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes
+system.physmem.avgGap 3450647.54 # Average gap between requests
+system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ)
+system.physmem_0.averagePower 670.688732 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states
+system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ)
-system.physmem_1.averagePower 670.737211 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states
+system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ)
+system.physmem_1.averagePower 670.721130 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states
+system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 7535038 # DTB read hits
-system.cpu0.dtb.read_misses 7765 # DTB read misses
+system.cpu0.dtb.read_hits 7492205 # DTB read hits
+system.cpu0.dtb.read_misses 7443 # DTB read misses
system.cpu0.dtb.read_acv 210 # DTB read access violations
-system.cpu0.dtb.read_accesses 524069 # DTB read accesses
-system.cpu0.dtb.write_hits 5127057 # DTB write hits
-system.cpu0.dtb.write_misses 910 # DTB write misses
-system.cpu0.dtb.write_acv 133 # DTB write access violations
-system.cpu0.dtb.write_accesses 202595 # DTB write accesses
-system.cpu0.dtb.data_hits 12662095 # DTB hits
-system.cpu0.dtb.data_misses 8675 # DTB misses
-system.cpu0.dtb.data_acv 343 # DTB access violations
-system.cpu0.dtb.data_accesses 726664 # DTB accesses
-system.cpu0.itb.fetch_hits 3654300 # ITB hits
-system.cpu0.itb.fetch_misses 3984 # ITB misses
+system.cpu0.dtb.read_accesses 490673 # DTB read accesses
+system.cpu0.dtb.write_hits 5067323 # DTB write hits
+system.cpu0.dtb.write_misses 813 # DTB write misses
+system.cpu0.dtb.write_acv 134 # DTB write access violations
+system.cpu0.dtb.write_accesses 187452 # DTB write accesses
+system.cpu0.dtb.data_hits 12559528 # DTB hits
+system.cpu0.dtb.data_misses 8256 # DTB misses
+system.cpu0.dtb.data_acv 344 # DTB access violations
+system.cpu0.dtb.data_accesses 678125 # DTB accesses
+system.cpu0.itb.fetch_hits 3501951 # ITB hits
+system.cpu0.itb.fetch_misses 3871 # ITB misses
system.cpu0.itb.fetch_acv 184 # ITB acv
-system.cpu0.itb.fetch_accesses 3658284 # ITB accesses
+system.cpu0.itb.fetch_accesses 3505822 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
@@ -349,241 +354,240 @@ system.cpu0.itb.data_hits 0 # DT
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3925685712 # number of cpu cycles simulated
+system.cpu0.numCycles 3923838766 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 47981838 # Number of instructions committed
-system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses
-system.cpu0.num_func_calls 1202945 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 44508329 # number of integer instructions
-system.cpu0.num_fp_insts 212945 # number of float instructions
-system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written
-system.cpu0.num_mem_refs 12703139 # number of memory refs
-system.cpu0.num_load_insts 7562835 # Number of load instructions
-system.cpu0.num_store_insts 5140304 # Number of store instructions
-system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles
-system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles
-system.cpu0.Branches 7224625 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction
-system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction
-system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction
-system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction
-system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction
-system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 47743384 # Number of instructions committed
+system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses
+system.cpu0.num_func_calls 1202353 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 44279734 # number of integer instructions
+system.cpu0.num_fp_insts 210698 # number of float instructions
+system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12599731 # number of memory refs
+system.cpu0.num_load_insts 7519361 # Number of load instructions
+system.cpu0.num_store_insts 5080370 # Number of store instructions
+system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles
+system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles
+system.cpu0.Branches 7198745 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction
+system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction
+system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction
+system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction
+system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction
+system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 47990856 # Class of executed instruction
+system.cpu0.op_class::total 47751984 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
-system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
-system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
-system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
-system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
-system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
-system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
-system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 234 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
+system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
+system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
+system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
+system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
+system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
+system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
+system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed
-system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed
-system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
-system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 149871 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
+system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 149812 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1369
-system.cpu0.kern.mode_good::user 1370
+system.cpu0.kern.mode_good::kernel 1282
+system.cpu0.kern.mode_good::user 1282
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3098 # number of times the context was actually changed
-system.cpu0.dcache.tags.replacements 1190069 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -592,62 +596,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -655,59 +659,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -716,51 +718,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.dtb.data_accesses 344610 # DTB accesses
+system.cpu1.itb.fetch_hits 1964101 # ITB hits
+system.cpu1.itb.fetch_misses 1216 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1809833 # ITB accesses
+system.cpu1.itb.fetch_accesses 1965317 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -773,219 +775,220 @@ system.cpu1.itb.data_hits 0 # DT
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3923834021 # number of cpu cycles simulated
+system.cpu1.numCycles 3925225373 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 12938544 # Number of instructions committed
-system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses
-system.cpu1.num_func_calls 411382 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 11924615 # number of integer instructions
-system.cpu1.num_fp_insts 171199 # number of float instructions
-system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4106042 # number of memory refs
-system.cpu1.num_load_insts 2395192 # Number of load instructions
-system.cpu1.num_store_insts 1710850 # Number of store instructions
-system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles
-system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles
-system.cpu1.Branches 1847277 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction
-system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction
-system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction
-system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction
-system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction
-system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 13155254 # Number of instructions committed
+system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses
+system.cpu1.num_func_calls 411301 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 12132982 # number of integer instructions
+system.cpu1.num_fp_insts 173111 # number of float instructions
+system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4200357 # number of memory refs
+system.cpu1.num_load_insts 2433886 # Number of load instructions
+system.cpu1.num_store_insts 1766471 # Number of store instructions
+system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles
+system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles
+system.cpu1.Branches 1871330 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction
+system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction
+system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction
+system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction
+system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction
+system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 12941423 # Class of executed instruction
+system.cpu1.op_class::total 13158616 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
-system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
-system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
-system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
-system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
-system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
-system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 92 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
+system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
+system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
+system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
+system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed
-system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed
-system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
-system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
+system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed
+system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
+system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 71468 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 804
-system.cpu1.kern.mode_good::user 368
-system.cpu1.kern.mode_good::idle 436
-system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 71473 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 463 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 890
+system.cpu1.kern.mode_good::user 463
+system.cpu1.kern.mode_good::idle 427
+system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1968 # number of times the context was actually changed
-system.cpu1.dcache.tags.replacements 157282 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits
-system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -994,62 +997,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -1057,58 +1060,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 318148 # number of replacements
-system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses
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-system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits
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-system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles
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-system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency
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+system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1117,30 +1121,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles
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+system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -1156,11 +1160,11 @@ system.disk2.dma_write_bytes 8192 # Nu
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
-system.iobus.trans_dist::WriteReq 55631 # Transaction distribution
-system.iobus.trans_dist::WriteResp 14079 # Transaction distribution
+system.iobus.trans_dist::WriteReq 55604 # Transaction distribution
+system.iobus.trans_dist::WriteResp 14052 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
@@ -1171,12 +1175,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
@@ -1187,13 +1191,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
@@ -1213,52 +1217,52 @@ system.iobus.reqLayer27.occupancy 76000 # La
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
@@ -1267,40 +1271,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency
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-system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.writebacks::total 41520 # number of writebacks
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-system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -1309,189 +1313,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1626,96 +1630,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 292731 # Transaction distribution
-system.membus.trans_dist::ReadResp 292731 # Transaction distribution
-system.membus.trans_dist::WriteReq 14079 # Transaction distribution
-system.membus.trans_dist::WriteResp 14079 # Transaction distribution
-system.membus.trans_dist::Writeback 121235 # Transaction distribution
+system.membus.trans_dist::ReadReq 292759 # Transaction distribution
+system.membus.trans_dist::ReadResp 292759 # Transaction distribution
+system.membus.trans_dist::WriteReq 14052 # Transaction distribution
+system.membus.trans_dist::WriteResp 14052 # Transaction distribution
+system.membus.trans_dist::Writeback 120350 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution
-system.membus.trans_dist::ReadExReq 124107 # Transaction distribution
-system.membus.trans_dist::ReadExResp 123261 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution
+system.membus.trans_dist::ReadExReq 122543 # Transaction distribution
+system.membus.trans_dist::ReadExResp 121713 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 22119 # Total snoops (count)
-system.membus.snoop_fanout::samples 600328 # Request fanout histogram
+system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 21558 # Total snoops (count)
+system.membus.snoop_fanout::samples 597341 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 600328 # Request fanout histogram
-system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 597341 # Request fanout histogram
+system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 99473 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 98552 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 5c3a9c7d0..d63246d54 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,107 +1,107 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.920419 # Number of seconds simulated
-sim_ticks 1920418772000 # Number of ticks simulated
-final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.922414 # Number of seconds simulated
+sim_ticks 1922413663500 # Number of ticks simulated
+final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1235696 # Simulator instruction rate (inst/s)
-host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42298287542 # Simulator tick rate (ticks/s)
-host_mem_usage 370580 # Number of bytes of host memory used
-host_seconds 45.40 # Real time elapsed on the host
-sim_insts 56102800 # Number of instructions simulated
-sim_ops 56102800 # Number of ops (including micro ops) simulated
+host_inst_rate 1122927 # Simulator instruction rate (inst/s)
+host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38428929684 # Simulator tick rate (ticks/s)
+host_mem_usage 370248 # Number of bytes of host memory used
+host_seconds 50.03 # Real time elapsed on the host
+sim_insts 56174594 # Number of instructions simulated
+sim_ops 56174594 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 401711 # Number of read requests accepted
-system.physmem.writeReqs 157234 # Number of write requests accepted
-system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one
+system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 401737 # Number of read requests accepted
+system.physmem.writeReqs 157245 # Number of write requests accepted
+system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM
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+system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 1920406851000 # Total gap between requests
+system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
+system.physmem.totGap 1922401791500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 401711 # Read request sizes (log2)
+system.physmem.readPktSize::6 401737 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 157234 # Write request sizes (log2)
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system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
@@ -148,184 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh
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-system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads
-system.physmem.totQLat 2115529750 # Total ticks spent queuing
-system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads
+system.physmem.totQLat 2057087750 # Total ticks spent queuing
+system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing
-system.physmem.readRowHits 359951 # Number of row buffer hits during reads
-system.physmem.writeRowHits 130246 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes
-system.physmem.avgGap 3435770.69 # Average gap between requests
-system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ)
-system.physmem_0.averagePower 670.686102 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states
+system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing
+system.physmem.readRowHits 360176 # Number of row buffer hits during reads
+system.physmem.writeRowHits 107764 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes
+system.physmem.avgGap 3439112.16 # Average gap between requests
+system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ)
+system.physmem_0.averagePower 670.677845 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states
+system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ)
-system.physmem_1.averagePower 670.730762 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states
+system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ)
+system.physmem_1.averagePower 670.732006 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states
+system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9052701 # DTB read hits
-system.cpu.dtb.read_misses 10312 # DTB read misses
+system.cpu.dtb.read_hits 9063642 # DTB read hits
+system.cpu.dtb.read_misses 10324 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728817 # DTB read accesses
-system.cpu.dtb.write_hits 6349364 # DTB write hits
-system.cpu.dtb.write_misses 1140 # DTB write misses
+system.cpu.dtb.read_accesses 728853 # DTB read accesses
+system.cpu.dtb.write_hits 6355525 # DTB write hits
+system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_accesses 291929 # DTB write accesses
-system.cpu.dtb.data_hits 15402065 # DTB hits
-system.cpu.dtb.data_misses 11452 # DTB misses
+system.cpu.dtb.write_accesses 291931 # DTB write accesses
+system.cpu.dtb.data_hits 15419167 # DTB hits
+system.cpu.dtb.data_misses 11466 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_accesses 1020746 # DTB accesses
-system.cpu.itb.fetch_hits 4973977 # ITB hits
-system.cpu.itb.fetch_misses 4997 # ITB misses
+system.cpu.dtb.data_accesses 1020784 # DTB accesses
+system.cpu.itb.fetch_hits 4974414 # ITB hits
+system.cpu.itb.fetch_misses 5010 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4978974 # ITB accesses
+system.cpu.itb.fetch_accesses 4979424 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -338,87 +343,87 @@ system.cpu.itb.data_hits 0 # DT
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3840837544 # number of cpu cycles simulated
+system.cpu.numCycles 3844827327 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56102800 # Number of instructions committed
-system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
-system.cpu.num_func_calls 1481300 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls
-system.cpu.num_int_insts 51978055 # number of integer instructions
-system.cpu.num_fp_insts 324393 # number of float instructions
-system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
-system.cpu.num_mem_refs 15454652 # number of memory refs
-system.cpu.num_load_insts 9089529 # Number of load instructions
-system.cpu.num_store_insts 6365123 # Number of store instructions
-system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles
-system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles
-system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.934485 # Percentage of idle cycles
-system.cpu.Branches 8412940 # Number of branches fetched
-system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction
-system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction
-system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
-system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
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-system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
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-system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
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-system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
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-system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
-system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction
-system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction
-system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction
+system.cpu.committedInsts 56174594 # Number of instructions committed
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+system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
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+system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls
+system.cpu.num_int_insts 52047018 # number of integer instructions
+system.cpu.num_fp_insts 324460 # number of float instructions
+system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read
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+system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
+system.cpu.num_mem_refs 15471782 # number of memory refs
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+system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.933046 # Percentage of idle cycles
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+system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 56114619 # Class of executed instruction
+system.cpu.op_class::total 56186427 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
@@ -454,10 +459,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed
system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
@@ -466,101 +471,101 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu
system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192900 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1913
-system.cpu.kern.mode_good::user 1743
+system.cpu.kern.callpal::total 192894 # number of callpals executed
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+system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1910
+system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4177 # number of times the context was actually changed
-system.cpu.dcache.tags.replacements 1389979 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
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+system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode
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+system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode
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+system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency
+system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -569,54 +574,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks
-system.cpu.dcache.writebacks::total 834368 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency
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-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks
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-system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -889,41 +894,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 41901 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -996,23 +1001,23 @@ system.iobus.reqLayer27.occupancy 76000 # La
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks)
+system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks)
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
-system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -1026,14 +1031,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
@@ -1050,19 +1055,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -1076,14 +1081,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -1092,57 +1097,57 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 292351 # Transaction distribution
-system.membus.trans_dist::ReadResp 292351 # Transaction distribution
+system.membus.trans_dist::ReadReq 292358 # Transaction distribution
+system.membus.trans_dist::ReadResp 292358 # Transaction distribution
system.membus.trans_dist::WriteReq 9650 # Transaction distribution
system.membus.trans_dist::WriteResp 9650 # Transaction distribution
-system.membus.trans_dist::Writeback 115682 # Transaction distribution
+system.membus.trans_dist::Writeback 115693 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
-system.membus.trans_dist::ReadExReq 116719 # Transaction distribution
-system.membus.trans_dist::ReadExResp 116719 # Transaction distribution
+system.membus.trans_dist::ReadExReq 116738 # Transaction distribution
+system.membus.trans_dist::ReadExResp 116738 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 431 # Total snoops (count)
-system.membus.snoop_fanout::samples 559506 # Request fanout histogram
+system.membus.snoop_fanout::samples 559589 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 559506 # Request fanout histogram
-system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 559589 # Request fanout histogram
+system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index def60114c..cb5fe02ce 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -1,73 +1,73 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.802895 # Number of seconds simulated
-sim_ticks 2802895103500 # Number of ticks simulated
-final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2802894699500 # Number of ticks simulated
+final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 834307 # Simulator instruction rate (inst/s)
-host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15926512431 # Simulator tick rate (ticks/s)
-host_mem_usage 572876 # Number of bytes of host memory used
-host_seconds 175.99 # Real time elapsed on the host
-sim_insts 146829031 # Number of instructions simulated
-sim_ops 178908942 # Number of ops (including micro ops) simulated
+host_inst_rate 1337323 # Simulator instruction rate (inst/s)
+host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25528979782 # Simulator tick rate (ticks/s)
+host_mem_usage 626168 # Number of bytes of host memory used
+host_seconds 109.79 # Real time elapsed on the host
+sim_insts 146828240 # Number of instructions simulated
+sim_ops 178908039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
@@ -142,9 +142,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573
system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 20339962 # DTB read hits
+system.cpu0.dtb.read_hits 20339720 # DTB read hits
system.cpu0.dtb.read_misses 6874 # DTB read misses
-system.cpu0.dtb.write_hits 16391171 # DTB write hits
+system.cpu0.dtb.write_hits 16391078 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@@ -155,12 +155,12 @@ system.cpu0.dtb.align_faults 0 # Nu
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 20346836 # DTB read accesses
-system.cpu0.dtb.write_accesses 16392264 # DTB write accesses
+system.cpu0.dtb.read_accesses 20346594 # DTB read accesses
+system.cpu0.dtb.write_accesses 16392171 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 36731133 # DTB hits
+system.cpu0.dtb.hits 36730798 # DTB hits
system.cpu0.dtb.misses 7967 # DTB misses
-system.cpu0.dtb.accesses 36739100 # DTB accesses
+system.cpu0.dtb.accesses 36738765 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -208,7 +208,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 97440315 # ITB inst hits
+system.cpu0.itb.inst_hits 97439331 # ITB inst hits
system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -225,37 +225,37 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses
-system.cpu0.itb.hits 97440315 # DTB hits
+system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses
+system.cpu0.itb.hits 97439331 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
-system.cpu0.itb.accesses 97443673 # DTB accesses
-system.cpu0.numCycles 5605792176 # number of cpu cycles simulated
+system.cpu0.itb.accesses 97442689 # DTB accesses
+system.cpu0.numCycles 5605791368 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 95427853 # Number of instructions committed
-system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses
+system.cpu0.committedInsts 95426926 # Number of instructions committed
+system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
-system.cpu0.num_func_calls 8000324 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 100763618 # number of integer instructions
+system.cpu0.num_func_calls 8000180 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 100762696 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
-system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written
-system.cpu0.num_mem_refs 37874145 # number of memory refs
-system.cpu0.num_load_insts 20597552 # Number of load instructions
-system.cpu0.num_store_insts 17276593 # Number of store instructions
-system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles
-system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles
+system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written
+system.cpu0.num_mem_refs 37873810 # number of memory refs
+system.cpu0.num_load_insts 20597310 # Number of load instructions
+system.cpu0.num_store_insts 17276500 # Number of store instructions
+system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles
+system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
-system.cpu0.Branches 21941792 # Number of branches fetched
+system.cpu0.Branches 21941499 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction
+system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction
system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
@@ -284,20 +284,20 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
-system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 116883193 # Class of executed instruction
+system.cpu0.op_class::total 116882065 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 693476 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 693477 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
@@ -305,50 +305,50 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits
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system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
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system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
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system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
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system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses
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system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
@@ -357,8 +357,8 @@ system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses
@@ -371,14 +371,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu0.icache.tags.replacements 1109735 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use
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system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy
@@ -388,26 +388,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212
system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses
@@ -429,123 +429,123 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 #
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
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-system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits
+system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits
+system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits
+system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits
+system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits
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+system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits
+system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits
+system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses
+system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses
+system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses
+system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses
+system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses
+system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses
+system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses
+system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses
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+system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses
+system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses
+system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses
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+system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses
+system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses
+system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses)
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+system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses)
-system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses
-system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses
-system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses
+system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses
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+system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses
+system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses
+system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -554,45 +554,43 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks
-system.cpu0.l2cache.writebacks::total 192841 # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks
+system.cpu0.l2cache.writebacks::total 192974 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 322042 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 322019 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -642,9 +640,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588
system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 12173884 # DTB read hits
+system.cpu1.dtb.read_hits 12173916 # DTB read hits
system.cpu1.dtb.read_misses 2852 # DTB read misses
-system.cpu1.dtb.write_hits 7587193 # DTB write hits
+system.cpu1.dtb.write_hits 7587209 # DTB write hits
system.cpu1.dtb.write_misses 506 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@@ -655,12 +653,12 @@ system.cpu1.dtb.align_faults 0 # Nu
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 12176736 # DTB read accesses
-system.cpu1.dtb.write_accesses 7587699 # DTB write accesses
+system.cpu1.dtb.read_accesses 12176768 # DTB read accesses
+system.cpu1.dtb.write_accesses 7587715 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 19761077 # DTB hits
+system.cpu1.dtb.hits 19761125 # DTB hits
system.cpu1.dtb.misses 3358 # DTB misses
-system.cpu1.dtb.accesses 19764435 # DTB accesses
+system.cpu1.dtb.accesses 19764483 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -708,7 +706,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 53671431 # ITB inst hits
+system.cpu1.itb.inst_hits 53671575 # ITB inst hits
system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
@@ -725,37 +723,37 @@ system.cpu1.itb.domain_faults 0 # Nu
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses
-system.cpu1.itb.hits 53671431 # DTB hits
+system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses
+system.cpu1.itb.hits 53671575 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
-system.cpu1.itb.accesses 53673165 # DTB accesses
-system.cpu1.numCycles 5605321082 # number of cpu cycles simulated
+system.cpu1.itb.accesses 53673309 # DTB accesses
+system.cpu1.numCycles 5605320274 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 51401178 # Number of instructions committed
-system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses
+system.cpu1.committedInsts 51401314 # Number of instructions committed
+system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
-system.cpu1.num_func_calls 9170823 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 56984089 # number of integer instructions
+system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 56984241 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
-system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written
-system.cpu1.num_mem_refs 20026333 # number of memory refs
-system.cpu1.num_load_insts 12289505 # Number of load instructions
-system.cpu1.num_store_insts 7736828 # Number of store instructions
-system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles
-system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles
+system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written
+system.cpu1.num_mem_refs 20026381 # number of memory refs
+system.cpu1.num_load_insts 12289537 # Number of load instructions
+system.cpu1.num_store_insts 7736844 # Number of store instructions
+system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles
+system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
-system.cpu1.Branches 15217445 # Number of branches fetched
+system.cpu1.Branches 15217493 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction
+system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction
system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
@@ -784,70 +782,70 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction
-system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction
+system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 65459288 # Class of executed instruction
+system.cpu1.op_class::total 65459464 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 191938 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits
+system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
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+system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits
-system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits
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+system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 259820 # number of overall misses
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-system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses
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+system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses
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+system.cpu1.dcache.overall_misses::total 259817 # number of overall misses
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+system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses
@@ -856,10 +854,10 @@ system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -870,42 +868,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks
-system.cpu1.dcache.writebacks::total 120709 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks
+system.cpu1.dcache.writebacks::total 120855 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 523373 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses
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-system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits
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-system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 53148636 # number of overall hits
+system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses
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+system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits
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system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses
system.cpu1.icache.overall_misses::total 523885 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses
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+system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
@@ -927,88 +925,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 #
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 48598 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements 48604 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor
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system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy
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system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits
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+system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses
+system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits
+system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits
+system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits
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+system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits
+system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits
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+system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses
+system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses
+system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses
+system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses
+system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses
+system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses
+system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses
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+system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses
+system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses
+system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
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+system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses
+system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses
+system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses
@@ -1021,27 +1019,27 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996
system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1050,51 +1048,49 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks
-system.cpu1.l2cache.writebacks::total 32919 # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks
+system.cpu1.l2cache.writebacks::total 32977 # number of writebacks
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 499587 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 499492 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
-system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
+system.iobus.trans_dist::WriteResp 23195 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
@@ -1115,11 +1111,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
@@ -1140,10 +1136,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses
+system.l2c.overall_misses::cpu1.inst 2365 # number of overall misses
+system.l2c.overall_misses::cpu1.data 16940 # number of overall misses
+system.l2c.overall_misses::total 184325 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 78 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 44759 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 87381 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1378,49 +1374,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 94860 # number of writebacks
-system.l2c.writebacks::total 94860 # number of writebacks
+system.l2c.writebacks::writebacks 94914 # number of writebacks
+system.l2c.writebacks::total 94914 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 75978 # Transaction distribution
-system.membus.trans_dist::ReadResp 75978 # Transaction distribution
-system.membus.trans_dist::WriteReq 30905 # Transaction distribution
-system.membus.trans_dist::WriteResp 30905 # Transaction distribution
-system.membus.trans_dist::Writeback 131050 # Transaction distribution
+system.membus.trans_dist::ReadReq 75966 # Transaction distribution
+system.membus.trans_dist::ReadResp 75966 # Transaction distribution
+system.membus.trans_dist::WriteReq 30891 # Transaction distribution
+system.membus.trans_dist::WriteResp 30891 # Transaction distribution
+system.membus.trans_dist::Writeback 131104 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution
-system.membus.trans_dist::ReadExReq 196304 # Transaction distribution
-system.membus.trans_dist::ReadExResp 152218 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution
+system.membus.trans_dist::ReadExReq 196339 # Transaction distribution
+system.membus.trans_dist::ReadExResp 152220 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 496844 # Request fanout histogram
+system.membus.snoop_fanout::samples 496901 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 496844 # Request fanout histogram
+system.membus.snoop_fanout::total 496901 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -1452,33 +1448,33 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes)
+system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36713 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index fb9bec115..20c993e31 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,56 +1,56 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.783867 # Number of seconds simulated
-sim_ticks 2783867165000 # Number of ticks simulated
-final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2783867052000 # Number of ticks simulated
+final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1374338 # Simulator instruction rate (inst/s)
-host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26797569978 # Simulator tick rate (ticks/s)
-host_mem_usage 615488 # Number of bytes of host memory used
-host_seconds 103.89 # Real time elapsed on the host
-sim_insts 142773109 # Number of instructions simulated
-sim_ops 173803334 # Number of ops (including micro ops) simulated
+host_inst_rate 1378466 # Simulator instruction rate (inst/s)
+host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
+host_mem_usage 614624 # Number of bytes of host memory used
+host_seconds 103.57 # Real time elapsed on the host
+sim_insts 142772879 # Number of instructions simulated
+sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
@@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865
system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31526301 # DTB read hits
+system.cpu.dtb.read_hits 31526223 # DTB read hits
system.cpu.dtb.read_misses 8581 # DTB read misses
-system.cpu.dtb.write_hits 23124463 # DTB write hits
+system.cpu.dtb.write_hits 23124452 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
@@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31534882 # DTB read accesses
-system.cpu.dtb.write_accesses 23125911 # DTB write accesses
+system.cpu.dtb.read_accesses 31534804 # DTB read accesses
+system.cpu.dtb.write_accesses 23125900 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 54650764 # DTB hits
+system.cpu.dtb.hits 54650675 # DTB hits
system.cpu.dtb.misses 10029 # DTB misses
-system.cpu.dtb.accesses 54660793 # DTB accesses
+system.cpu.dtb.accesses 54660704 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 147039592 # ITB inst hits
+system.cpu.itb.inst_hits 147039346 # ITB inst hits
system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@@ -202,37 +202,37 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
-system.cpu.itb.hits 147039592 # DTB hits
+system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
+system.cpu.itb.hits 147039346 # DTB hits
system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.accesses 147044354 # DTB accesses
-system.cpu.numCycles 5567737414 # number of cpu cycles simulated
+system.cpu.itb.accesses 147044108 # DTB accesses
+system.cpu.numCycles 5567737188 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 142773109 # Number of instructions committed
-system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
+system.cpu.committedInsts 142772879 # Number of instructions committed
+system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
-system.cpu.num_func_calls 16873879 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
-system.cpu.num_int_insts 153162826 # number of integer instructions
+system.cpu.num_func_calls 16873899 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
+system.cpu.num_int_insts 153162683 # number of integer instructions
system.cpu.num_fp_insts 11484 # number of float instructions
-system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
-system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
+system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
+system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
-system.cpu.num_mem_refs 55939365 # number of memory refs
-system.cpu.num_load_insts 31855962 # Number of load instructions
-system.cpu.num_store_insts 24083403 # Number of store instructions
-system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
-system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
+system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
+system.cpu.num_mem_refs 55939276 # number of memory refs
+system.cpu.num_load_insts 31855884 # Number of load instructions
+system.cpu.num_store_insts 24083392 # Number of store instructions
+system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
+system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
-system.cpu.Branches 36397028 # Number of branches fetched
+system.cpu.Branches 36396981 # Number of branches fetched
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
@@ -261,18 +261,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 177220138 # Class of executed instruction
+system.cpu.op_class::total 177219912 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 819403 # number of replacements
+system.cpu.dcache.tags.replacements 819402 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
@@ -282,24 +282,24 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286
system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
-system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
+system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
@@ -308,24 +308,24 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612
system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
-system.cpu.dcache.overall_misses::total 814075 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
+system.cpu.dcache.overall_misses::total 814074 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
@@ -348,14 +348,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
-system.cpu.dcache.writebacks::total 682060 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
+system.cpu.dcache.writebacks::total 682059 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 1699220 # number of replacements
+system.cpu.icache.tags.replacements 1699214 # number of replacements
system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
+system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
@@ -366,26 +366,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
-system.cpu.icache.overall_hits::total 145342961 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
-system.cpu.icache.overall_misses::total 1699738 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
+system.cpu.icache.overall_hits::total 145342721 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
+system.cpu.icache.overall_misses::total 1699732 # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
@@ -401,17 +401,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 110027 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 110026 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
@@ -428,34 +428,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
@@ -464,21 +464,21 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 147864
system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
-system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
+system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
@@ -487,19 +487,19 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
@@ -508,12 +508,12 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -524,51 +524,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
-system.cpu.l2cache.writebacks::total 101898 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
+system.cpu.l2cache.writebacks::total 101897 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
-system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
@@ -589,11 +587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
@@ -614,17 +612,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 36430 # number of replacements
-system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
@@ -667,11 +665,11 @@ system.iocache.cache_copies 0 # nu
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 74235 # Transaction distribution
-system.membus.trans_dist::ReadResp 74235 # Transaction distribution
-system.membus.trans_dist::WriteReq 27560 # Transaction distribution
-system.membus.trans_dist::WriteResp 27560 # Transaction distribution
-system.membus.trans_dist::Writeback 138088 # Transaction distribution
+system.membus.trans_dist::ReadReq 74227 # Transaction distribution
+system.membus.trans_dist::ReadResp 74227 # Transaction distribution
+system.membus.trans_dist::WriteReq 27546 # Transaction distribution
+system.membus.trans_dist::WriteResp 27546 # Transaction distribution
+system.membus.trans_dist::Writeback 138087 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
@@ -679,34 +677,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 359047 # Request fanout histogram
+system.membus.snoop_fanout::samples 359045 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 359047 # Request fanout histogram
+system.membus.snoop_fanout::total 359045 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index 391769400..64a01b6e7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,160 +1,156 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.868319 # Number of seconds simulated
-sim_ticks 2868318696500 # Number of ticks simulated
-final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.868581 # Number of seconds simulated
+sim_ticks 2868581440500 # Number of ticks simulated
+final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 534652 # Simulator instruction rate (inst/s)
-host_op_rate 646675 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11631340017 # Simulator tick rate (ticks/s)
-host_mem_usage 586476 # Number of bytes of host memory used
-host_seconds 246.60 # Real time elapsed on the host
-sim_insts 131846562 # Number of instructions simulated
-sim_ops 159471778 # Number of ops (including micro ops) simulated
+host_inst_rate 717360 # Simulator instruction rate (inst/s)
+host_op_rate 867708 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15647358559 # Simulator tick rate (ticks/s)
+host_mem_usage 639748 # Number of bytes of host memory used
+host_seconds 183.33 # Real time elapsed on the host
+sim_insts 131511324 # Number of instructions simulated
+sim_ops 159074269 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 200214 # Number of read requests accepted
-system.physmem.writeReqs 175885 # Number of write requests accepted
-system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue
-system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 12188 # Per bank write bursts
-system.physmem.perBankRdBursts::1 12046 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12591 # Per bank write bursts
-system.physmem.perBankRdBursts::3 12330 # Per bank write bursts
-system.physmem.perBankRdBursts::4 20750 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12582 # Per bank write bursts
-system.physmem.perBankRdBursts::6 12043 # Per bank write bursts
-system.physmem.perBankRdBursts::7 12246 # Per bank write bursts
-system.physmem.perBankRdBursts::8 12442 # Per bank write bursts
-system.physmem.perBankRdBursts::9 12402 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11722 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11146 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11467 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11916 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10852 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11341 # Per bank write bursts
-system.physmem.perBankWrBursts::0 10835 # Per bank write bursts
-system.physmem.perBankWrBursts::1 11264 # Per bank write bursts
-system.physmem.perBankWrBursts::2 11493 # Per bank write bursts
-system.physmem.perBankWrBursts::3 10899 # Per bank write bursts
-system.physmem.perBankWrBursts::4 10487 # Per bank write bursts
-system.physmem.perBankWrBursts::5 11152 # Per bank write bursts
-system.physmem.perBankWrBursts::6 11024 # Per bank write bursts
-system.physmem.perBankWrBursts::7 10595 # Per bank write bursts
-system.physmem.perBankWrBursts::8 10782 # Per bank write bursts
-system.physmem.perBankWrBursts::9 10958 # Per bank write bursts
-system.physmem.perBankWrBursts::10 10716 # Per bank write bursts
-system.physmem.perBankWrBursts::11 10408 # Per bank write bursts
-system.physmem.perBankWrBursts::12 10444 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9906 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9416 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9817 # Per bank write bursts
+system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 191448 # Number of read requests accepted
+system.physmem.writeReqs 168916 # Number of write requests accepted
+system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11402 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11523 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11617 # Per bank write bursts
+system.physmem.perBankRdBursts::3 11771 # Per bank write bursts
+system.physmem.perBankRdBursts::4 20348 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12097 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11123 # Per bank write bursts
+system.physmem.perBankRdBursts::7 11241 # Per bank write bursts
+system.physmem.perBankRdBursts::8 11419 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11532 # Per bank write bursts
+system.physmem.perBankRdBursts::10 11480 # Per bank write bursts
+system.physmem.perBankRdBursts::11 10715 # Per bank write bursts
+system.physmem.perBankRdBursts::12 11252 # Per bank write bursts
+system.physmem.perBankRdBursts::13 11225 # Per bank write bursts
+system.physmem.perBankRdBursts::14 11052 # Per bank write bursts
+system.physmem.perBankRdBursts::15 11518 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9249 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9496 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9535 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9435 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8870 # Per bank write bursts
+system.physmem.perBankWrBursts::5 9467 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9116 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8737 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8796 # Per bank write bursts
+system.physmem.perBankWrBursts::9 9230 # Per bank write bursts
+system.physmem.perBankWrBursts::10 9164 # Per bank write bursts
+system.physmem.perBankWrBursts::11 8822 # Per bank write bursts
+system.physmem.perBankWrBursts::12 9029 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8642 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8756 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8750 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
-system.physmem.totGap 2868318254500 # Total gap between requests
+system.physmem.numWrRetry 83 # Number of times write queue was full causing retry
+system.physmem.totGap 2868581033500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 9742 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 190444 # Read request sizes (log2)
+system.physmem.readPktSize::6 181678 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 171449 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 164480 # Write request sizes (log2)
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@@ -184,178 +180,162 @@ system.physmem.wrQLenPdf::11 1 # Wh
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+system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing
-system.physmem.readRowHits 167229 # Number of row buffer hits during reads
-system.physmem.writeRowHits 112615 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes
-system.physmem.avgGap 7626497.96 # Average gap between requests
-system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.622475 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states
+system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing
+system.physmem.readRowHits 160412 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94279 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes
+system.physmem.avgGap 7960231.97 # Average gap between requests
+system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.504870 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.527135 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states
+system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.408745 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
@@ -411,57 +391,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 7749 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 7634 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 19044092 # DTB read hits
-system.cpu0.dtb.read_misses 6608 # DTB read misses
-system.cpu0.dtb.write_hits 15688894 # DTB write hits
-system.cpu0.dtb.write_misses 1141 # DTB write misses
+system.cpu0.dtb.read_hits 25111402 # DTB read hits
+system.cpu0.dtb.read_misses 6533 # DTB read misses
+system.cpu0.dtb.write_hits 18719047 # DTB write hits
+system.cpu0.dtb.write_misses 1101 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 19050700 # DTB read accesses
-system.cpu0.dtb.write_accesses 15690035 # DTB write accesses
+system.cpu0.dtb.read_accesses 25117935 # DTB read accesses
+system.cpu0.dtb.write_accesses 18720148 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 34732986 # DTB hits
-system.cpu0.dtb.misses 7749 # DTB misses
-system.cpu0.dtb.accesses 34740735 # DTB accesses
+system.cpu0.dtb.hits 43830449 # DTB hits
+system.cpu0.dtb.misses 7634 # DTB misses
+system.cpu0.dtb.accesses 43838083 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -499,20 +480,20 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348
system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated
@@ -523,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 91510827 # ITB inst hits
+system.cpu0.itb.inst_hits 118783416 # ITB inst hits
system.cpu0.itb.inst_misses 3348 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -540,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses
-system.cpu0.itb.hits 91510827 # DTB hits
+system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses
+system.cpu0.itb.hits 118783416 # DTB hits
system.cpu0.itb.misses 3348 # DTB misses
-system.cpu0.itb.accesses 91514175 # DTB accesses
-system.cpu0.numCycles 5736637393 # number of cpu cycles simulated
+system.cpu0.itb.accesses 118786764 # DTB accesses
+system.cpu0.numCycles 5737162881 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 89363678 # Number of instructions committed
-system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses
+system.cpu0.committedInsts 115118664 # Number of instructions committed
+system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
-system.cpu0.num_func_calls 6606472 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 94350928 # number of integer instructions
+system.cpu0.num_func_calls 12673072 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 123147620 # number of integer instructions
system.cpu0.num_fp_insts 9820 # number of float instructions
-system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written
-system.cpu0.num_mem_refs 35866705 # number of memory refs
-system.cpu0.num_load_insts 19295047 # Number of load instructions
-system.cpu0.num_store_insts 16571658 # Number of store instructions
-system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles
-system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles
-system.cpu0.Branches 19970568 # Number of branches fetched
+system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written
+system.cpu0.num_mem_refs 44965604 # number of memory refs
+system.cpu0.num_load_insts 25362826 # Number of load instructions
+system.cpu0.num_store_insts 19602778 # Number of store instructions
+system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles
+system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles
+system.cpu0.Branches 29061799 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction
-system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -714,82 +695,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks
-system.cpu0.dcache.writebacks::total 504116 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks
+system.cpu0.dcache.writebacks::total 504121 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -797,58 +778,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1099798 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy
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+system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits
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-system.cpu0.icache.overall_hits::total 90410508 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total 1100319 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles
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-system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency
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@@ -857,223 +838,224 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
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@@ -1082,128 +1064,128 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
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-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency
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-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1213,57 +1195,55 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 648932 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 633519 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -1294,59 +1274,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 3332 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 3283 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10115566 # DTB read hits
-system.cpu1.dtb.read_misses 2828 # DTB read misses
-system.cpu1.dtb.write_hits 6544640 # DTB write hits
-system.cpu1.dtb.write_misses 504 # DTB write misses
+system.cpu1.dtb.read_hits 3974119 # DTB read hits
+system.cpu1.dtb.read_misses 2776 # DTB read misses
+system.cpu1.dtb.write_hits 3444686 # DTB write hits
+system.cpu1.dtb.write_misses 507 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10118394 # DTB read accesses
-system.cpu1.dtb.write_accesses 6545144 # DTB write accesses
+system.cpu1.dtb.read_accesses 3976895 # DTB read accesses
+system.cpu1.dtb.write_accesses 3445193 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 16660206 # DTB hits
-system.cpu1.dtb.misses 3332 # DTB misses
-system.cpu1.dtb.accesses 16663538 # DTB accesses
+system.cpu1.dtb.hits 7418805 # DTB hits
+system.cpu1.dtb.misses 3283 # DTB misses
+system.cpu1.dtb.accesses 7422088 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1376,42 +1359,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 1746 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 1740 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 44359905 # ITB inst hits
-system.cpu1.itb.inst_misses 1746 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 16749094 # ITB inst hits
+system.cpu1.itb.inst_misses 1740 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
@@ -1420,178 +1404,178 @@ system.cpu1.itb.flush_tlb 66 # Nu
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses
-system.cpu1.itb.hits 44359905 # DTB hits
-system.cpu1.itb.misses 1746 # DTB misses
-system.cpu1.itb.accesses 44361651 # DTB accesses
-system.cpu1.numCycles 5735725430 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses
+system.cpu1.itb.hits 16749094 # DTB hits
+system.cpu1.itb.misses 1740 # DTB misses
+system.cpu1.itb.accesses 16750834 # DTB accesses
+system.cpu1.numCycles 5736248293 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 42482884 # Number of instructions committed
-system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses
+system.cpu1.committedInsts 16392660 # Number of instructions committed
+system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
-system.cpu1.num_func_calls 7121857 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 47161467 # number of integer instructions
+system.cpu1.num_func_calls 1033061 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 17976734 # number of integer instructions
system.cpu1.num_fp_insts 1857 # number of float instructions
-system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written
-system.cpu1.num_mem_refs 16924073 # number of memory refs
-system.cpu1.num_load_insts 10229886 # Number of load instructions
-system.cpu1.num_store_insts 6694187 # Number of store instructions
-system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles
-system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles
-system.cpu1.Branches 12116511 # Number of branches fetched
+system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written
+system.cpu1.num_mem_refs 7653523 # number of memory refs
+system.cpu1.num_load_insts 4085696 # Number of load instructions
+system.cpu1.num_store_insts 3567827 # Number of store instructions
+system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles
+system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles
+system.cpu1.Branches 2968133 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction
-system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction
-system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction
-system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction
+system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction
+system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 54073981 # Class of executed instruction
+system.cpu1.op_class::total 20309210 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements 191058 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits
-system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses
-system.cpu1.dcache.overall_misses::total 260939 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1600,82 +1584,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 118649 # number of writebacks
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-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency
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-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency
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+system.cpu1.dcache.writebacks::total 117066 # number of writebacks
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@@ -1683,58 +1667,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1743,219 +1727,220 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses
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+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency
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-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -2093,64 +2078,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
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-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution
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-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 572639 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram
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+system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
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+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 567913 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31024 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31024 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59440 # Transaction distribution
-system.iobus.trans_dist::WriteResp 23216 # Transaction distribution
+system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59423 # Transaction distribution
+system.iobus.trans_dist::WriteResp 23199 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
@@ -2171,11 +2154,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
@@ -2196,11 +2179,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -2240,23 +2223,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36445 # number of replacements
-system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -2270,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 255 #
system.iocache.demand_misses::total 255 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 255 # number of overall misses
system.iocache.overall_misses::total 255 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
@@ -2294,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -2320,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 255
system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -2336,303 +2319,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 130735 # number of replacements
-system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use
-system.l2c.tags.total_refs 343053 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks.
+system.l2c.tags.replacements 120296 # number of replacements
+system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use
+system.l2c.tags.total_refs 339434 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@@ -2835,58 +2793,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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-system.membus.snoop_fanout::total 499419 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 484369 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@@ -2919,44 +2877,44 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 286323 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 289326 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index b3648bdab..08c475a80 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,120 +1,120 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.902862 # Number of seconds simulated
-sim_ticks 2902861767000 # Number of ticks simulated
-final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.903548 # Number of seconds simulated
+sim_ticks 2903547931500 # Number of ticks simulated
+final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 747193 # Simulator instruction rate (inst/s)
-host_op_rate 900893 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19275657141 # Simulator tick rate (ticks/s)
-host_mem_usage 615228 # Number of bytes of host memory used
-host_seconds 150.60 # Real time elapsed on the host
-sim_insts 112525269 # Number of instructions simulated
-sim_ops 135672104 # Number of ops (including micro ops) simulated
+host_inst_rate 732027 # Simulator instruction rate (inst/s)
+host_op_rate 882601 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 18897780106 # Simulator tick rate (ticks/s)
+host_mem_usage 614620 # Number of bytes of host memory used
+host_seconds 153.65 # Real time elapsed on the host
+sim_insts 112472279 # Number of instructions simulated
+sim_ops 135607130 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 168015 # Number of read requests accepted
-system.physmem.writeReqs 158980 # Number of write requests accepted
-system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9689 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9230 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10198 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10267 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18984 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10226 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10551 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10350 # Per bank write bursts
-system.physmem.perBankRdBursts::8 9702 # Per bank write bursts
-system.physmem.perBankRdBursts::9 9930 # Per bank write bursts
-system.physmem.perBankRdBursts::10 9908 # Per bank write bursts
-system.physmem.perBankRdBursts::11 8848 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9929 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10408 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9925 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9750 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9389 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8975 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10251 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9953 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9418 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9499 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9770 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9764 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9682 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9836 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9791 # Per bank write bursts
-system.physmem.perBankWrBursts::11 9091 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9681 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9852 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9372 # Per bank write bursts
-system.physmem.perBankWrBursts::15 9026 # Per bank write bursts
+system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 168876 # Number of read requests accepted
+system.physmem.writeReqs 160010 # Number of write requests accepted
+system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10030 # Per bank write bursts
+system.physmem.perBankRdBursts::1 9665 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10302 # Per bank write bursts
+system.physmem.perBankRdBursts::3 9920 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18863 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
+system.physmem.perBankRdBursts::6 10296 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10601 # Per bank write bursts
+system.physmem.perBankRdBursts::8 9928 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10198 # Per bank write bursts
+system.physmem.perBankRdBursts::10 9956 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9036 # Per bank write bursts
+system.physmem.perBankRdBursts::12 9857 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10481 # Per bank write bursts
+system.physmem.perBankRdBursts::14 9974 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9528 # Per bank write bursts
+system.physmem.perBankWrBursts::0 8313 # Per bank write bursts
+system.physmem.perBankWrBursts::1 8253 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9067 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8494 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8419 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8394 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8676 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8975 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8824 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8984 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8586 # Per bank write bursts
+system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8548 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8715 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8203 # Per bank write bursts
+system.physmem.perBankWrBursts::15 7843 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 2902861390500 # Total gap between requests
+system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
+system.physmem.totGap 2903547607000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 9558 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 158443 # Read request sizes (log2)
+system.physmem.readPktSize::6 159304 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 154599 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 155629 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -159,178 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation
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+system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads
-system.physmem.totQLat 1487834250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads
+system.physmem.totQLat 1499821694 # Total ticks spent queuing
+system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.06 # Data bus utilization in percentage
+system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing
-system.physmem.readRowHits 138089 # Number of row buffer hits during reads
-system.physmem.writeRowHits 122193 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes
-system.physmem.avgGap 8877387.70 # Average gap between requests
-system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.522458 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states
+system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing
+system.physmem.readRowHits 138826 # Number of row buffer hits during reads
+system.physmem.writeRowHits 106054 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes
+system.physmem.avgGap 8828431.76 # Average gap between requests
+system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.525264 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states
+system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.435479 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states
+system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.425095 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states
+system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
@@ -380,57 +365,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 9552 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks 9545 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24537663 # DTB read hits
-system.cpu.dtb.read_misses 8142 # DTB read misses
-system.cpu.dtb.write_hits 19618927 # DTB write hits
-system.cpu.dtb.write_misses 1410 # DTB write misses
+system.cpu.dtb.read_hits 24524755 # DTB read hits
+system.cpu.dtb.read_misses 8132 # DTB read misses
+system.cpu.dtb.write_hits 19610055 # DTB write hits
+system.cpu.dtb.write_misses 1413 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24545805 # DTB read accesses
-system.cpu.dtb.write_accesses 19620337 # DTB write accesses
+system.cpu.dtb.read_accesses 24532887 # DTB read accesses
+system.cpu.dtb.write_accesses 19611468 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44156590 # DTB hits
-system.cpu.dtb.misses 9552 # DTB misses
-system.cpu.dtb.accesses 44166142 # DTB accesses
+system.cpu.dtb.hits 44134810 # DTB hits
+system.cpu.dtb.misses 9545 # DTB misses
+system.cpu.dtb.accesses 44144355 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -468,18 +453,18 @@ system.cpu.itb.walker.walkWaitTime::samples 4762 #
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
@@ -490,7 +475,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 115624412 # ITB inst hits
+system.cpu.itb.inst_hits 115569545 # ITB inst hits
system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@@ -507,38 +492,38 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 115629174 # ITB inst accesses
-system.cpu.itb.hits 115624412 # DTB hits
+system.cpu.itb.inst_accesses 115574307 # ITB inst accesses
+system.cpu.itb.hits 115569545 # DTB hits
system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.accesses 115629174 # DTB accesses
-system.cpu.numCycles 5805723534 # number of cpu cycles simulated
+system.cpu.itb.accesses 115574307 # DTB accesses
+system.cpu.numCycles 5807095863 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 112525269 # Number of instructions committed
-system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses
-system.cpu.num_func_calls 9899985 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls
-system.cpu.num_int_insts 119969678 # number of integer instructions
-system.cpu.num_fp_insts 11290 # number of float instructions
-system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read
-system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read
+system.cpu.committedInsts 112472279 # Number of instructions committed
+system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
+system.cpu.num_func_calls 9892504 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls
+system.cpu.num_int_insts 119910547 # number of integer instructions
+system.cpu.num_fp_insts 11161 # number of float instructions
+system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read
+system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written
-system.cpu.num_mem_refs 45438019 # number of memory refs
-system.cpu.num_load_insts 24860597 # Number of load instructions
-system.cpu.num_store_insts 20577422 # Number of store instructions
-system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles
-system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles
-system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.927847 # Percentage of idle cycles
-system.cpu.Branches 25932360 # Number of branches fetched
+system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written
+system.cpu.num_mem_refs 45415290 # number of memory refs
+system.cpu.num_load_insts 24846976 # Number of load instructions
+system.cpu.num_store_insts 20568314 # Number of store instructions
+system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles
+system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles
+system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.927424 # Percentage of idle cycles
+system.cpu.Branches 25918910 # Number of branches fetched
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction
-system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction
+system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction
+system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
@@ -562,194 +547,194 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction
-system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction
+system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 138794587 # Class of executed instruction
+system.cpu.op_class::total 138727463 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 823321 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
+system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 820494 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits
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-system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 42354457 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses
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-system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses
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-system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 820894 # number of overall misses
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-system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles
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-system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles
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-system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked
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+system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses
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+system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.dcache.writebacks::total 686487 # number of writebacks
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -1016,100 +1001,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1119,61 +1104,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 53107 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 22814 # Transaction distribution
+system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
@@ -1194,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
@@ -1219,11 +1202,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -1263,23 +1246,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
-system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
@@ -1293,14 +1276,14 @@ system.iocache.demand_misses::realview.ide 234 #
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
@@ -1317,19 +1300,19 @@ system.iocache.demand_miss_rate::realview.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -1343,14 +1326,14 @@ system.iocache.demand_mshr_misses::realview.ide 234
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -1359,66 +1342,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 70661 # Transaction distribution
-system.membus.trans_dist::ReadResp 70661 # Transaction distribution
-system.membus.trans_dist::WriteReq 27618 # Transaction distribution
-system.membus.trans_dist::WriteResp 27618 # Transaction distribution
-system.membus.trans_dist::Writeback 118375 # Transaction distribution
+system.membus.trans_dist::ReadReq 70719 # Transaction distribution
+system.membus.trans_dist::ReadResp 70719 # Transaction distribution
+system.membus.trans_dist::WriteReq 27589 # Transaction distribution
+system.membus.trans_dist::WriteResp 27589 # Transaction distribution
+system.membus.trans_dist::Writeback 119405 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution
-system.membus.trans_dist::ReadExReq 128454 # Transaction distribution
-system.membus.trans_dist::ReadExResp 128454 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129241 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129241 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 498 # Total snoops (count)
-system.membus.snoop_fanout::samples 318040 # Request fanout histogram
+system.membus.snoop_fanout::samples 319985 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 318040 # Request fanout histogram
-system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 319985 # Request fanout histogram
+system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index f0c87683a..33aa26eaf 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -1,73 +1,73 @@
---------- Begin Simulation Statistics ----------
sim_seconds 2.783867 # Number of seconds simulated
-sim_ticks 2783867165000 # Number of ticks simulated
-final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2783867052000 # Number of ticks simulated
+final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1311458 # Simulator instruction rate (inst/s)
-host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25571502260 # Simulator tick rate (ticks/s)
-host_mem_usage 616488 # Number of bytes of host memory used
-host_seconds 108.87 # Real time elapsed on the host
-sim_insts 142773109 # Number of instructions simulated
-sim_ops 173803334 # Number of ops (including micro ops) simulated
+host_inst_rate 1291395 # Simulator instruction rate (inst/s)
+host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25180347721 # Simulator tick rate (ticks/s)
+host_mem_usage 616688 # Number of bytes of host memory used
+host_seconds 110.56 # Real time elapsed on the host
+sim_insts 142772879 # Number of instructions simulated
+sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 728420 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 728356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11540296 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 728420 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 11540232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 728356 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8837248 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8837184 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8854772 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8854708 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 19835 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 19834 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 189290 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138082 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 189289 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138081 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142463 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 142462 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 261658 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 261635 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4145419 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 261658 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4145396 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 261635 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3174450 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3174427 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3180745 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3174450 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3180722 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3174427 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 261658 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 261635 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7326164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7326119 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
@@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 5682 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 5683 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 15994592 # DTB read hits
-system.cpu0.dtb.read_misses 4787 # DTB read misses
-system.cpu0.dtb.write_hits 11285776 # DTB write hits
+system.cpu0.dtb.read_hits 15994593 # DTB read hits
+system.cpu0.dtb.read_misses 4788 # DTB read misses
+system.cpu0.dtb.write_hits 11285810 # DTB write hits
system.cpu0.dtb.write_misses 895 # DTB write misses
system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3233 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 774 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 15999379 # DTB read accesses
-system.cpu0.dtb.write_accesses 11286671 # DTB write accesses
+system.cpu0.dtb.read_accesses 15999381 # DTB read accesses
+system.cpu0.dtb.write_accesses 11286705 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 27280368 # DTB hits
-system.cpu0.dtb.misses 5682 # DTB misses
-system.cpu0.dtb.accesses 27286050 # DTB accesses
+system.cpu0.dtb.hits 27280403 # DTB hits
+system.cpu0.dtb.misses 5683 # DTB misses
+system.cpu0.dtb.accesses 27286086 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 74779253 # ITB inst hits
+system.cpu0.itb.inst_hits 74779098 # ITB inst hits
system.cpu0.itb.inst_misses 2611 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -219,38 +219,38 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 74781864 # ITB inst accesses
-system.cpu0.itb.hits 74779253 # DTB hits
+system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses
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system.cpu0.itb.misses 2611 # DTB misses
-system.cpu0.itb.accesses 74781864 # DTB accesses
-system.cpu0.numCycles 5536444795 # number of cpu cycles simulated
+system.cpu0.itb.accesses 74781709 # DTB accesses
+system.cpu0.numCycles 5536444792 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 72626511 # Number of instructions committed
-system.cpu0.committedOps 87972361 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 77485845 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5272 # Number of float alu accesses
-system.cpu0.num_func_calls 8692455 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 9458284 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 77485845 # number of integer instructions
-system.cpu0.num_fp_insts 5272 # number of float instructions
-system.cpu0.num_int_register_reads 144065543 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 54441741 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 4114 # number of times the floating registers were read
+system.cpu0.committedInsts 72626333 # Number of instructions committed
+system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses
+system.cpu0.num_func_calls 8692525 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 77485858 # number of integer instructions
+system.cpu0.num_fp_insts 5256 # number of float instructions
+system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 268855206 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 31825195 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27911692 # number of memory refs
-system.cpu0.num_load_insts 16162187 # Number of load instructions
-system.cpu0.num_store_insts 11749505 # Number of store instructions
-system.cpu0.num_idle_cycles 5353607103.050808 # Number of idle cycles
-system.cpu0.num_busy_cycles 182837691.949192 # Number of busy cycles
+system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written
+system.cpu0.num_mem_refs 27911721 # number of memory refs
+system.cpu0.num_load_insts 16162181 # Number of load instructions
+system.cpu0.num_store_insts 11749540 # Number of store instructions
+system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles
+system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles
system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles
-system.cpu0.Branches 18597060 # Number of branches fetched
+system.cpu0.Branches 18597106 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 61764761 68.82% 68.83% # Class of executed instruction
-system.cpu0.op_class::IntMult 59661 0.07% 68.89% # Class of executed instruction
+system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction
@@ -274,25 +274,25 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Cl
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 4406 0.00% 68.90% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction
-system.cpu0.op_class::MemRead 16162187 18.01% 86.91% # Class of executed instruction
-system.cpu0.op_class::MemWrite 11749505 13.09% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 89742709 # Class of executed instruction
+system.cpu0.op_class::total 89742700 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 819403 # number of replacements
+system.cpu0.dcache.tags.replacements 819402 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 53784478 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 65.597627 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821680 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175494 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
@@ -301,86 +301,86 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 219237567 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 219237567 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 15302739 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 14826353 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 30129092 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 10898468 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 11441639 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186053 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209002 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 395055 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235062 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222268 # number of LoadLockedReq hits
+system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses
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system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits
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system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
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+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses
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system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
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system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
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+system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012480 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014127 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226204 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227880 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227092 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019447 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013638 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses
@@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 682284 # number of writebacks
-system.cpu0.dcache.writebacks::total 682284 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 682283 # number of writebacks
+system.cpu0.dcache.writebacks::total 682283 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1699220 # number of replacements
+system.cpu0.icache.tags.replacements 1699214 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127365 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536315 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110422 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
@@ -413,43 +413,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77
system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 148742437 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 148742437 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 73936562 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 71406399 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 73936562 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 71406399 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 145342961 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 73936562 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 71406399 # number of overall hits
-system.cpu0.icache.overall_hits::total 145342961 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 844577 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 855161 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 844577 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 855161 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1699738 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 844577 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 855161 # number of overall misses
-system.cpu0.icache.overall_misses::total 1699738 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 74781139 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261560 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 74781139 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 72261560 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 74781139 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 72261560 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
+system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits
+system.cpu0.icache.overall_hits::total 145342721 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses
+system.cpu0.icache.overall_misses::total 1699732 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011834 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011834 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011834 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
@@ -509,25 +509,25 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060
system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 15530019 # DTB read hits
-system.cpu1.dtb.read_misses 5412 # DTB read misses
-system.cpu1.dtb.write_hits 11838449 # DTB write hits
-system.cpu1.dtb.write_misses 791 # DTB write misses
+system.cpu1.dtb.read_hits 15529940 # DTB read hits
+system.cpu1.dtb.read_misses 5414 # DTB read misses
+system.cpu1.dtb.write_hits 11838406 # DTB write hits
+system.cpu1.dtb.write_misses 789 # DTB write misses
system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 15535431 # DTB read accesses
-system.cpu1.dtb.write_accesses 11839240 # DTB write accesses
+system.cpu1.dtb.read_accesses 15535354 # DTB read accesses
+system.cpu1.dtb.write_accesses 11839195 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 27368468 # DTB hits
+system.cpu1.dtb.hits 27368346 # DTB hits
system.cpu1.dtb.misses 6203 # DTB misses
-system.cpu1.dtb.accesses 27374671 # DTB accesses
+system.cpu1.dtb.accesses 27374549 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -557,26 +557,26 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 3040 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 3041 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 72259450 # ITB inst hits
-system.cpu1.itb.inst_misses 3040 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 72259358 # ITB inst hits
+system.cpu1.itb.inst_misses 3041 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
@@ -585,45 +585,45 @@ system.cpu1.itb.flush_tlb 2817 # Nu
system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 72262490 # ITB inst accesses
-system.cpu1.itb.hits 72259450 # DTB hits
-system.cpu1.itb.misses 3040 # DTB misses
-system.cpu1.itb.accesses 72262490 # DTB accesses
-system.cpu1.numCycles 88040872 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses
+system.cpu1.itb.hits 72259358 # DTB hits
+system.cpu1.itb.misses 3041 # DTB misses
+system.cpu1.itb.accesses 72262399 # DTB accesses
+system.cpu1.numCycles 88040649 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 70146598 # Number of instructions committed
-system.cpu1.committedOps 85830973 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 75676981 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 6212 # Number of float alu accesses
-system.cpu1.num_func_calls 8181424 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 9272106 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 75676981 # number of integer instructions
-system.cpu1.num_fp_insts 6212 # number of float instructions
-system.cpu1.num_int_register_reads 140994581 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 52737823 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 4658 # number of times the floating registers were read
+system.cpu1.committedInsts 70146546 # Number of instructions committed
+system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses
+system.cpu1.num_func_calls 8181374 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 75676825 # number of integer instructions
+system.cpu1.num_fp_insts 6228 # number of float instructions
+system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 261999475 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 30539263 # number of times the CC registers were written
-system.cpu1.num_mem_refs 28027673 # number of memory refs
-system.cpu1.num_load_insts 15693775 # Number of load instructions
-system.cpu1.num_store_insts 12333898 # Number of store instructions
-system.cpu1.num_idle_cycles 85385179.520823 # Number of idle cycles
-system.cpu1.num_busy_cycles 2655692.479177 # Number of busy cycles
+system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written
+system.cpu1.num_mem_refs 28027555 # number of memory refs
+system.cpu1.num_load_insts 15693703 # Number of load instructions
+system.cpu1.num_store_insts 12333852 # Number of store instructions
+system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles
+system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles
system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles
-system.cpu1.Branches 17799968 # Number of branches fetched
+system.cpu1.Branches 17799875 # Number of branches fetched
system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 59388214 67.89% 67.89% # Class of executed instruction
-system.cpu1.op_class::IntMult 57231 0.07% 67.96% # Class of executed instruction
+system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction
+system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction
@@ -647,23 +647,23 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Cl
system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 4163 0.00% 67.96% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction
-system.cpu1.op_class::MemRead 15693775 17.94% 85.90% # Class of executed instruction
-system.cpu1.op_class::MemWrite 12333898 14.10% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction
+system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 87477429 # Class of executed instruction
+system.cpu1.op_class::total 87477212 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
-system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
+system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
@@ -684,11 +684,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
@@ -709,17 +709,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
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@@ -941,14 +941,14 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.l2c.writebacks::writebacks 101892 # number of writebacks
-system.l2c.writebacks::total 101892 # number of writebacks
+system.l2c.writebacks::writebacks 101891 # number of writebacks
+system.l2c.writebacks::total 101891 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 74229 # Transaction distribution
-system.membus.trans_dist::ReadResp 74229 # Transaction distribution
-system.membus.trans_dist::WriteReq 27560 # Transaction distribution
-system.membus.trans_dist::WriteResp 27560 # Transaction distribution
-system.membus.trans_dist::Writeback 138082 # Transaction distribution
+system.membus.trans_dist::ReadReq 74221 # Transaction distribution
+system.membus.trans_dist::ReadResp 74221 # Transaction distribution
+system.membus.trans_dist::WriteReq 27546 # Transaction distribution
+system.membus.trans_dist::WriteResp 27546 # Transaction distribution
+system.membus.trans_dist::Writeback 138081 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
@@ -956,34 +956,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 606178 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498773 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 606133 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 715296 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 715251 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18258691 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095548 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18258521 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22908547 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 359035 # Request fanout histogram
+system.membus.snoop_fanout::samples 359033 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 359035 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 359035 # Request fanout histogram
+system.membus.snoop_fanout::total 359033 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
@@ -1015,41 +1015,39 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 2291995 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2291995 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 682284 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2291984 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 682283 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417520 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444926 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20800 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41508 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5924754 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324555 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83016 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 205268491 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417508 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444881 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5924703 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324385 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36631 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3272329 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.011143 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 3235865 98.89% 98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3272329 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
index 83b8a4ab7..b412f009d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt
@@ -1,77 +1,77 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 47.177080 # Number of seconds simulated
-sim_ticks 47177080006500 # Number of ticks simulated
-final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.216814 # Number of seconds simulated
+sim_ticks 47216814145000 # Number of ticks simulated
+final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1049876 # Simulator instruction rate (inst/s)
-host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50706899360 # Simulator tick rate (ticks/s)
-host_mem_usage 670076 # Number of bytes of host memory used
-host_seconds 930.39 # Real time elapsed on the host
-sim_insts 976792036 # Number of instructions simulated
-sim_ops 1149086878 # Number of ops (including micro ops) simulated
+host_inst_rate 1225013 # Simulator instruction rate (inst/s)
+host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59296512316 # Simulator tick rate (ticks/s)
+host_mem_usage 723320 # Number of bytes of host memory used
+host_seconds 796.28 # Real time elapsed on the host
+sim_insts 975457230 # Number of instructions simulated
+sim_ops 1147538415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
@@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 123914 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 125229 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 91355479 # DTB read hits
-system.cpu0.dtb.read_misses 87819 # DTB read misses
-system.cpu0.dtb.write_hits 84601943 # DTB write hits
-system.cpu0.dtb.write_misses 36095 # DTB write misses
+system.cpu0.dtb.read_hits 92662773 # DTB read hits
+system.cpu0.dtb.read_misses 88786 # DTB read misses
+system.cpu0.dtb.write_hits 85694958 # DTB write hits
+system.cpu0.dtb.write_misses 36443 # DTB write misses
system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 91443298 # DTB read accesses
-system.cpu0.dtb.write_accesses 84638038 # DTB write accesses
+system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 92751559 # DTB read accesses
+system.cpu0.dtb.write_accesses 85731401 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 175957422 # DTB hits
-system.cpu0.dtb.misses 123914 # DTB misses
-system.cpu0.dtb.accesses 176081336 # DTB accesses
+system.cpu0.dtb.hits 178357731 # DTB hits
+system.cpu0.dtb.misses 125229 # DTB misses
+system.cpu0.dtb.accesses 178482960 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -202,187 +202,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 60226 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 61377 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 491372488 # ITB inst hits
-system.cpu0.itb.inst_misses 60226 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 497696393 # ITB inst hits
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses
-system.cpu0.itb.hits 491372488 # DTB hits
-system.cpu0.itb.misses 60226 # DTB misses
-system.cpu0.itb.accesses 491432714 # DTB accesses
-system.cpu0.numCycles 94354173207 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses
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+system.cpu0.itb.misses 61377 # DTB misses
+system.cpu0.itb.accesses 497757770 # DTB accesses
+system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 491139120 # Number of instructions committed
-system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses
-system.cpu0.num_func_calls 28573576 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 529301791 # number of integer instructions
-system.cpu0.num_fp_insts 523058 # number of float instructions
-system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written
-system.cpu0.num_mem_refs 176058068 # number of memory refs
-system.cpu0.num_load_insts 91428761 # Number of load instructions
-system.cpu0.num_store_insts 84629307 # Number of store instructions
-system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles
-system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles
-system.cpu0.Branches 109891880 # Number of branches fetched
+system.cpu0.committedInsts 497466384 # Number of instructions committed
+system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
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+system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses
+system.cpu0.num_func_calls 28869117 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 536103359 # number of integer instructions
+system.cpu0.num_fp_insts 526132 # number of float instructions
+system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written
+system.cpu0.num_mem_refs 178459396 # number of memory refs
+system.cpu0.num_load_insts 92737001 # Number of load instructions
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+system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
+system.cpu0.Branches 111287587 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction
-system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
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-system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
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-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction
-system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 577906497 # Class of executed instruction
+system.cpu0.op_class::total 585300003 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 6189405 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 6272759 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
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+system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits
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-system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses
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-system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -391,50 +391,50 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks
-system.cpu0.dcache.writebacks::total 4407988 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks
+system.cpu0.dcache.writebacks::total 4469723 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 5467768 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 5539081 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
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system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses
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-system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses
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+system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -450,132 +450,132 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 #
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements 2648971 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.replacements 2710840 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy
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system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
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system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -584,47 +584,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -654,45 +652,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 144852 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 144041 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 91720002 # DTB read hits
-system.cpu1.dtb.read_misses 112244 # DTB read misses
-system.cpu1.dtb.write_hits 82499013 # DTB write hits
-system.cpu1.dtb.write_misses 32608 # DTB write misses
+system.cpu1.dtb.read_hits 90153061 # DTB read hits
+system.cpu1.dtb.read_misses 111753 # DTB read misses
+system.cpu1.dtb.write_hits 81132787 # DTB write hits
+system.cpu1.dtb.write_misses 32288 # DTB write misses
system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 91832246 # DTB read accesses
-system.cpu1.dtb.write_accesses 82531621 # DTB write accesses
+system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 90264814 # DTB read accesses
+system.cpu1.dtb.write_accesses 81165075 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 174219015 # DTB hits
-system.cpu1.dtb.misses 144852 # DTB misses
-system.cpu1.dtb.accesses 174363867 # DTB accesses
+system.cpu1.dtb.hits 171285848 # DTB hits
+system.cpu1.dtb.misses 144041 # DTB misses
+system.cpu1.dtb.accesses 171429889 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -722,186 +720,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 61939 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 60885 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 485906850 # ITB inst hits
-system.cpu1.itb.inst_misses 61939 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 478248118 # ITB inst hits
+system.cpu1.itb.inst_misses 60885 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses
-system.cpu1.itb.hits 485906850 # DTB hits
-system.cpu1.itb.misses 61939 # DTB misses
-system.cpu1.itb.accesses 485968789 # DTB accesses
-system.cpu1.numCycles 94354166192 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses
+system.cpu1.itb.hits 478248118 # DTB hits
+system.cpu1.itb.misses 60885 # DTB misses
+system.cpu1.itb.accesses 478309003 # DTB accesses
+system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 485652916 # Number of instructions committed
-system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses
-system.cpu1.num_func_calls 28666071 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 524558211 # number of integer instructions
-system.cpu1.num_fp_insts 375128 # number of float instructions
-system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written
-system.cpu1.num_mem_refs 174340371 # number of memory refs
-system.cpu1.num_load_insts 91819242 # Number of load instructions
-system.cpu1.num_store_insts 82521129 # Number of store instructions
-system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles
-system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles
-system.cpu1.Branches 108195111 # Number of branches fetched
+system.cpu1.committedInsts 477990846 # Number of instructions committed
+system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses
+system.cpu1.num_func_calls 28237407 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 516282159 # number of integer instructions
+system.cpu1.num_fp_insts 374678 # number of float instructions
+system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written
+system.cpu1.num_mem_refs 171406825 # number of memory refs
+system.cpu1.num_load_insts 90251973 # Number of load instructions
+system.cpu1.num_store_insts 81154852 # Number of store instructions
+system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
+system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
+system.cpu1.Branches 106497601 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction
-system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction
-system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction
-system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction
-system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction
+system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction
+system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu1.dcache.tags.replacements 6025220 # number of replacements
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system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -910,49 +909,49 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 4091318 # number of writebacks
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses
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+system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses
-system.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses
-system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses
+system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses
+system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1103,53 +1101,51 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks
-system.cpu1.l2cache.writebacks::total 1212706 # number of writebacks
+system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks
+system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136741 # Transaction distribution
-system.iobus.trans_dist::WriteResp 30013 # Transaction distribution
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29906 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
@@ -1164,13 +1160,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -1185,54 +1181,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115586 # number of replacements
-system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use
+system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115585 # number of replacements
+system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040802 # Number of tag accesses
-system.iocache.tags.data_accesses 1040802 # Number of data accesses
+system.iocache.tags.tag_accesses 1040793 # Number of tag accesses
+system.iocache.tags.data_accesses 1040793 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8877 # number of overall misses
-system.iocache.overall_misses::total 8917 # number of overall misses
+system.iocache.overall_misses::realview.ide 8876 # number of overall misses
+system.iocache.overall_misses::total 8916 # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -1257,205 +1253,205 @@ system.iocache.cache_copies 0 # nu
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1764050 # number of replacements
-system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use
-system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks.
+system.l2c.tags.replacements 1759966 # number of replacements
+system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use
+system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor
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+system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses
+system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses
+system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 561677 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 3483 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses
+system.l2c.overall_misses::cpu0.data 561677 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses
+system.l2c.overall_misses::cpu1.data 608055 # number of overall misses
+system.l2c.overall_misses::total 1280735 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1464,49 +1460,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 1467678 # number of writebacks
-system.l2c.writebacks::total 1467678 # number of writebacks
+system.l2c.writebacks::writebacks 1464604 # number of writebacks
+system.l2c.writebacks::total 1464604 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 577534 # Transaction distribution
-system.membus.trans_dist::ReadResp 577534 # Transaction distribution
-system.membus.trans_dist::WriteReq 38903 # Transaction distribution
-system.membus.trans_dist::WriteResp 38903 # Transaction distribution
-system.membus.trans_dist::Writeback 1574372 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution
-system.membus.trans_dist::ReadExReq 961374 # Transaction distribution
-system.membus.trans_dist::ReadExResp 780321 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 575939 # Transaction distribution
+system.membus.trans_dist::ReadResp 575939 # Transaction distribution
+system.membus.trans_dist::WriteReq 38831 # Transaction distribution
+system.membus.trans_dist::WriteResp 38831 # Transaction distribution
+system.membus.trans_dist::Writeback 1571298 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution
+system.membus.trans_dist::ReadExReq 965776 # Transaction distribution
+system.membus.trans_dist::ReadExResp 778482 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 4407750 # Request fanout histogram
+system.membus.snoop_fanout::samples 4414869 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4407750 # Request fanout histogram
+system.membus.snoop_fanout::total 4414869 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
@@ -1549,35 +1545,35 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 117315 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 117306 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
index 70b8700c6..b381100ef 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt
@@ -1,56 +1,56 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.111151 # Number of seconds simulated
-sim_ticks 51111150553500 # Number of ticks simulated
-final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1336104 # Simulator instruction rate (inst/s)
-host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 69344550867 # Simulator tick rate (ticks/s)
-host_mem_usage 712616 # Number of bytes of host memory used
-host_seconds 737.06 # Real time elapsed on the host
-sim_insts 984789519 # Number of instructions simulated
-sim_ops 1157289961 # Number of ops (including micro ops) simulated
+host_inst_rate 1276359 # Simulator instruction rate (inst/s)
+host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
+host_mem_usage 712024 # Number of bytes of host memory used
+host_seconds 771.39 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
@@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 265618 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walks 265715 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 184057973 # DTB read hits
-system.cpu.dtb.read_misses 194269 # DTB read misses
-system.cpu.dtb.write_hits 168276300 # DTB write hits
-system.cpu.dtb.write_misses 71349 # DTB write misses
+system.cpu.dtb.read_hits 184014035 # DTB read hits
+system.cpu.dtb.read_misses 194198 # DTB read misses
+system.cpu.dtb.write_hits 168232768 # DTB write hits
+system.cpu.dtb.write_misses 71517 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 184252242 # DTB read accesses
-system.cpu.dtb.write_accesses 168347649 # DTB write accesses
+system.cpu.dtb.read_accesses 184208233 # DTB read accesses
+system.cpu.dtb.write_accesses 168304285 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 352334273 # DTB hits
-system.cpu.dtb.misses 265618 # DTB misses
-system.cpu.dtb.accesses 352599891 # DTB accesses
+system.cpu.dtb.hits 352246803 # DTB hits
+system.cpu.dtb.misses 265715 # DTB misses
+system.cpu.dtb.accesses 352512518 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 126829 # Table walker walks requested
-system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walks 126837 # Table walker walks requested
+system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 985266544 # ITB inst hits
-system.cpu.itb.inst_misses 126829 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 985047321 # ITB inst hits
+system.cpu.itb.inst_misses 126837 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -199,46 +199,46 @@ system.cpu.itb.flush_tlb 11 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 985393373 # ITB inst accesses
-system.cpu.itb.hits 985266544 # DTB hits
-system.cpu.itb.misses 126829 # DTB misses
-system.cpu.itb.accesses 985393373 # DTB accesses
-system.cpu.numCycles 102222317883 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 985174158 # ITB inst accesses
+system.cpu.itb.hits 985047321 # DTB hits
+system.cpu.itb.misses 126837 # DTB misses
+system.cpu.itb.accesses 985174158 # DTB accesses
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 984789519 # Number of instructions committed
-system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses
-system.cpu.num_func_calls 57075493 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1060698532 # number of integer instructions
-system.cpu.num_fp_insts 880773 # number of float instructions
-system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read
-system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written
+system.cpu.committedInsts 984570519 # Number of instructions committed
+system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses
+system.cpu.num_func_calls 57056367 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1060455466 # number of integer instructions
+system.cpu.num_fp_insts 880805 # number of float instructions
+system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read
+system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written
system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written
-system.cpu.num_mem_refs 352552781 # number of memory refs
-system.cpu.num_load_insts 184224242 # Number of load instructions
-system.cpu.num_store_insts 168328539 # Number of store instructions
-system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles
-system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles
-system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.988672 # Percentage of idle cycles
-system.cpu.Branches 220135160 # Number of branches fetched
+system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written
+system.cpu.num_mem_refs 352465606 # number of memory refs
+system.cpu.num_load_insts 184180431 # Number of load instructions
+system.cpu.num_store_insts 168285175 # Number of store instructions
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
+system.cpu.Branches 220088562 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction
-system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction
-system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction
+system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction
+system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction
+system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
@@ -265,93 +265,93 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction
-system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1157924802 # Class of executed instruction
+system.cpu.op_class::total 1157666593 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 11615783 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks.
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system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
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system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -412,130 +412,129 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -544,53 +543,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 116335 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 40296 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40296 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
@@ -605,13 +602,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -626,54 +623,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115460 # number of replacements
+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115463 # number of replacements
system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
-system.iocache.tags.data_accesses 1039659 # Number of data accesses
+system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
+system.iocache.tags.data_accesses 1039686 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8814 # number of overall misses
-system.iocache.overall_misses::total 8854 # number of overall misses
+system.iocache.overall_misses::realview.ide 8817 # number of overall misses
+system.iocache.overall_misses::total 8857 # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -698,46 +695,46 @@ system.iocache.cache_copies 0 # nu
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 526448 # Transaction distribution
-system.membus.trans_dist::ReadResp 526448 # Transaction distribution
-system.membus.trans_dist::WriteReq 33712 # Transaction distribution
-system.membus.trans_dist::WriteResp 33712 # Transaction distribution
-system.membus.trans_dist::Writeback 1613712 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution
+system.membus.trans_dist::ReadReq 526062 # Transaction distribution
+system.membus.trans_dist::ReadResp 526062 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610046 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution
-system.membus.trans_dist::ReadExReq 833043 # Transaction distribution
-system.membus.trans_dist::ReadExResp 833043 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825948 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825948 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3591670 # Request fanout histogram
+system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3591670 # Request fanout histogram
+system.membus.snoop_fanout::total 3583537 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
index cd0cb8f17..fb0fbc4a7 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt
@@ -1,168 +1,168 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 47.410782 # Number of seconds simulated
-sim_ticks 47410781652000 # Number of ticks simulated
-final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.367818 # Number of seconds simulated
+sim_ticks 47367817574000 # Number of ticks simulated
+final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 787433 # Simulator instruction rate (inst/s)
-host_op_rate 926573 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41969003911 # Simulator tick rate (ticks/s)
-host_mem_usage 699232 # Number of bytes of host memory used
-host_seconds 1129.66 # Real time elapsed on the host
-sim_insts 889532971 # Number of instructions simulated
-sim_ops 1046714541 # Number of ops (including micro ops) simulated
+host_inst_rate 678056 # Simulator instruction rate (inst/s)
+host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
+host_mem_usage 751768 # Number of bytes of host memory used
+host_seconds 1245.10 # Real time elapsed on the host
+sim_insts 844246943 # Number of instructions simulated
+sim_ops 993804803 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory
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system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
-system.physmem.totGap 47410778671000 # Total gap between requests
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+system.physmem.totGap 47367814519500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 878653 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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@@ -188,181 +188,170 @@ system.physmem.wrQLenPdf::11 1 # Wh
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-system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads
-system.physmem.totQLat 32913462781 # Total ticks spent queuing
-system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads
+system.physmem.totQLat 20326500723 # Total ticks spent queuing
+system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing
-system.physmem.readRowHits 687654 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes
-system.physmem.avgGap 17230665.31 # Average gap between requests
-system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.749637 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states
+system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
+system.physmem.readRowHits 509481 # Number of row buffer hits during reads
+system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
+system.physmem.avgGap 20763390.98 # Average gap between requests
+system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.723459 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states
+system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
@@ -393,9 +382,9 @@ system.realview.nvmem.bw_total::total 4 # To
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1673 # Number of DMA write transactions.
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -426,66 +415,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 107972 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 83792624 # DTB read hits
-system.cpu0.dtb.read_misses 78614 # DTB read misses
-system.cpu0.dtb.write_hits 76883618 # DTB write hits
-system.cpu0.dtb.write_misses 29358 # DTB write misses
+system.cpu0.dtb.read_hits 81219280 # DTB read hits
+system.cpu0.dtb.read_misses 71070 # DTB read misses
+system.cpu0.dtb.write_hits 73504932 # DTB write hits
+system.cpu0.dtb.write_misses 24397 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 83871238 # DTB read accesses
-system.cpu0.dtb.write_accesses 76912976 # DTB write accesses
+system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
+system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 160676242 # DTB hits
-system.cpu0.dtb.misses 107972 # DTB misses
-system.cpu0.dtb.accesses 160784214 # DTB accesses
+system.cpu0.dtb.hits 154724212 # DTB hits
+system.cpu0.dtb.misses 95467 # DTB misses
+system.cpu0.dtb.accesses 154819679 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -515,236 +505,239 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 64255 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 56383 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 448595101 # ITB inst hits
-system.cpu0.itb.inst_misses 64255 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 434853798 # ITB inst hits
+system.cpu0.itb.inst_misses 56383 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses
-system.cpu0.itb.hits 448595101 # DTB hits
-system.cpu0.itb.misses 64255 # DTB misses
-system.cpu0.itb.accesses 448659356 # DTB accesses
-system.cpu0.numCycles 94821563304 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
+system.cpu0.itb.hits 434853798 # DTB hits
+system.cpu0.itb.misses 56383 # DTB misses
+system.cpu0.itb.accesses 434910181 # DTB accesses
+system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 448345930 # Number of instructions committed
-system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses
-system.cpu0.num_func_calls 26890258 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 484594714 # number of integer instructions
-system.cpu0.num_fp_insts 558267 # number of float instructions
-system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written
-system.cpu0.num_mem_refs 160668093 # number of memory refs
-system.cpu0.num_load_insts 83788812 # Number of load instructions
-system.cpu0.num_store_insts 76879281 # Number of store instructions
-system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles
-system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles
-system.cpu0.Branches 100174256 # Number of branches fetched
+system.cpu0.committedInsts 434594659 # Number of instructions committed
+system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
+system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 468245604 # number of integer instructions
+system.cpu0.num_fp_insts 368958 # number of float instructions
+system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
+system.cpu0.num_mem_refs 154715442 # number of memory refs
+system.cpu0.num_load_insts 81215665 # Number of load instructions
+system.cpu0.num_store_insts 73499777 # Number of store instructions
+system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
+system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
+system.cpu0.Branches 96525602 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction
-system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction
-system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction
-system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction
-system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
+system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
+system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
+system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
+system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 527943731 # Class of executed instruction
+system.cpu0.op_class::total 510121531 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 5753925 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits
-system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses
-system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency
+system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 5284481 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
+system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -753,92 +746,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -846,58 +839,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -906,241 +899,240 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
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system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1292,58 +1284,56 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
@@ -1374,74 +1364,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 99527 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 83767099 # DTB read hits
-system.cpu1.dtb.read_misses 74857 # DTB read misses
-system.cpu1.dtb.write_hits 75685520 # DTB write hits
-system.cpu1.dtb.write_misses 24670 # DTB write misses
+system.cpu1.dtb.read_hits 78277454 # DTB read hits
+system.cpu1.dtb.read_misses 68245 # DTB read misses
+system.cpu1.dtb.write_hits 71517077 # DTB write hits
+system.cpu1.dtb.write_misses 24264 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 83841956 # DTB read accesses
-system.cpu1.dtb.write_accesses 75710190 # DTB write accesses
+system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
+system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 159452619 # DTB hits
-system.cpu1.dtb.misses 99527 # DTB misses
-system.cpu1.dtb.accesses 159552146 # DTB accesses
+system.cpu1.dtb.hits 149794531 # DTB hits
+system.cpu1.dtb.misses 92509 # DTB misses
+system.cpu1.dtb.accesses 149887040 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1471,239 +1454,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 55326 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 60524 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 441493680 # ITB inst hits
-system.cpu1.itb.inst_misses 55326 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 409921957 # ITB inst hits
+system.cpu1.itb.inst_misses 60524 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses
-system.cpu1.itb.hits 441493680 # DTB hits
-system.cpu1.itb.misses 55326 # DTB misses
-system.cpu1.itb.accesses 441549006 # DTB accesses
-system.cpu1.numCycles 94821563303 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
+system.cpu1.itb.hits 409921957 # DTB hits
+system.cpu1.itb.misses 60524 # DTB misses
+system.cpu1.itb.accesses 409982481 # DTB accesses
+system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 441187041 # Number of instructions committed
-system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses
-system.cpu1.num_func_calls 26570520 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 477531543 # number of integer instructions
-system.cpu1.num_fp_insts 364386 # number of float instructions
-system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written
-system.cpu1.num_mem_refs 159443034 # number of memory refs
-system.cpu1.num_load_insts 83763663 # Number of load instructions
-system.cpu1.num_store_insts 75679371 # Number of store instructions
-system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles
-system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles
-system.cpu1.Branches 98214896 # Number of branches fetched
+system.cpu1.committedInsts 409652284 # Number of instructions committed
+system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
+system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 446181756 # number of integer instructions
+system.cpu1.num_fp_insts 565626 # number of float instructions
+system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
+system.cpu1.num_mem_refs 149782083 # number of memory refs
+system.cpu1.num_load_insts 78271508 # Number of load instructions
+system.cpu1.num_store_insts 71510575 # Number of store instructions
+system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
+system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
+system.cpu1.Branches 91673037 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction
-system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction
-system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction
-system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction
-system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
+system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
+system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
+system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
+system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 519369853 # Class of executed instruction
+system.cpu1.op_class::total 484255317 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements 4977655 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits
-system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses
-system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1712,92 +1698,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 3230902 # number of writebacks
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-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency
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-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -1805,59 +1791,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1866,239 +1852,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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@@ -2107,136 +2090,136 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan
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-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -2246,66 +2229,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40416 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40416 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136984 # Transaction distribution
-system.iobus.trans_dist::WriteResp 30064 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
@@ -2315,18 +2295,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -2336,18 +2316,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -2367,7 +2347,7 @@ system.iobus.reqLayer16.occupancy 12000 # La
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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+system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@@ -3083,58 +3064,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 841910 # Transaction distribution
-system.membus.trans_dist::ReadResp 841910 # Transaction distribution
-system.membus.trans_dist::WriteReq 38471 # Transaction distribution
-system.membus.trans_dist::WriteResp 38471 # Transaction distribution
-system.membus.trans_dist::Writeback 1161772 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138806 # Transaction distribution
-system.membus.trans_dist::ReadExResp 121371 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 622157 # Transaction distribution
+system.membus.trans_dist::ReadResp 622157 # Transaction distribution
+system.membus.trans_dist::WriteReq 38973 # Transaction distribution
+system.membus.trans_dist::WriteResp 38973 # Transaction distribution
+system.membus.trans_dist::Writeback 957695 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
+system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
+system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 613627 # Total snoops (count)
-system.membus.snoop_fanout::samples 3433927 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 581158 # Total snoops (count)
+system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3433927 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2928688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
@@ -3178,45 +3159,45 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1593139 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1518303 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 11eb5dd0c..d577712e0 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -1,138 +1,138 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.821157 # Number of seconds simulated
-sim_ticks 51821157171000 # Number of ticks simulated
-final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.824462 # Number of seconds simulated
+sim_ticks 51824462100500 # Number of ticks simulated
+final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 734878 # Simulator instruction rate (inst/s)
-host_op_rate 863519 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42416153440 # Simulator tick rate (ticks/s)
-host_mem_usage 712380 # Number of bytes of host memory used
-host_seconds 1221.73 # Real time elapsed on the host
-sim_insts 897823750 # Number of instructions simulated
-sim_ops 1054987960 # Number of ops (including micro ops) simulated
+host_inst_rate 723017 # Simulator instruction rate (inst/s)
+host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
+host_mem_usage 712044 # Number of bytes of host memory used
+host_seconds 1235.77 # Real time elapsed on the host
+sim_insts 893481288 # Number of instructions simulated
+sim_ops 1049881338 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory
+system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 959908 # Number of read requests accepted
-system.physmem.writeReqs 1865455 # Number of write requests accepted
-system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue
-system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 56974 # Per bank write bursts
-system.physmem.perBankRdBursts::1 60608 # Per bank write bursts
-system.physmem.perBankRdBursts::2 56247 # Per bank write bursts
-system.physmem.perBankRdBursts::3 58787 # Per bank write bursts
-system.physmem.perBankRdBursts::4 55621 # Per bank write bursts
-system.physmem.perBankRdBursts::5 61105 # Per bank write bursts
-system.physmem.perBankRdBursts::6 53454 # Per bank write bursts
-system.physmem.perBankRdBursts::7 55202 # Per bank write bursts
-system.physmem.perBankRdBursts::8 54549 # Per bank write bursts
-system.physmem.perBankRdBursts::9 101006 # Per bank write bursts
-system.physmem.perBankRdBursts::10 57136 # Per bank write bursts
-system.physmem.perBankRdBursts::11 59250 # Per bank write bursts
-system.physmem.perBankRdBursts::12 54470 # Per bank write bursts
-system.physmem.perBankRdBursts::13 61564 # Per bank write bursts
-system.physmem.perBankRdBursts::14 57688 # Per bank write bursts
-system.physmem.perBankRdBursts::15 55438 # Per bank write bursts
-system.physmem.perBankWrBursts::0 113578 # Per bank write bursts
-system.physmem.perBankWrBursts::1 118177 # Per bank write bursts
-system.physmem.perBankWrBursts::2 119014 # Per bank write bursts
-system.physmem.perBankWrBursts::3 122732 # Per bank write bursts
-system.physmem.perBankWrBursts::4 115108 # Per bank write bursts
-system.physmem.perBankWrBursts::5 118421 # Per bank write bursts
-system.physmem.perBankWrBursts::6 110433 # Per bank write bursts
-system.physmem.perBankWrBursts::7 110649 # Per bank write bursts
-system.physmem.perBankWrBursts::8 111009 # Per bank write bursts
-system.physmem.perBankWrBursts::9 115530 # Per bank write bursts
-system.physmem.perBankWrBursts::10 116272 # Per bank write bursts
-system.physmem.perBankWrBursts::11 116171 # Per bank write bursts
-system.physmem.perBankWrBursts::12 116950 # Per bank write bursts
-system.physmem.perBankWrBursts::13 121923 # Per bank write bursts
-system.physmem.perBankWrBursts::14 117171 # Per bank write bursts
-system.physmem.perBankWrBursts::15 115525 # Per bank write bursts
+system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 923811 # Number of read requests accepted
+system.physmem.writeReqs 1833124 # Number of write requests accepted
+system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue
+system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 57129 # Per bank write bursts
+system.physmem.perBankRdBursts::1 60965 # Per bank write bursts
+system.physmem.perBankRdBursts::2 52485 # Per bank write bursts
+system.physmem.perBankRdBursts::3 50413 # Per bank write bursts
+system.physmem.perBankRdBursts::4 54002 # Per bank write bursts
+system.physmem.perBankRdBursts::5 59718 # Per bank write bursts
+system.physmem.perBankRdBursts::6 51713 # Per bank write bursts
+system.physmem.perBankRdBursts::7 51669 # Per bank write bursts
+system.physmem.perBankRdBursts::8 50247 # Per bank write bursts
+system.physmem.perBankRdBursts::9 101235 # Per bank write bursts
+system.physmem.perBankRdBursts::10 59848 # Per bank write bursts
+system.physmem.perBankRdBursts::11 58323 # Per bank write bursts
+system.physmem.perBankRdBursts::12 55369 # Per bank write bursts
+system.physmem.perBankRdBursts::13 55988 # Per bank write bursts
+system.physmem.perBankRdBursts::14 51743 # Per bank write bursts
+system.physmem.perBankRdBursts::15 52477 # Per bank write bursts
+system.physmem.perBankWrBursts::0 110630 # Per bank write bursts
+system.physmem.perBankWrBursts::1 112240 # Per bank write bursts
+system.physmem.perBankWrBursts::2 108805 # Per bank write bursts
+system.physmem.perBankWrBursts::3 108103 # Per bank write bursts
+system.physmem.perBankWrBursts::4 111102 # Per bank write bursts
+system.physmem.perBankWrBursts::5 113339 # Per bank write bursts
+system.physmem.perBankWrBursts::6 105567 # Per bank write bursts
+system.physmem.perBankWrBursts::7 107723 # Per bank write bursts
+system.physmem.perBankWrBursts::8 108849 # Per bank write bursts
+system.physmem.perBankWrBursts::9 115780 # Per bank write bursts
+system.physmem.perBankWrBursts::10 115663 # Per bank write bursts
+system.physmem.perBankWrBursts::11 113049 # Per bank write bursts
+system.physmem.perBankWrBursts::12 112494 # Per bank write bursts
+system.physmem.perBankWrBursts::13 116984 # Per bank write bursts
+system.physmem.perBankWrBursts::14 111502 # Per bank write bursts
+system.physmem.perBankWrBursts::15 110389 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
-system.physmem.totGap 51821154615000 # Total gap between requests
+system.physmem.numWrRetry 145 # Number of times write queue was full causing retry
+system.physmem.totGap 51824459475500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43101 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 916792 # Read request sizes (log2)
+system.physmem.readPktSize::6 880695 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1862882 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1830551 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@@ -159,181 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads
-system.physmem.totQLat 12424177254 # Total ticks spent queuing
-system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads
+system.physmem.totQLat 12043609520 # Total ticks spent queuing
+system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing
-system.physmem.readRowHits 722238 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes
-system.physmem.avgGap 18341414.75 # Average gap between requests
-system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.671195 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states
+system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing
+system.physmem.readRowHits 694872 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes
+system.physmem.avgGap 18797853.22 # Average gap between requests
+system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.655841 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.683425 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states
+system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.672178 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
@@ -387,73 +371,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 215397 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walks 211321 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 168647599 # DTB read hits
-system.cpu.dtb.read_misses 158984 # DTB read misses
-system.cpu.dtb.write_hits 153347297 # DTB write hits
-system.cpu.dtb.write_misses 56413 # DTB write misses
+system.cpu.dtb.read_hits 167775531 # DTB read hits
+system.cpu.dtb.read_misses 155743 # DTB read misses
+system.cpu.dtb.write_hits 152648275 # DTB write hits
+system.cpu.dtb.write_misses 55578 # DTB write misses
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 168806583 # DTB read accesses
-system.cpu.dtb.write_accesses 153403710 # DTB write accesses
+system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 167931274 # DTB read accesses
+system.cpu.dtb.write_accesses 152703853 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 321994896 # DTB hits
-system.cpu.dtb.misses 215397 # DTB misses
-system.cpu.dtb.accesses 322210293 # DTB accesses
+system.cpu.dtb.hits 320423806 # DTB hits
+system.cpu.dtb.misses 211321 # DTB misses
+system.cpu.dtb.accesses 320635127 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -483,91 +462,97 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 123370 # Table walker walks requested
-system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated
+system.cpu.itb.walker.walks 122916 # Table walker walks requested
+system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 898375907 # ITB inst hits
-system.cpu.itb.inst_misses 123370 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst
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+system.cpu.itb.inst_misses 122916 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
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-system.cpu.itb.hits 898375907 # DTB hits
-system.cpu.itb.misses 123370 # DTB misses
-system.cpu.itb.accesses 898499277 # DTB accesses
-system.cpu.numCycles 103642314342 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 897823750 # Number of instructions committed
-system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed
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-system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses
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-system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written
-system.cpu.num_mem_refs 321978685 # number of memory refs
-system.cpu.num_load_insts 168640749 # Number of load instructions
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-system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles
-system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.969434 # Percentage of idle cycles
-system.cpu.Branches 200551202 # Number of branches fetched
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+system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses
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+system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written
+system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read
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+system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles
+system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.969376 # Percentage of idle cycles
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system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction
-system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction
-system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction
+system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
@@ -590,126 +575,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
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+system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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+system.cpu.op_class::total 1050473844 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -718,88 +703,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 7913457 # number of writebacks
-system.cpu.dcache.writebacks::total 7913457 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7211 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21165 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 21165 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71123 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 71123 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 28376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 28376 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 28376 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 28376 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5335094 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 5335094 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2217380 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2217380 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308216 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 1308216 # number of SoftPFReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232790 # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232790 # number of WriteInvalidateReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233934 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 233934 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks
+system.cpu.dcache.writebacks::total 7878976 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 7552474 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 7552474 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 8860690 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 8860690 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72364530247 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 72364530247 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58930269477 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 58930269477 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19541293498 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19541293498 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25112944493 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25112944493 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2872283000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2872283000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131294799724 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 131294799724 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150836093222 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 150836093222 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727964499 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727964499 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573385250 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573385250 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301349749 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301349749 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032750 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032750 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015010 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015010 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766338 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766338 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786129 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786129 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058419 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058419 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024314 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.024314 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028369 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028369 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13563.871648 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13563.871648 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26576.531527 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26576.531527 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14937.360113 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14937.360113 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20370.821059 # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20370.821059 # average WriteInvalidateReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12278.176751 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12278.176751 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17384.343160 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17384.343160 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17023.064030 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -807,59 +792,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 13791662 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.892960 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 884583728 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 13792174 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 64.136642 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 31822438250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.892960 # Average occupied blocks per requestor
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@@ -1078,108 +1064,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -1189,62 +1175,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 473368 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40403 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40403 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136733 # Transaction distribution
-system.iobus.trans_dist::WriteResp 30069 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40333 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40333 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29907 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
@@ -1259,13 +1243,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -1280,13 +1264,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -1314,71 +1298,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115482 # number of replacements
-system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use
+system.iocache.tags.replacements 115493 # number of replacements
+system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039866 # Number of tag accesses
-system.iocache.tags.data_accesses 1039866 # Number of data accesses
+system.iocache.tags.tag_accesses 1039965 # Number of tag accesses
+system.iocache.tags.data_accesses 1039965 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8877 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8888 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8837 # number of overall misses
-system.iocache.overall_misses::total 8877 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles
+system.iocache.overall_misses::realview.ide 8848 # number of overall misses
+system.iocache.overall_misses::total 8888 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -1392,55 +1376,55 @@ system.iocache.demand_miss_rate::total 1 # mi
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
@@ -1454,71 +1438,71 @@ system.iocache.demand_mshr_miss_rate::total 1 #
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 463332 # Transaction distribution
-system.membus.trans_dist::ReadResp 463332 # Transaction distribution
-system.membus.trans_dist::WriteReq 33872 # Transaction distribution
-system.membus.trans_dist::WriteResp 33872 # Transaction distribution
-system.membus.trans_dist::Writeback 1244337 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution
+system.membus.trans_dist::ReadReq 448489 # Transaction distribution
+system.membus.trans_dist::ReadResp 448489 # Transaction distribution
+system.membus.trans_dist::WriteReq 33710 # Transaction distribution
+system.membus.trans_dist::WriteResp 33710 # Transaction distribution
+system.membus.trans_dist::Writeback 1214153 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution
-system.membus.trans_dist::ReadExReq 533903 # Transaction distribution
-system.membus.trans_dist::ReadExResp 533903 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution
+system.membus.trans_dist::ReadExReq 512353 # Transaction distribution
+system.membus.trans_dist::ReadExResp 512353 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3539 # Total snoops (count)
-system.membus.snoop_fanout::samples 2819489 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3324 # Total snoops (count)
+system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2819489 # Request fanout histogram
-system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2750930 # Request fanout histogram
+system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
index 5213927ce..f36b7859c 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt
@@ -1,74 +1,74 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.111151 # Number of seconds simulated
-sim_ticks 51111150553500 # Number of ticks simulated
-final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.111153 # Number of seconds simulated
+sim_ticks 51111152682000 # Number of ticks simulated
+final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1151312 # Simulator instruction rate (inst/s)
-host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59753764865 # Simulator tick rate (ticks/s)
-host_mem_usage 728116 # Number of bytes of host memory used
-host_seconds 855.36 # Real time elapsed on the host
-sim_insts 984789519 # Number of instructions simulated
-sim_ops 1157289961 # Number of ops (including micro ops) simulated
+host_inst_rate 1095499 # Simulator instruction rate (inst/s)
+host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
+host_mem_usage 728040 # Number of bytes of host memory used
+host_seconds 898.74 # Real time elapsed on the host
+sim_insts 984570519 # Number of instructions simulated
+sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 200576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 185152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 3380276 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 37995016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 209984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 187968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2175808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 37325312 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 82097788 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 3380276 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2175808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5556084 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 103277696 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory
+system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 103298276 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3134 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2893 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 93224 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 593685 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 3281 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2937 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 33997 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 583208 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1323198 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1613714 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1616287 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3924 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 3623 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 66136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 743380 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 4108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 42570 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 730277 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1606260 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 66136 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 42570 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 108706 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2020649 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2021052 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2020649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3924 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 66136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 743783 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 42570 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 730277 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3627311 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
@@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 144982 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 144734 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 91965302 # DTB read hits
-system.cpu0.dtb.read_misses 107321 # DTB read misses
-system.cpu0.dtb.write_hits 84365950 # DTB write hits
-system.cpu0.dtb.write_misses 37661 # DTB write misses
+system.cpu0.dtb.read_hits 91873100 # DTB read hits
+system.cpu0.dtb.read_misses 107254 # DTB read misses
+system.cpu0.dtb.write_hits 84300346 # DTB write hits
+system.cpu0.dtb.write_misses 37480 # DTB write misses
system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 56687 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4951 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11060 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 92072623 # DTB read accesses
-system.cpu0.dtb.write_accesses 84403611 # DTB write accesses
+system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91980354 # DTB read accesses
+system.cpu0.dtb.write_accesses 84337826 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 176331252 # DTB hits
-system.cpu0.dtb.misses 144982 # DTB misses
-system.cpu0.dtb.accesses 176476234 # DTB accesses
+system.cpu0.dtb.hits 176173446 # DTB hits
+system.cpu0.dtb.misses 144734 # DTB misses
+system.cpu0.dtb.accesses 176318180 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -189,219 +189,219 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 70785 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 70623 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 493804573 # ITB inst hits
-system.cpu0.itb.inst_misses 70785 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 493558289 # ITB inst hits
+system.cpu0.itb.inst_misses 70623 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 40296 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 493875358 # ITB inst accesses
-system.cpu0.itb.hits 493804573 # DTB hits
-system.cpu0.itb.misses 70785 # DTB misses
-system.cpu0.itb.accesses 493875358 # DTB accesses
-system.cpu0.numCycles 98036815347 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses
+system.cpu0.itb.hits 493558289 # DTB hits
+system.cpu0.itb.misses 70623 # DTB misses
+system.cpu0.itb.accesses 493628912 # DTB accesses
+system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 493589418 # Number of instructions committed
-system.cpu0.committedOps 579610206 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 531010156 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 454321 # Number of float alu accesses
-system.cpu0.num_func_calls 28538505 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 76169999 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 531010156 # number of integer instructions
-system.cpu0.num_fp_insts 454321 # number of float instructions
-system.cpu0.num_int_register_reads 784912346 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 421695474 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 742936 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 362460 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 132983142 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 132661017 # number of times the CC registers were written
-system.cpu0.num_mem_refs 176454648 # number of memory refs
-system.cpu0.num_load_insts 92059270 # Number of load instructions
-system.cpu0.num_store_insts 84395378 # Number of store instructions
-system.cpu0.num_idle_cycles 96925999292.039536 # Number of idle cycles
-system.cpu0.num_busy_cycles 1110816054.960464 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011331 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988669 # Percentage of idle cycles
-system.cpu0.Branches 110347037 # Number of branches fetched
+system.cpu0.committedInsts 493343054 # Number of instructions committed
+system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses
+system.cpu0.num_func_calls 28504103 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 530703417 # number of integer instructions
+system.cpu0.num_fp_insts 453665 # number of float instructions
+system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written
+system.cpu0.num_mem_refs 176296730 # number of memory refs
+system.cpu0.num_load_insts 91967123 # Number of load instructions
+system.cpu0.num_store_insts 84329607 # Number of store instructions
+system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
+system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
+system.cpu0.Branches 110281342 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 402205176 69.35% 69.35% # Class of executed instruction
-system.cpu0.op_class::IntMult 1169973 0.20% 69.56% # Class of executed instruction
-system.cpu0.op_class::IntDiv 50634 0.01% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction
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-system.cpu0.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction
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system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
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+system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025423 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025101 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029891 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029609 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -410,63 +410,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 8923646 # number of writebacks
-system.cpu0.dcache.writebacks::total 8923646 # number of writebacks
+system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks
+system.cpu0.dcache.writebacks::total 8921315 # number of writebacks
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 14287218 # number of replacements
+system.cpu0.icache.tags.replacements 14295641 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 971093500 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks.
+system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 267.813987 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 244.170612 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523074 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476896 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 999668970 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 999668970 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 486710504 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 484382996 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 971093500 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 486710504 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 484382996 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 971093500 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 486710504 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 484382996 # number of overall hits
-system.cpu0.icache.overall_hits::total 971093500 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 7158773 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 7128962 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 14287735 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 7158773 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 7128962 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 14287735 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 7158773 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 7128962 # number of overall misses
-system.cpu0.icache.overall_misses::total 14287735 # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 493869277 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 491511958 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 493869277 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 491511958 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::cpu1.inst 491511958 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014495 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014504 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014495 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014504 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014495 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014504 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses
+system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits
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+system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits
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+system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits
+system.cpu0.icache.overall_hits::total 970865862 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses
+system.cpu0.icache.overall_misses::total 14296158 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -505,45 +505,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 143312 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 143589 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 92072581 # DTB read hits
-system.cpu1.dtb.read_misses 106555 # DTB read misses
-system.cpu1.dtb.write_hits 83907281 # DTB write hits
-system.cpu1.dtb.write_misses 36757 # DTB write misses
+system.cpu1.dtb.read_hits 92120843 # DTB read hits
+system.cpu1.dtb.read_misses 106565 # DTB read misses
+system.cpu1.dtb.write_hits 83929435 # DTB write hits
+system.cpu1.dtb.write_misses 37024 # DTB write misses
system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 56101 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4637 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10591 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 92179136 # DTB read accesses
-system.cpu1.dtb.write_accesses 83944038 # DTB write accesses
+system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 92227408 # DTB read accesses
+system.cpu1.dtb.write_accesses 83966459 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 175979862 # DTB hits
-system.cpu1.dtb.misses 143312 # DTB misses
-system.cpu1.dtb.accesses 176123174 # DTB accesses
+system.cpu1.dtb.hits 176050278 # DTB hits
+system.cpu1.dtb.misses 143589 # DTB misses
+system.cpu1.dtb.accesses 176193867 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -573,113 +573,113 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 69790 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 69863 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 491448225 # ITB inst hits
-system.cpu1.itb.inst_misses 69790 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 491475383 # ITB inst hits
+system.cpu1.itb.inst_misses 69863 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 40454 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 491518015 # ITB inst accesses
-system.cpu1.itb.hits 491448225 # DTB hits
-system.cpu1.itb.misses 69790 # DTB misses
-system.cpu1.itb.accesses 491518015 # DTB accesses
-system.cpu1.numCycles 97463256917 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses
+system.cpu1.itb.hits 491475383 # DTB hits
+system.cpu1.itb.misses 69863 # DTB misses
+system.cpu1.itb.accesses 491545246 # DTB accesses
+system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 491200101 # Number of instructions committed
-system.cpu1.committedOps 577679755 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 529688376 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 426452 # Number of float alu accesses
-system.cpu1.num_func_calls 28536988 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 75796446 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 529688376 # number of integer instructions
-system.cpu1.num_fp_insts 426452 # number of float instructions
-system.cpu1.num_int_register_reads 779402047 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 420937852 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 676063 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 385332 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 131460069 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 131204494 # number of times the CC registers were written
-system.cpu1.num_mem_refs 176098133 # number of memory refs
-system.cpu1.num_load_insts 92164972 # Number of load instructions
-system.cpu1.num_store_insts 83933161 # Number of store instructions
-system.cpu1.num_idle_cycles 96357264034.410416 # Number of idle cycles
-system.cpu1.num_busy_cycles 1105992882.589586 # Number of busy cycles
+system.cpu1.committedInsts 491227465 # Number of instructions committed
+system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses
+system.cpu1.num_func_calls 28552264 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 529752049 # number of integer instructions
+system.cpu1.num_fp_insts 427140 # number of float instructions
+system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written
+system.cpu1.num_mem_refs 176168876 # number of memory refs
+system.cpu1.num_load_insts 92213308 # Number of load instructions
+system.cpu1.num_store_insts 83955568 # Number of store instructions
+system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
+system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
-system.cpu1.Branches 109788123 # Number of branches fetched
+system.cpu1.Branches 109807220 # Number of branches fetched
system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 400601727 69.31% 69.31% # Class of executed instruction
-system.cpu1.op_class::IntMult 1185429 0.21% 69.51% # Class of executed instruction
-system.cpu1.op_class::IntDiv 51217 0.01% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 55063 0.01% 69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction
-system.cpu1.op_class::MemRead 92164972 15.95% 85.48% # Class of executed instruction
-system.cpu1.op_class::MemWrite 83933161 14.52% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction
+system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction
+system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 577991612 # Class of executed instruction
+system.cpu1.op_class::total 578022895 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq 40296 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40296 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136621 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29957 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29851 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
@@ -694,13 +694,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
@@ -715,54 +715,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes)
-system.iocache.tags.replacements 115460 # number of replacements
+system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes)
+system.iocache.tags.replacements 115463 # number of replacements
system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039659 # Number of tag accesses
-system.iocache.tags.data_accesses 1039659 # Number of data accesses
+system.iocache.tags.tag_accesses 1039686 # Number of tag accesses
+system.iocache.tags.data_accesses 1039686 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8854 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8857 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8814 # number of overall misses
-system.iocache.overall_misses::total 8854 # number of overall misses
+system.iocache.overall_misses::realview.ide 8817 # number of overall misses
+system.iocache.overall_misses::total 8857 # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
@@ -787,198 +787,197 @@ system.iocache.cache_copies 0 # nu
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1726938 # number of replacements
-system.l2c.tags.tagsinuse 65261.456077 # Cycle average of tags in use
-system.l2c.tags.total_refs 30061688 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1789677 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 16.797270 # Average number of references to valid blocks.
+system.l2c.tags.replacements 1722682 # number of replacements
+system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use
+system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 37843.446470 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.851039 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 182.256334 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3658.181664 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 9398.442867 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.187628 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 187.456005 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2615.769048 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 11103.865022 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.577445 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002042 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.002781 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.055819 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.143409 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002109 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.002860 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.039913 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.169432 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 62493 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 54021 # Occupied blocks per task id
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+system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 282613 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.325924 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.336281 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.019253 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.007002 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.114043 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.019925 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.004771 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.113139 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.049931 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.019253 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.007002 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.114043 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.019925 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.004771 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.113139 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.049931 # miss rate for overall accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -987,49 +986,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 1507083 # number of writebacks
-system.l2c.writebacks::total 1507083 # number of writebacks
+system.l2c.writebacks::writebacks 1503417 # number of writebacks
+system.l2c.writebacks::total 1503417 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 526435 # Transaction distribution
-system.membus.trans_dist::ReadResp 526435 # Transaction distribution
-system.membus.trans_dist::WriteReq 33712 # Transaction distribution
-system.membus.trans_dist::WriteResp 33712 # Transaction distribution
-system.membus.trans_dist::Writeback 1613714 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 654603 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 654603 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 40598 # Transaction distribution
+system.membus.trans_dist::ReadReq 526050 # Transaction distribution
+system.membus.trans_dist::ReadResp 526050 # Transaction distribution
+system.membus.trans_dist::WriteReq 33606 # Transaction distribution
+system.membus.trans_dist::WriteResp 33606 # Transaction distribution
+system.membus.trans_dist::Writeback 1610048 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 40599 # Transaction distribution
-system.membus.trans_dist::ReadExReq 833044 # Transaction distribution
-system.membus.trans_dist::ReadExResp 833044 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
+system.membus.trans_dist::ReadExReq 825949 # Transaction distribution
+system.membus.trans_dist::ReadExResp 825949 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5323323 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5452833 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5790500 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213243872 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 213413240 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 227630584 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3591663 # Request fanout histogram
+system.membus.snoop_fanout::samples 3583531 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3591663 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3591663 # Request fanout histogram
+system.membus.snoop_fanout::total 3583531 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
@@ -1072,43 +1071,41 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 23461417 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 23461417 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 51262 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 51263 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28661720 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32393430 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832700 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655510 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 63543360 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3330800 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6622040 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2239287552 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 116335 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 36238577 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.003188 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.056370 # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 116338 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 36123059 99.68% 99.68% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 36238577 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index b290fab5a..3b1b184c8 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -1,129 +1,125 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.188464 # Number of seconds simulated
-sim_ticks 5188464227000 # Number of ticks simulated
-final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.184750 # Number of seconds simulated
+sim_ticks 5184749789500 # Number of ticks simulated
+final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 671592 # Simulator instruction rate (inst/s)
-host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27056983658 # Simulator tick rate (ticks/s)
-host_mem_usage 641928 # Number of bytes of host memory used
-host_seconds 191.76 # Real time elapsed on the host
-sim_insts 128784844 # Number of instructions simulated
-sim_ops 248241672 # Number of ops (including micro ops) simulated
+host_inst_rate 858252 # Simulator instruction rate (inst/s)
+host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34581252938 # Simulator tick rate (ticks/s)
+host_mem_usage 653812 # Number of bytes of host memory used
+host_seconds 149.93 # Real time elapsed on the host
+sim_insts 128677191 # Number of instructions simulated
+sim_ops 248045844 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory
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system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.totGap 5188464163500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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@@ -156,209 +152,194 @@ system.physmem.wrQLenPdf::11 1 # Wh
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+system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads
-system.physmem.totQLat 1439298500 # Total ticks spent queuing
-system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
+system.physmem.totQLat 1425327951 # Total ticks spent queuing
+system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
-system.physmem.readRowHits 127137 # Number of row buffer hits during reads
-system.physmem.writeRowHits 140055 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes
-system.physmem.avgGap 15800904.98 # Average gap between requests
-system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.773100 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states
+system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing
+system.physmem.readRowHits 126892 # Number of row buffer hits during reads
+system.physmem.writeRowHits 117801 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes
+system.physmem.avgGap 15810345.15 # Average gap between requests
+system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.758961 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states
+system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.787680 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states
+system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.782314 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states
+system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.numCycles 10376928454 # number of cpu cycles simulated
+system.cpu.numCycles 10369499579 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 128784844 # Number of instructions committed
-system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses
+system.cpu.committedInsts 128677191 # Number of instructions committed
+system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu.num_func_calls 2318021 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls
-system.cpu.num_int_insts 232811079 # number of integer instructions
+system.cpu.num_func_calls 2317433 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls
+system.cpu.num_int_insts 232619140 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read
-system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written
+system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read
+system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written
-system.cpu.num_mem_refs 22376754 # number of memory refs
-system.cpu.num_load_insts 13962110 # Number of load instructions
-system.cpu.num_store_insts 8414644 # Number of store instructions
-system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles
-system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles
-system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.942354 # Percentage of idle cycles
-system.cpu.Branches 26395735 # Number of branches fetched
-system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction
-system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction
-system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction
+system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written
+system.cpu.num_mem_refs 22361713 # number of memory refs
+system.cpu.num_load_insts 13951833 # Number of load instructions
+system.cpu.num_store_insts 8409880 # Number of store instructions
+system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles
+system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles
+system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.942121 # Percentage of idle cycles
+system.cpu.Branches 26373024 # Number of branches fetched
+system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction
+system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction
+system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction
+system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction
@@ -385,150 +366,149 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl
system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction
-system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction
+system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 248243229 # Class of executed instruction
+system.cpu.op_class::total 248047391 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.dcache.tags.replacements 1624253 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements 1622522 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -536,58 +516,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -596,86 +576,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -953,90 +919,78 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1044,59 +998,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution
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-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 53190 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 54167 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 230298 # Transaction distribution
-system.iobus.trans_dist::ReadResp 230298 # Transaction distribution
+system.iobus.trans_dist::ReadReq 228399 # Transaction distribution
+system.iobus.trans_dist::ReadResp 228399 # Transaction distribution
system.iobus.trans_dist::WriteReq 57726 # Transaction distribution
system.iobus.trans_dist::WriteResp 11006 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1653 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1653 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1652 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1652 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
@@ -1105,7 +1059,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
@@ -1115,12 +1069,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
@@ -1129,7 +1083,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
@@ -1139,13 +1093,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks)
+system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
@@ -1163,7 +1117,7 @@ system.iobus.reqLayer7.occupancy 50000 # La
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
@@ -1181,54 +1135,54 @@ system.iobus.reqLayer17.occupancy 9000 # La
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks)
+system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks)
+system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks)
+system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47511 # number of replacements
-system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use
+system.iocache.tags.replacements 47502 # number of replacements
+system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428094 # Number of tag accesses
-system.iocache.tags.data_accesses 428094 # Number of data accesses
-system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 846 # number of ReadReq misses
+system.iocache.tags.tag_accesses 428013 # Number of tag accesses
+system.iocache.tags.data_accesses 428013 # Number of data accesses
+system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 837 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses
-system.iocache.demand_misses::total 846 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses
-system.iocache.overall_misses::total 846 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses
+system.iocache.demand_misses::total 837 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses
+system.iocache.overall_misses::total 837 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
@@ -1237,40 +1191,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
@@ -1279,71 +1233,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 624018 # Transaction distribution
-system.membus.trans_dist::ReadResp 624018 # Transaction distribution
-system.membus.trans_dist::WriteReq 13918 # Transaction distribution
-system.membus.trans_dist::WriteResp 13918 # Transaction distribution
-system.membus.trans_dist::Writeback 126962 # Transaction distribution
+system.membus.trans_dist::ReadReq 617109 # Transaction distribution
+system.membus.trans_dist::ReadResp 617109 # Transaction distribution
+system.membus.trans_dist::WriteReq 13916 # Transaction distribution
+system.membus.trans_dist::WriteResp 13916 # Transaction distribution
+system.membus.trans_dist::Writeback 126970 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution
-system.membus.trans_dist::ReadExReq 113313 # Transaction distribution
-system.membus.trans_dist::ReadExResp 113313 # Transaction distribution
-system.membus.trans_dist::MessageReq 1653 # Transaction distribution
-system.membus.trans_dist::MessageResp 1653 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution
+system.membus.trans_dist::ReadExReq 112993 # Transaction distribution
+system.membus.trans_dist::ReadExResp 112993 # Transaction distribution
+system.membus.trans_dist::MessageReq 1652 # Transaction distribution
+system.membus.trans_dist::MessageResp 1652 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1602 # Total snoops (count)
-system.membus.snoop_fanout::samples 331576 # Request fanout histogram
+system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1583 # Total snoops (count)
+system.membus.snoop_fanout::samples 331203 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 331576 # Request fanout histogram
-system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 331203 # Request fanout histogram
+system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).