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authorAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-01-07 13:05:54 -0500
commit9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch)
treefab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/quick/fs/10.linux-boot
parent009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff)
downloadgem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz
stats: update stats for previous changes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini239
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout8
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt136
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini239
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt1866
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini245
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt964
12 files changed, 1886 insertions, 1834 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index c876dab9d..9cf4fe14a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -82,6 +82,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -92,6 +93,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
@@ -104,23 +106,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -134,7 +131,7 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@@ -144,23 +141,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -169,6 +161,23 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=ArmInterrupts
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu0.itb]
type=ArmTLB
children=walker
@@ -177,7 +186,7 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@@ -187,11 +196,10 @@ type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -200,6 +208,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -210,6 +219,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
@@ -222,23 +232,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -252,7 +257,7 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
@@ -262,23 +267,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -287,6 +287,23 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu1.interrupts]
type=ArmInterrupts
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu1.itb]
type=ArmTLB
children=walker
@@ -295,7 +312,7 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
@@ -319,57 +336,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@@ -381,11 +388,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -401,15 +408,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
@@ -424,7 +444,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@@ -433,7 +453,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@@ -480,7 +500,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@@ -498,11 +518,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@@ -511,7 +532,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@@ -520,7 +541,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@@ -537,7 +558,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@@ -551,7 +572,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@@ -561,7 +582,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@@ -571,7 +592,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@@ -581,7 +602,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@@ -595,7 +616,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@@ -608,7 +629,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@@ -637,7 +658,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@@ -647,7 +668,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@@ -659,7 +680,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@@ -671,7 +692,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@@ -684,7 +705,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@@ -694,7 +715,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@@ -704,7 +725,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@@ -714,7 +735,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@@ -724,7 +745,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -738,7 +759,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -751,7 +772,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@@ -766,7 +787,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@@ -776,7 +797,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@@ -786,7 +807,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@@ -796,7 +817,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@@ -813,7 +834,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
index 04178bb32..e8e271d58 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
@@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 0ce4b8c1f..4bb186944 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:29:32
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 3841577ac..362d16758 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,22 +4,40 @@ sim_seconds 0.912097 # Nu
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1752000 # Simulator instruction rate (inst/s)
-host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25930494646 # Simulator tick rate (ticks/s)
-host_mem_usage 382232 # Number of bytes of host memory used
-host_seconds 35.17 # Real time elapsed on the host
+host_inst_rate 599236 # Simulator instruction rate (inst/s)
+host_op_rate 771515 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8869004975 # Simulator tick rate (ticks/s)
+host_mem_usage 384344 # Number of bytes of host memory used
+host_seconds 102.84 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory
-system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory
+system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
@@ -31,11 +49,11 @@ system.physmem.num_reads::realview.clcd 4915200 # Nu
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory
@@ -44,11 +62,11 @@ system.physmem.bw_read::realview.clcd 43111215 # To
system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s)
@@ -61,11 +79,11 @@ system.physmem.bw_total::realview.clcd 43111215 # To
system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
@@ -224,47 +242,29 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 70662 # number of replacements
-system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use
-system.l2c.total_refs 1623342 # Total number of references to valid blocks.
-system.l2c.sampled_refs 135814 # Sample count of references to valid blocks.
-system.l2c.avg_refs 11.952685 # Average number of references to valid blocks.
+system.l2c.replacements 70658 # number of replacements
+system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
+system.l2c.total_refs 1623339 # Total number of references to valid blocks.
+system.l2c.sampled_refs 135810 # Sample count of references to valid blocks.
+system.l2c.avg_refs 11.953015 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy
+system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits
@@ -282,27 +282,27 @@ system.l2c.UpgradeReq_hits::total 1274 # nu
system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1317469 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits
system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits
-system.l2c.overall_hits::cpu0.data 233339 # number of overall hits
+system.l2c.overall_hits::cpu0.data 233336 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits
system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits
system.l2c.overall_hits::cpu1.data 219723 # number of overall hits
-system.l2c.overall_hits::total 1317469 # number of overall hits
+system.l2c.overall_hits::total 1317466 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses
@@ -317,25 +317,25 @@ system.l2c.UpgradeReq_misses::total 9236 # nu
system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses
-system.l2c.demand_misses::total 163287 # number of demand (read+write) misses
+system.l2c.demand_misses::total 163290 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses
-system.l2c.overall_misses::cpu0.data 98853 # number of overall misses
+system.l2c.overall_misses::cpu0.data 98856 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses
system.l2c.overall_misses::cpu1.data 53648 # number of overall misses
-system.l2c.overall_misses::total 163287 # number of overall misses
+system.l2c.overall_misses::total 163290 # number of overall misses
system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses)
@@ -388,25 +388,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.878782 # mi
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -490,15 +490,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe
system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed
-system.cpu0.icache.replacements 428547 # number of replacements
-system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use
+system.cpu0.icache.replacements 428546 # number of replacements
+system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use
system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks.
+system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index edcbc8719..8e8c112af 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -81,6 +81,7 @@ dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -89,6 +90,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=
@@ -100,23 +102,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -130,7 +127,7 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[3]
@@ -140,23 +137,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -165,6 +157,23 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=ArmInterrupts
+[system.cpu0.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu0.itb]
type=ArmTLB
children=walker
@@ -173,7 +182,7 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[2]
@@ -183,11 +192,10 @@ type=ExeTracer
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -195,6 +203,7 @@ dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -203,6 +212,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=
@@ -214,23 +224,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -244,7 +249,7 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[7]
@@ -254,23 +259,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -279,6 +279,23 @@ mem_side=system.toL2Bus.slave[4]
[system.cpu1.interrupts]
type=ArmInterrupts
+[system.cpu1.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu1.itb]
type=ArmTLB
children=walker
@@ -287,7 +304,7 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.toL2Bus.slave[6]
@@ -311,57 +328,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@@ -373,11 +380,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -393,15 +400,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
@@ -416,7 +436,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@@ -425,7 +445,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@@ -472,7 +492,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@@ -490,11 +510,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@@ -503,7 +524,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@@ -512,7 +533,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@@ -529,7 +550,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@@ -543,7 +564,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@@ -553,7 +574,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@@ -563,7 +584,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@@ -573,7 +594,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@@ -587,7 +608,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@@ -600,7 +621,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@@ -629,7 +650,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@@ -639,7 +660,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@@ -651,7 +672,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@@ -663,7 +684,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@@ -676,7 +697,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@@ -686,7 +707,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@@ -696,7 +717,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@@ -706,7 +727,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@@ -716,7 +737,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -730,7 +751,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -743,7 +764,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@@ -758,7 +779,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@@ -768,7 +789,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@@ -778,7 +799,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@@ -788,7 +809,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@@ -805,7 +826,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
index 04178bb32..e8e271d58 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
@@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr icialluis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index 155c18cca..cecfd8ad7 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:31:36
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1207290627000 because m5_exit instruction encountered
+Exiting @ tick 1182882156500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index af19e8e2a..b637311d9 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -1,122 +1,140 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.182883 # Number of seconds simulated
-sim_ticks 1182883275000 # Number of ticks simulated
-final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.182882 # Number of seconds simulated
+sim_ticks 1182882156500 # Number of ticks simulated
+final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 656929 # Simulator instruction rate (inst/s)
-host_op_rate 837075 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12645375755 # Simulator tick rate (ticks/s)
-host_mem_usage 400812 # Number of bytes of host memory used
-host_seconds 93.54 # Real time elapsed on the host
-sim_insts 61450949 # Number of instructions simulated
-sim_ops 78302298 # Number of ops (including micro ops) simulated
+host_inst_rate 184229 # Simulator instruction rate (inst/s)
+host_op_rate 234741 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3546252898 # Simulator tick rate (ticks/s)
+host_mem_usage 402168 # Number of bytes of host memory used
+host_seconds 333.56 # Real time elapsed on the host
+sim_insts 61450993 # Number of instructions simulated
+sim_ops 78299715 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6653924 # Total number of read requests seen
-system.physmem.writeReqs 820678 # Total number of write requests seen
-system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425851136 # Total number of bytes read from memory
-system.physmem.bytesWritten 52523392 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654451 # Total number of read requests seen
+system.physmem.writeReqs 821128 # Total number of write requests seen
+system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425884864 # Total number of bytes read from memory
+system.physmem.bytesWritten 52552192 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1182878800500 # Total gap between requests
+system.physmem.totGap 1182877668000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159035 # Categorize read packet sizes
+system.physmem.readPktSize::6 159562 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -125,7 +143,7 @@ system.physmem.writePktSize::2 756836 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 63842 # categorize write packet sizes
+system.physmem.writePktSize::6 64292 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -134,26 +152,26 @@ system.physmem.neitherpktsize::2 0 # ca
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
@@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 37110.672889 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32833.976067 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38801.841792 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35260.147845 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 34311.151928 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
@@ -656,26 +656,26 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7072907 # DTB read hits
-system.cpu0.dtb.read_misses 3765 # DTB read misses
-system.cpu0.dtb.write_hits 5658426 # DTB write hits
-system.cpu0.dtb.write_misses 809 # DTB write misses
+system.cpu0.dtb.read_hits 7070111 # DTB read hits
+system.cpu0.dtb.read_misses 3764 # DTB read misses
+system.cpu0.dtb.write_hits 5656042 # DTB write hits
+system.cpu0.dtb.write_misses 804 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7076672 # DTB read accesses
-system.cpu0.dtb.write_accesses 5659235 # DTB write accesses
+system.cpu0.dtb.read_accesses 7073875 # DTB read accesses
+system.cpu0.dtb.write_accesses 5656846 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12731333 # DTB hits
-system.cpu0.dtb.misses 4574 # DTB misses
-system.cpu0.dtb.accesses 12735907 # DTB accesses
-system.cpu0.itb.inst_hits 29570611 # ITB inst hits
+system.cpu0.dtb.hits 12726153 # DTB hits
+system.cpu0.dtb.misses 4568 # DTB misses
+system.cpu0.dtb.accesses 12730721 # DTB accesses
+system.cpu0.itb.inst_hits 29570310 # ITB inst hits
system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
@@ -692,79 +692,79 @@ system.cpu0.itb.domain_faults 0 # Nu
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses
-system.cpu0.itb.hits 29570611 # DTB hits
+system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses
+system.cpu0.itb.hits 29570310 # DTB hits
system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29572816 # DTB accesses
-system.cpu0.numCycles 2365766550 # number of cpu cycles simulated
+system.cpu0.itb.accesses 29572515 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 28872677 # Number of instructions committed
-system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses
+system.cpu0.committedInsts 28872367 # Number of instructions committed
+system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
-system.cpu0.num_func_calls 1241693 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 33106294 # number of integer instructions
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system.cpu0.num_fp_insts 3860 # number of float instructions
-system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13399479 # number of memory refs
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-system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed
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system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit.
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+system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -895,66 +895,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -964,26 +964,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8308581 # DTB read hits
+system.cpu1.dtb.read_hits 8310545 # DTB read hits
system.cpu1.dtb.read_misses 3643 # DTB read misses
-system.cpu1.dtb.write_hits 5825594 # DTB write hits
-system.cpu1.dtb.write_misses 1436 # DTB write misses
+system.cpu1.dtb.write_hits 5827351 # DTB write hits
+system.cpu1.dtb.write_misses 1434 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8312224 # DTB read accesses
-system.cpu1.dtb.write_accesses 5827030 # DTB write accesses
+system.cpu1.dtb.read_accesses 8314188 # DTB read accesses
+system.cpu1.dtb.write_accesses 5828785 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14134175 # DTB hits
-system.cpu1.dtb.misses 5079 # DTB misses
-system.cpu1.dtb.accesses 14139254 # DTB accesses
-system.cpu1.itb.inst_hits 33188757 # ITB inst hits
+system.cpu1.dtb.hits 14137896 # DTB hits
+system.cpu1.dtb.misses 5077 # DTB misses
+system.cpu1.dtb.accesses 14142973 # DTB accesses
+system.cpu1.itb.inst_hits 33189113 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
@@ -1000,79 +1000,79 @@ system.cpu1.itb.domain_faults 0 # Nu
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses
-system.cpu1.itb.hits 33188757 # DTB hits
+system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses
+system.cpu1.itb.hits 33189113 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33190928 # DTB accesses
-system.cpu1.numCycles 2364324282 # number of cpu cycles simulated
+system.cpu1.itb.accesses 33191284 # DTB accesses
+system.cpu1.numCycles 2364318212 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32578272 # Number of instructions committed
-system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses
+system.cpu1.committedInsts 32578626 # Number of instructions committed
+system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 961975 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37307259 # number of integer instructions
+system.cpu1.num_func_calls 962009 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 37313171 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 14671912 # number of memory refs
-system.cpu1.num_load_insts 8630468 # Number of load instructions
-system.cpu1.num_store_insts 6041444 # Number of store instructions
-system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles
-system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles
+system.cpu1.num_mem_refs 14675641 # number of memory refs
+system.cpu1.num_load_insts 8632449 # Number of load instructions
+system.cpu1.num_store_insts 6043192 # Number of store instructions
+system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles
+system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed
-system.cpu1.icache.replacements 469210 # number of replacements
-system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use
-system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor
+system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed
+system.cpu1.icache.replacements 469194 # number of replacements
+system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use
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+system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy
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-system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 32719031 # number of overall hits
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-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles
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-system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency
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+system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles
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+system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles
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+system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses
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+system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses
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+system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles
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system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses
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-system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1203,66 +1203,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
@@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 663527e71..eecdc36d4 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -8,22 +8,23 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/gem5/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.realview.nvmem
-midr_regval=890224640
+mem_ranges=0:134217727
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@@ -64,16 +65,15 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/gem5/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -81,6 +81,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -89,6 +90,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=
@@ -100,27 +102,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@@ -130,41 +127,53 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -173,10 +182,42 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -197,56 +238,24 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=1
-forward_snoops=true
-hash_delay=1
-hit_latency=10000
-is_top_level=false
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
@@ -259,11 +268,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -279,15 +288,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
@@ -302,7 +324,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@@ -311,7 +333,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@@ -358,7 +380,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@@ -376,11 +398,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@@ -389,7 +412,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@@ -398,7 +421,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@@ -415,7 +438,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@@ -429,7 +452,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@@ -439,7 +462,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@@ -449,7 +472,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@@ -459,7 +482,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@@ -473,7 +496,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@@ -486,7 +509,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@@ -515,7 +538,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@@ -525,7 +548,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@@ -537,7 +560,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@@ -549,7 +572,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@@ -562,7 +585,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@@ -572,7 +595,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@@ -582,7 +605,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@@ -592,7 +615,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@@ -602,7 +625,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -616,7 +639,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -629,7 +652,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@@ -644,7 +667,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@@ -654,7 +677,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@@ -664,7 +687,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@@ -674,7 +697,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@@ -688,16 +711,6 @@ number=0
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
[system.vncserver]
type=VncServer
frame_capture=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index 9a28ceb37..3ee89fc27 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -11,7 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 956979587..fedaf9185 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 4 2013 21:17:24
+gem5 started Jan 4 2013 23:31:27
+gem5 executing on u200540
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2629149747000 because m5_exit instruction encountered
+Exiting @ tick 2603634694000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 50e9a8afa..fcb402e49 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,68 +1,80 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603636 # Number of seconds simulated
-sim_ticks 2603636076000 # Number of ticks simulated
-final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.603635 # Number of seconds simulated
+sim_ticks 2603634694000 # Number of ticks simulated
+final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 264193 # Simulator instruction rate (inst/s)
-host_op_rate 336182 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11426847777 # Simulator tick rate (ticks/s)
-host_mem_usage 395692 # Number of bytes of host memory used
-host_seconds 227.85 # Real time elapsed on the host
-sim_insts 60197128 # Number of instructions simulated
-sim_ops 76599899 # Number of ops (including micro ops) simulated
+host_inst_rate 156094 # Simulator instruction rate (inst/s)
+host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
+host_mem_usage 397752 # Number of bytes of host memory used
+host_seconds 385.65 # Real time elapsed on the host
+sim_insts 60197457 # Number of instructions simulated
+sim_ops 76600355 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494089 # Total number of read requests seen
-system.physmem.writeReqs 811479 # Total number of write requests seen
-system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991621696 # Total number of bytes read from memory
-system.physmem.bytesWritten 51934656 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize()
+system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494095 # Total number of read requests seen
+system.physmem.writeReqs 811481 # Total number of write requests seen
+system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991622080 # Total number of bytes read from memory
+system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis
@@ -73,12 +85,12 @@ system.physmem.perBankRdReqs::11 968056 # Tr
system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis
@@ -89,17 +101,17 @@ system.physmem.perBankWrReqs::11 51005 # Tr
system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603631716000 # Total gap between requests
+system.physmem.totGap 2603630334000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152013 # Categorize read packet sizes
+system.physmem.readPktSize::6 152019 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -108,7 +120,7 @@ system.physmem.writePktSize::2 754018 # ca
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 57461 # categorize write packet sizes
+system.physmem.writePktSize::6 57463 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -120,23 +132,23 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
@@ -153,10 +165,10 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see
@@ -169,56 +181,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh
system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests
-system.physmem.totBusLat 61975012000 # Total cycles spent in databus access
-system.physmem.totBankLat 216185438000 # Total cycles spent in bank access
-system.physmem.avgQLat 242.04 # Average queueing delay per request
-system.physmem.avgBankLat 13953.07 # Average bank access latency per request
+system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests
+system.physmem.totBusLat 61975036000 # Total cycles spent in databus access
+system.physmem.totBankLat 16863224000 # Total cycles spent in bank access
+system.physmem.avgQLat 18619.82 # Average queueing delay per request
+system.physmem.avgBankLat 1088.39 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 18195.12 # Average memory access latency
+system.physmem.avgMemAccLat 23708.21 # Average memory access latency
system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 2.51 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.11 # Average read queue length over time
-system.physmem.avgWrQLen 12.38 # Average write queue length over time
-system.physmem.readRowHits 15449450 # Number of row buffer hits during reads
-system.physmem.writeRowHits 784611 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes
-system.physmem.avgGap 159677.46 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.avgRdQLen 0.14 # Average read queue length over time
+system.physmem.avgWrQLen 12.40 # Average write queue length over time
+system.physmem.readRowHits 15451886 # Number of row buffer hits during reads
+system.physmem.writeRowHits 785061 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
+system.physmem.avgGap 159677.30 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
@@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14995523 # DTB read hits
-system.cpu.dtb.read_misses 7332 # DTB read misses
-system.cpu.dtb.write_hits 11230789 # DTB write hits
+system.cpu.dtb.read_hits 14995645 # DTB read hits
+system.cpu.dtb.read_misses 7331 # DTB read misses
+system.cpu.dtb.write_hits 11230857 # DTB write hits
system.cpu.dtb.write_misses 2203 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
@@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu
system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 15002855 # DTB read accesses
-system.cpu.dtb.write_accesses 11232992 # DTB write accesses
+system.cpu.dtb.read_accesses 15002976 # DTB read accesses
+system.cpu.dtb.write_accesses 11233060 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 26226312 # DTB hits
-system.cpu.dtb.misses 9535 # DTB misses
-system.cpu.dtb.accesses 26235847 # DTB accesses
-system.cpu.itb.inst_hits 61491068 # ITB inst hits
+system.cpu.dtb.hits 26226502 # DTB hits
+system.cpu.dtb.misses 9534 # DTB misses
+system.cpu.dtb.accesses 26236036 # DTB accesses
+system.cpu.itb.inst_hits 61491397 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
@@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 61495539 # ITB inst accesses
-system.cpu.itb.hits 61491068 # DTB hits
+system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
+system.cpu.itb.hits 61491397 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
-system.cpu.itb.accesses 61495539 # DTB accesses
-system.cpu.numCycles 5207272152 # number of cpu cycles simulated
+system.cpu.itb.accesses 61495868 # DTB accesses
+system.cpu.numCycles 5207269388 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 60197128 # Number of instructions committed
-system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses
+system.cpu.committedInsts 60197457 # Number of instructions committed
+system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
-system.cpu.num_func_calls 2139710 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls
-system.cpu.num_int_insts 68867725 # number of integer instructions
+system.cpu.num_func_calls 2139722 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
+system.cpu.num_int_insts 68868122 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
-system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read
-system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written
+system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
+system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
-system.cpu.num_mem_refs 27393681 # number of memory refs
-system.cpu.num_load_insts 15659530 # Number of load instructions
-system.cpu.num_store_insts 11734151 # Number of store instructions
-system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles
-system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles
-system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.879363 # Percentage of idle cycles
+system.cpu.num_mem_refs 27393871 # number of memory refs
+system.cpu.num_load_insts 15659652 # Number of load instructions
+system.cpu.num_store_insts 11734219 # Number of store instructions
+system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles
+system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles
+system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.879373 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
-system.cpu.icache.replacements 855500 # number of replacements
-system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use
-system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks.
+system.cpu.icache.replacements 855485 # number of replacements
+system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use
+system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits
-system.cpu.icache.overall_hits::total 60635056 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses
-system.cpu.icache.overall_misses::total 856012 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits
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+system.cpu.icache.overall_misses::total 855997 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -344,18 +344,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles
@@ -366,288 +366,152 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11480.986499 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11480.986499 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11480.986499 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 627255 # number of replacements
-system.cpu.dcache.tagsinuse 511.914823 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23654861 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 627767 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.680956 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 460735000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.914823 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999834 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999834 # Average percentage of cache occupancy
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32707.824249 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 44802 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 32668.666667 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33282.876758 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -751,6 +615,142 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
@@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles
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system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 19:44:43 +0000