diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-07-22 20:31:24 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-07-22 20:31:24 -0500 |
| commit | 2590a7dd0a563d8548ba13a62c9ea8b82fa464ad (patch) | |
| tree | 87c6d67b85cbe7e328576b263a4a992117ef9709 /tests/quick/fs/10.linux-boot | |
| parent | 11a551ae3ac179c6ce0e72dccfd4476fdf640798 (diff) | |
| download | gem5-2590a7dd0a563d8548ba13a62c9ea8b82fa464ad.tar.xz | |
Regression: Update stats due to changes to x86 cpuid instruction
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
8 files changed, 216 insertions, 208 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 8bff0c61a..a4365933a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic memories=system.physmem @@ -608,7 +608,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.pc.pciconfig.pio master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master @@ -670,9 +670,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] @@ -934,7 +934,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -954,7 +954,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1150,7 +1150,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index fd09f1faf..a77b4f0ee 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -3,6 +3,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: instruction 'fxsave' unimplemented +warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 18f4bf90b..d8387d75d 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,12 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:08:09 -gem5 started Jun 28 2012 23:02:50 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Jul 22 2012 08:05:39 +gem5 started Jul 22 2012 08:43:43 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 1886c90bb..96f4e7d80 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1996585 # Simulator instruction rate (inst/s) -host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51080652430 # Simulator tick rate (ticks/s) -host_mem_usage 357308 # Number of bytes of host memory used -host_seconds 100.08 # Real time elapsed on the host -sim_insts 199813912 # Number of instructions simulated -sim_ops 409133288 # Number of ops (including micro ops) simulated +host_inst_rate 1067695 # Simulator instruction rate (inst/s) +host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27315912254 # Simulator tick rate (ticks/s) +host_mem_usage 409548 # Number of bytes of host memory used +host_seconds 187.15 # Real time elapsed on the host +sim_insts 199813914 # Number of instructions simulated +sim_ops 409133298 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -47,16 +47,16 @@ system.physmem.bw_total::cpu.inst 167022 # To system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 106561 # number of replacements -system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use +system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use system.l2c.total_refs 3457342 # Total number of references to valid blocks. system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -213,54 +213,54 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199813912 # Number of instructions committed -system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses +system.cpu.committedInsts 199813914 # Number of instructions committed +system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls -system.cpu.num_int_insts 374297254 # number of integer instructions +system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls +system.cpu.num_int_insts 374297264 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read -system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written +system.cpu.num_int_register_reads 1159028989 # number of times the integer registers were read +system.cpu.num_int_register_writes 636431681 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_mem_refs 35626517 # number of memory refs system.cpu.num_load_insts 27217782 # Number of load instructions system.cpu.num_store_insts 8408735 # Number of store instructions -system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles -system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles +system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles +system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955646 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790793 # number of replacements system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. +system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits -system.cpu.icache.overall_hits::total 243365777 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits +system.cpu.icache.overall_hits::total 243365779 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses system.cpu.icache.overall_misses::total 791312 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 04a12f8a0..8535283af 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -668,7 +668,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] @@ -930,7 +930,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -950,7 +950,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index fd09f1faf..a77b4f0ee 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -3,6 +3,7 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: instruction 'fxsave' unimplemented +warn: x86 cpuid: unknown family 0x8086 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 66f0cf496..64807f302 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 12:41:46 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Jul 22 2012 08:05:39 +gem5 started Jul 22 2012 08:43:19 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5191766314000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b0d3b38b0..49cb796d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.191766 # Nu sim_ticks 5191766314000 # Number of ticks simulated final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 843973 # Simulator instruction rate (inst/s) -host_op_rate 1619974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31713438762 # Simulator tick rate (ticks/s) -host_mem_usage 354068 # Number of bytes of host memory used -host_seconds 163.71 # Real time elapsed on the host -sim_insts 138165779 # Number of instructions simulated -sim_ops 265203823 # Number of ops (including micro ops) simulated +host_inst_rate 672863 # Simulator instruction rate (inst/s) +host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25283717995 # Simulator tick rate (ticks/s) +host_mem_usage 405876 # Number of bytes of host memory used +host_seconds 205.34 # Real time elapsed on the host +sim_insts 138165780 # Number of instructions simulated +sim_ops 265203824 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory @@ -43,15 +43,15 @@ system.physmem.bw_total::cpu.inst 158183 # To system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 86221 # number of replacements -system.l2c.tagsinuse 64766.656106 # Cycle average of tags in use -system.l2c.total_refs 3491041 # Total number of references to valid blocks. +system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use +system.l2c.total_refs 3491043 # Total number of references to valid blocks. system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.127594 # Average number of references to valid blocks. +system.l2c.avg_refs 23.127608 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50170.355132 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3484.481213 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11111.678563 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy @@ -60,10 +60,10 @@ system.l2c.occ_percent::total 0.988261 # Av system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1279350 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2065978 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1542134 # number of Writeback hits -system.l2c.Writeback_hits::total 1542134 # number of Writeback hits +system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits +system.l2c.Writeback_hits::total 1542135 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits @@ -71,13 +71,13 @@ system.l2c.ReadExReq_hits::total 200451 # nu system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1479801 # number of demand (read+write) hits -system.l2c.demand_hits::total 2266429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits +system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits system.l2c.overall_hits::cpu.dtb.walker 6306 # number of overall hits system.l2c.overall_hits::cpu.itb.walker 2757 # number of overall hits system.l2c.overall_hits::cpu.inst 777565 # number of overall hits -system.l2c.overall_hits::cpu.data 1479801 # number of overall hits -system.l2c.overall_hits::total 2266429 # number of overall hits +system.l2c.overall_hits::cpu.data 1479802 # number of overall hits +system.l2c.overall_hits::total 2266430 # number of overall hits system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.inst 12833 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 28373 # number of ReadReq misses @@ -113,10 +113,10 @@ system.l2c.overall_miss_latency::total 7997111500 # nu system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1307723 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2107189 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1542134 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1542134 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) @@ -124,13 +124,13 @@ system.l2c.ReadExReq_accesses::total 312686 # nu system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1620409 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2419875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.dtb.walker 6306 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.itb.walker 2762 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu.inst 790398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1620409 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2419875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001810 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.016236 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.021696 # miss rate for ReadReq accesses @@ -357,72 +357,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10383532628 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 138165779 # Number of instructions committed -system.cpu.committedOps 265203823 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 249613018 # Number of integer alu accesses +system.cpu.committedInsts 138165780 # Number of instructions committed +system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 24887740 # number of instructions that are conditional controls -system.cpu.num_int_insts 249613018 # number of integer instructions +system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls +system.cpu.num_int_insts 249613019 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 778264797 # number of times the integer registers were read -system.cpu.num_int_register_writes 423017345 # number of times the integer registers were written +system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read +system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 23180618 # number of memory refs -system.cpu.num_load_insts 14822217 # Number of load instructions -system.cpu.num_store_insts 8358401 # Number of store instructions -system.cpu.num_idle_cycles 9771874940.286118 # Number of idle cycles -system.cpu.num_busy_cycles 611657687.713882 # Number of busy cycles +system.cpu.num_mem_refs 23180616 # number of memory refs +system.cpu.num_load_insts 14822216 # Number of load instructions +system.cpu.num_store_insts 8358400 # Number of store instructions +system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles +system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles system.cpu.idle_fraction 0.941093 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 789892 # number of replacements system.cpu.icache.tagsinuse 510.351457 # Cycle average of tags in use -system.cpu.icache.total_refs 158472874 # Total number of references to valid blocks. +system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 790404 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200.496043 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 160421907000 # Cycle when the warmup percentage was hit. +system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.351457 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996780 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996780 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 158472874 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 158472874 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 158472874 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 158472874 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 158472874 # number of overall hits -system.cpu.icache.overall_hits::total 158472874 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits +system.cpu.icache.overall_hits::total 158472876 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses system.cpu.icache.overall_misses::total 790411 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780929500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11780929500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11780929500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11780929500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11780929500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11780929500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 159263285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 159263285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 159263285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 159263285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 159263285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 159263285 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.004963 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.004963 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.004963 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.814710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.814710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.814710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.814710 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,31 +439,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 790411 system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408678500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9408678500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408678500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9408678500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408678500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9408678500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004963 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.004963 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.004963 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.526773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.526773 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3403 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.070913 # Cycle average of tags in use system.cpu.itb_walker_cache.total_refs 8040 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3415 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.354319 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164836909000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070913 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191932 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.191932 # Average percentage of cache occupancy @@ -547,7 +547,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cy system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5161009068000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy @@ -622,63 +622,63 @@ system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1620697 # number of replacements +system.cpu.dcache.replacements 1620698 # number of replacements system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use -system.cpu.dcache.total_refs 20024819 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621209 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.351781 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11989145 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11989145 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8033493 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8033493 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20022638 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20022638 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20022638 # number of overall hits -system.cpu.dcache.overall_hits::total 20022638 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308549 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308549 # number of ReadReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits +system.cpu.dcache.overall_hits::total 20022635 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623421 # number of overall misses -system.cpu.dcache.overall_misses::total 1623421 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872658500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19872658500 # 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number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles @@ -715,18 +715,18 @@ system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.751128 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.751128 # 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