diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/fs/10.linux-boot | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
13 files changed, 9227 insertions, 9014 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index b3504c645..a85398f56 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2576820 # Simulator instruction rate (inst/s) -host_op_rate 2576818 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74107088123 # Simulator tick rate (ticks/s) -host_mem_usage 319644 # Number of bytes of host memory used -host_seconds 25.23 # Real time elapsed on the host +host_inst_rate 2452265 # Simulator instruction rate (inst/s) +host_op_rate 2452264 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70524991939 # Simulator tick rate (ticks/s) +host_mem_usage 374768 # Number of bytes of host memory used +host_seconds 26.51 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66539648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 763584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68179008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7831360 # Number of bytes written to this memory -system.physmem.bytes_written::total 7831360 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1663 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 68173952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 763584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 869824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory +system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065297 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122365 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122365 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35594910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56935 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1065218 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 408474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36471874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4189330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4189330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4189330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35594910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 36469170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 408474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 465306 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 408474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40661204 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40660828 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632997 # number of writebacks -system.cpu0.dcache.writebacks::total 632997 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks +system.cpu0.dcache.writebacks::total 632989 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 618298 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use @@ -655,8 +655,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7628 # Transaction distribution system.iobus.trans_dist::ReadResp 7628 # Transaction distribution system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 14588 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 56140 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -705,24 +704,24 @@ system.iocache.tags.tag_accesses 375579 # Nu system.iocache.tags.data_accesses 375579 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses system.iocache.demand_misses::total 179 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 179 # number of overall misses system.iocache.overall_misses::total 179 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -738,89 +737,86 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999763 # number of replacements -system.l2c.tags.tagsinuse 65320.982513 # Cycle average of tags in use -system.l2c.tags.total_refs 2387511 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064813 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.242188 # Average number of references to valid blocks. +system.l2c.tags.replacements 999684 # number of replacements +system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use +system.l2c.tags.total_refs 4588619 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064734 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.309639 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56016.894287 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4834.499535 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4176.023150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 178.992489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.573052 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55911.037805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4939.570238 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.759225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.853135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075372 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063732 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48943 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31464842 # Number of tag accesses -system.l2c.tags.data_accesses 31464842 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 606959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 626686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 379549 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1742207 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 777528 # number of Writeback hits -system.l2c.Writeback_hits::total 777528 # number of Writeback hits +system.l2c.tags.tag_accesses 49101323 # Number of tag accesses +system.l2c.tags.data_accesses 49101323 # Number of data accesses +system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits +system.l2c.Writeback_hits::total 777520 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111433 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168036 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 606959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738119 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379549 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 606993 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 986545 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 606993 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910243 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 606959 # number of overall hits -system.l2c.overall_hits::cpu0.data 738119 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379549 # number of overall hits +system.l2c.demand_hits::total 1910322 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606993 # number of overall hits +system.l2c.overall_hits::cpu0.data 738161 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910243 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1663 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941271 # number of ReadReq misses +system.l2c.overall_hits::total 1910322 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124985 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1663 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 11931 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13591 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 11931 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066256 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1663 # number of overall misses +system.l2c.demand_misses::total 1066177 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11931 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses system.l2c.overall_misses::cpu1.data 12102 # number of overall misses -system.l2c.overall_misses::total 1066256 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 618924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1553296 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 381212 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2683478 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 777528 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 777528 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::total 1066177 # number of overall misses +system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses) @@ -830,6 +826,12 @@ system.l2c.SCUpgradeReq_accesses::total 2335 # nu system.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 618924 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 381212 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1000136 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553296 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses @@ -840,30 +842,31 @@ system.l2c.overall_accesses::cpu0.data 1778645 # nu system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.596544 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004362 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505509 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426539 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.585010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004362 # miss rate for demand accesses +system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019277 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013589 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358225 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.585010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004362 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.358198 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358225 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358198 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,79 +875,84 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80845 # number of writebacks -system.l2c.writebacks::total 80845 # number of writebacks +system.l2c.writebacks::writebacks 80913 # number of writebacks +system.l2c.writebacks::total 80913 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 948899 # Transaction distribution -system.membus.trans_dist::ReadResp 948899 # Transaction distribution +system.membus.trans_dist::ReadReq 7449 # Transaction distribution +system.membus.trans_dist::ReadResp 948863 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::Writeback 122365 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 122433 # Transaction distribution +system.membus.trans_dist::CleanEvict 922490 # Transaction distribution system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution -system.membus.trans_dist::ReadExReq 126515 # Transaction distribution -system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.trans_dist::ReadExReq 126472 # Transaction distribution +system.membus.trans_dist::ReadExResp 124247 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941414 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 2300222 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2425204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3178369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3222443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3347604 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73456146 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73455442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76124178 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1287715 # Request fanout histogram +system.membus.snoop_fanout::samples 2210194 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1287715 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2210194 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1287715 # Request fanout histogram -system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution +system.membus.snoop_fanout::total 2210194 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 777528 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2204578 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237890 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762424 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627155 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6929248 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856188 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450155 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143095 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133818 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758587 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41895 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3895119 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.010714 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102951 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 6099689 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.006841 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.082430 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3853388 98.93% 98.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41731 1.07% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 6057958 99.32% 99.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 0.68% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3895119 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 6099689 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 3fe61f3f7..60a4f6e98 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2059947 # Simulator instruction rate (inst/s) -host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62765242809 # Simulator tick rate (ticks/s) -host_mem_usage 317596 # Number of bytes of host memory used -host_seconds 29.15 # Real time elapsed on the host +host_inst_rate 2495393 # Simulator instruction rate (inst/s) +host_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76033049021 # Simulator tick rate (ticks/s) +host_mem_usage 371696 # Number of bytes of host memory used +host_seconds 24.06 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory +system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks -system.cpu.dcache.writebacks::total 833501 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks +system.cpu.dcache.writebacks::total 833493 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 919605 # number of replacements system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use @@ -336,84 +336,88 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992219 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses +system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,36 +426,39 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks +system.cpu.l2cache.writebacks::total 74334 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41883 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -467,8 +474,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7358 # Transaction distribution system.iobus.trans_dist::ReadResp 7358 # Transaction distribution system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 9838 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51390 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -517,24 +523,24 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -550,41 +556,43 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 948404 # Transaction distribution -system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::ReadReq 7184 # Transaction distribution +system.membus.trans_dist::ReadResp 948374 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::Writeback 115797 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 115846 # Transaction distribution +system.membus.trans_dist::CleanEvict 918371 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116991 # Transaction distribution -system.membus.trans_dist::ReadExResp 116991 # Transaction distribution +system.membus.trans_dist::ReadExReq 116946 # Transaction distribution +system.membus.trans_dist::ReadExResp 116946 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1232714 # Request fanout histogram +system.membus.snoop_fanout::samples 2151059 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1232714 # Request fanout histogram +system.membus.snoop_fanout::total 2151059 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3f2e8762f..67605a567 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962613 # Number of seconds simulated -sim_ticks 1962612686500 # Number of ticks simulated -final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962608 # Number of seconds simulated +sim_ticks 1962608482500 # Number of ticks simulated +final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1118839 # Simulator instruction rate (inst/s) -host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36057415911 # Simulator tick rate (ticks/s) -host_mem_usage 319640 # Number of bytes of host memory used -host_seconds 54.43 # Real time elapsed on the host -sim_insts 60898638 # Number of instructions simulated -sim_ops 60898638 # Number of ops (including micro ops) simulated +host_inst_rate 1019388 # Simulator instruction rate (inst/s) +host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32859851956 # Simulator tick rate (ticks/s) +host_mem_usage 375280 # Number of bytes of host memory used +host_seconds 59.73 # Real time elapsed on the host +sim_insts 60884587 # Number of instructions simulated +sim_ops 60884587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory +system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406851 # Number of read requests accepted -system.physmem.writeReqs 161902 # Number of write requests accepted -system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25141 # Per bank write bursts -system.physmem.perBankRdBursts::1 25398 # Per bank write bursts -system.physmem.perBankRdBursts::2 25524 # Per bank write bursts -system.physmem.perBankRdBursts::3 24918 # Per bank write bursts -system.physmem.perBankRdBursts::4 25169 # Per bank write bursts -system.physmem.perBankRdBursts::5 25258 # Per bank write bursts -system.physmem.perBankRdBursts::6 25808 # Per bank write bursts -system.physmem.perBankRdBursts::7 25541 # Per bank write bursts -system.physmem.perBankRdBursts::8 25675 # Per bank write bursts -system.physmem.perBankRdBursts::9 25330 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25615 # Per bank write bursts -system.physmem.perBankRdBursts::12 25647 # Per bank write bursts -system.physmem.perBankRdBursts::13 25653 # Per bank write bursts -system.physmem.perBankRdBursts::14 25754 # Per bank write bursts -system.physmem.perBankRdBursts::15 25033 # Per bank write bursts -system.physmem.perBankWrBursts::0 8965 # Per bank write bursts -system.physmem.perBankWrBursts::1 8625 # Per bank write bursts -system.physmem.perBankWrBursts::2 8456 # Per bank write bursts -system.physmem.perBankWrBursts::3 7799 # Per bank write bursts -system.physmem.perBankWrBursts::4 8065 # Per bank write bursts -system.physmem.perBankWrBursts::5 8041 # Per bank write bursts -system.physmem.perBankWrBursts::6 8610 # Per bank write bursts -system.physmem.perBankWrBursts::7 8172 # Per bank write bursts -system.physmem.perBankWrBursts::8 8465 # Per bank write bursts -system.physmem.perBankWrBursts::9 8053 # Per bank write bursts -system.physmem.perBankWrBursts::10 8222 # Per bank write bursts -system.physmem.perBankWrBursts::11 8481 # Per bank write bursts -system.physmem.perBankWrBursts::12 8850 # Per bank write bursts -system.physmem.perBankWrBursts::13 9510 # Per bank write bursts -system.physmem.perBankWrBursts::14 9309 # Per bank write bursts -system.physmem.perBankWrBursts::15 8651 # Per bank write bursts +system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406729 # Number of read requests accepted +system.physmem.writeReqs 120393 # Number of write requests accepted +system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25025 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25447 # Per bank write bursts +system.physmem.perBankRdBursts::3 24899 # Per bank write bursts +system.physmem.perBankRdBursts::4 25181 # Per bank write bursts +system.physmem.perBankRdBursts::5 25235 # Per bank write bursts +system.physmem.perBankRdBursts::6 25799 # Per bank write bursts +system.physmem.perBankRdBursts::7 25539 # Per bank write bursts +system.physmem.perBankRdBursts::8 25681 # Per bank write bursts +system.physmem.perBankRdBursts::9 25348 # Per bank write bursts +system.physmem.perBankRdBursts::10 25259 # Per bank write bursts +system.physmem.perBankRdBursts::11 25592 # Per bank write bursts +system.physmem.perBankRdBursts::12 25653 # Per bank write bursts +system.physmem.perBankRdBursts::13 25554 # Per bank write bursts +system.physmem.perBankRdBursts::14 25887 # Per bank write bursts +system.physmem.perBankRdBursts::15 25094 # Per bank write bursts +system.physmem.perBankWrBursts::0 7701 # Per bank write bursts +system.physmem.perBankWrBursts::1 7641 # Per bank write bursts +system.physmem.perBankWrBursts::2 7454 # Per bank write bursts +system.physmem.perBankWrBursts::3 6926 # Per bank write bursts +system.physmem.perBankWrBursts::4 7165 # Per bank write bursts +system.physmem.perBankWrBursts::5 7117 # Per bank write bursts +system.physmem.perBankWrBursts::6 7626 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7527 # Per bank write bursts +system.physmem.perBankWrBursts::9 7238 # Per bank write bursts +system.physmem.perBankWrBursts::10 7225 # Per bank write bursts +system.physmem.perBankWrBursts::11 7418 # Per bank write bursts +system.physmem.perBankWrBursts::12 7843 # Per bank write bursts +system.physmem.perBankWrBursts::13 8207 # Per bank write bursts +system.physmem.perBankWrBursts::14 8447 # Per bank write bursts +system.physmem.perBankWrBursts::15 7584 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1962566141500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1962561950500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406851 # Read request sizes (log2) +system.physmem.readPktSize::6 406729 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 161902 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120393 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,190 +158,181 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads -system.physmem.totQLat 2137457500 # Total ticks spent queuing -system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads +system.physmem.totQLat 2204423500 # Total ticks spent queuing +system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 364433 # Number of row buffer hits during reads -system.physmem.writeRowHits 110956 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes -system.physmem.avgGap 3450647.54 # Average gap between requests -system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.688732 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 363741 # Number of row buffer hits during reads +system.physmem.writeRowHits 96228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes +system.physmem.avgGap 3723164.56 # Average gap between requests +system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.630269 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.721130 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.683332 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_hits 7500026 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_hits 5074087 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_hits 12574113 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_hits 3504450 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3505822 # ITB accesses +system.cpu0.itb.fetch_accesses 3508321 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,91 +345,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838766 # number of cpu cycles simulated +system.cpu0.numCycles 3923838721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47743384 # Number of instructions committed -system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses -system.cpu0.num_func_calls 1202353 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44279734 # number of integer instructions -system.cpu0.num_fp_insts 210698 # number of float instructions -system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599731 # number of memory refs -system.cpu0.num_load_insts 7519361 # Number of load instructions -system.cpu0.num_store_insts 5080370 # Number of store instructions -system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles -system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles -system.cpu0.Branches 7198745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction -system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.committedInsts 47783493 # Number of instructions committed +system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses +system.cpu0.num_func_calls 1203861 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44315744 # number of integer instructions +system.cpu0.num_fp_insts 211234 # number of float instructions +system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written +system.cpu0.num_mem_refs 12614351 # number of memory refs +system.cpu0.num_load_insts 7527207 # Number of load instructions +system.cpu0.num_store_insts 5087144 # Number of store instructions +system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles +system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles +system.cpu0.Branches 7204257 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction +system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction +system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47751984 # Class of executed instruction +system.cpu0.op_class::total 47792093 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -470,124 +461,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149812 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.callpal::total 150081 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1282 system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3068 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1180939 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.kern.swap_context 3073 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1181794 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses -system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits +system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses +system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,126 +587,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks -system.cpu0.dcache.writebacks::total 679102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks +system.cpu0.dcache.writebacks::total 679941 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 698758 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 700401 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits -system.cpu0.icache.overall_hits::total 47052596 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses -system.cpu0.icache.overall_misses::total 699388 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits +system.cpu0.icache.overall_hits::total 47091062 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses +system.cpu0.icache.overall_misses::total 701031 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,51 +715,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_hits 2409623 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_hits 1749165 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_hits 4158788 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_hits 1960477 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1965317 # ITB accesses +system.cpu1.itb.fetch_accesses 1961693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -781,87 +772,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925225373 # number of cpu cycles simulated +system.cpu1.numCycles 3925216965 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13155254 # Number of instructions committed -system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses -system.cpu1.num_func_calls 411301 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12132982 # number of integer instructions -system.cpu1.num_fp_insts 173111 # number of float instructions -system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written -system.cpu1.num_mem_refs 4200357 # number of memory refs -system.cpu1.num_load_insts 2433886 # Number of load instructions -system.cpu1.num_store_insts 1766471 # Number of store instructions -system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles -system.cpu1.Branches 1871330 # Number of branches fetched -system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction -system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.committedInsts 13101094 # Number of instructions committed +system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses +system.cpu1.num_func_calls 409417 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12083765 # number of integer instructions +system.cpu1.num_fp_insts 172106 # number of float instructions +system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written +system.cpu1.num_mem_refs 4182249 # number of memory refs +system.cpu1.num_load_insts 2423870 # Number of load instructions +system.cpu1.num_store_insts 1758379 # Number of store instructions +system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles +system.cpu1.Branches 1864071 # Number of branches fetched +system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction +system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13158616 # Class of executed instruction +system.cpu1.op_class::total 13104456 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -877,124 +868,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71473 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 427 -system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71137 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches +system.cpu1.kern.mode_switch::user 465 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 +system.cpu1.kern.mode_good::user 465 +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1998 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 166165 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1986 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 165381 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits -system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses -system.cpu1.dcache.overall_misses::total 180698 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits +system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses +system.cpu1.dcache.overall_misses::total 179876 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1003,128 +994,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks -system.cpu1.dcache.writebacks::total 114146 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks +system.cpu1.dcache.writebacks::total 113645 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 315648 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 313887 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits -system.cpu1.icache.overall_hits::total 12842415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses -system.cpu1.icache.overall_misses::total 316202 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits +system.cpu1.icache.overall_hits::total 12790016 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses +system.cpu1.icache.overall_misses::total 314441 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1133,30 +1124,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1172,10 +1163,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55604 # Transaction distribution -system.iobus.trans_dist::WriteResp 14052 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55595 # Transaction distribution +system.iobus.trans_dist::WriteResp 55595 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1187,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1203,11 +1193,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1229,23 +1219,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1253,49 +1243,49 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1303,211 +1293,217 @@ system.iocache.writebacks::writebacks 41520 # nu system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341367 # number of replacements -system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use -system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy +system.l2c.tags.replacements 341250 # number of replacements +system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use +system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25960355 # Number of tag accesses -system.l2c.tags.data_accesses 25960355 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits -system.l2c.Writeback_hits::total 793248 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 35905885 # Number of tag accesses +system.l2c.tags.data_accesses 35905885 # Number of data accesses +system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits +system.l2c.Writeback_hits::total 793586 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits -system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits -system.l2c.overall_hits::cpu0.data 790979 # number of overall hits -system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits -system.l2c.overall_hits::cpu1.data 155940 # number of overall hits -system.l2c.overall_hits::total 1948960 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6589 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13070 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387263 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 457 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6823 # number of demand (read+write) misses -system.l2c.demand_misses::total 407613 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13070 # number of overall misses -system.l2c.overall_misses::cpu0.data 387263 # number of overall misses -system.l2c.overall_misses::cpu1.inst 457 # number of overall misses -system.l2c.overall_misses::cpu1.data 6823 # number of overall misses -system.l2c.overall_misses::total 407613 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1052716500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 19700886500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 37366250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 18492250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 20809461500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1635455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 13268077 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 14903532 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1334957 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 185994 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1520951 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8793301011 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 540094736 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9333395747 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1052716500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 28494187511 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 37366250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 558586986 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30142857247 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1052716500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 28494187511 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 37366250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 558586986 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30142857247 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 699367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 936074 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 316201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 108940 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2060582 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793248 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3132 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2260 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5392 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1849 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 242168 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 53823 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295991 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 699367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1178242 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 316201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 162763 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2356573 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 699367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1178242 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 316201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 162763 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2356573 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.290186 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001445 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002148 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138503 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941571 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768142 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.868880 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961207 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.967550 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.477466 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.122420 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.412904 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328679 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001445 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.041920 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172969 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328679 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001445 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.041920 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172969 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80544.491201 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 554.579518 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1496.588565 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 850.168250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76368.034848 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73949.695537 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73949.695537 # average overall miss latency +system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits +system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits +system.l2c.overall_hits::cpu0.data 791881 # number of overall hits +system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits +system.l2c.overall_hits::cpu1.data 155607 # number of overall hits +system.l2c.overall_hits::total 1949434 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115542 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6588 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122130 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12999 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 505 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 271618 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 236 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271854 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 12999 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387160 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6824 # number of demand (read+write) misses +system.l2c.demand_misses::total 407488 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12999 # number of overall misses +system.l2c.overall_misses::cpu0.data 387160 # number of overall misses +system.l2c.overall_misses::cpu1.inst 505 # number of overall misses +system.l2c.overall_misses::cpu1.data 6824 # number of overall misses +system.l2c.overall_misses::total 407488 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1432000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 13109500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14541500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1162500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1376500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8812996500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 538144500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9351141000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1038304000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 40757500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1079061500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19659409500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 18967000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 19678376500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1038304000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 28472406000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 40757500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 557111500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30108579000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1038304000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 28472406000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 40757500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 557111500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30108579000 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 793586 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 793586 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2268 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5376 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 925 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1842 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53580 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295940 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 701010 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 314440 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1015450 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 936681 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 108851 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1045532 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 701010 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1179041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 314440 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 162431 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356922 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 701010 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1179041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 314440 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 162431 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2356922 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944337 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764109 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868304 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.953514 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973828 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.963626 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.476737 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122956 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412685 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018543 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001606 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013299 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.289979 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002168 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.260015 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328369 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001606 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.042012 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172890 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328369 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001606 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.042012 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172890 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 487.904600 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7564.627813 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3115.145673 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1318.027211 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 239.641657 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 775.492958 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76275.263541 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81685.564663 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76567.108818 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 79875.682745 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80707.920792 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 79906.805391 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 72378.890574 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 80368.644068 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 72385.826583 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79875.682745 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73541.703688 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80707.920792 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81640.020516 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 73888.259286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79875.682745 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73541.703688 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80707.920792 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81640.020516 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 73888.259286 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1516,231 +1512,241 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78830 # number of writebacks -system.l2c.writebacks::total 78830 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 78873 # number of writebacks +system.l2c.writebacks::total 78873 # number of writebacks +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13067 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271636 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 449 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 234 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285386 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1736 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4685 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1789 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6589 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122216 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13067 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387263 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 449 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6823 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407602 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13067 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387263 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses +system.l2c.CleanEvict_mshr_misses::writebacks 324 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 324 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4668 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 882 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 893 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1775 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115542 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6588 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122130 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12999 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 494 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13493 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271618 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 236 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271854 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12999 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387160 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 494 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6824 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407477 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12999 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387160 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 494 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6824 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407477 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14052 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21251 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347146989 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7804870753 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 23652214489 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25045404253 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 23652214489 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25045404253 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17620000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1392496000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153050500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674536000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2827586500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527926500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4220082500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575 # average overall mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14043 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 21242 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 60572500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 35873500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 96446000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 18219500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18324500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 36544000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7657576500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 472264500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8129841000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 908314000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 35012500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 943326500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 16943229500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 16607000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 16959836500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 908314000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 24600806000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 35012500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 488871500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26033004000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 908314000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 24600806000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 35012500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 488871500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26033004000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1403353000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17974000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1421327000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2195335000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 686710000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2882045000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3598688000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 704684000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4303372000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944337 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292759 # Transaction distribution -system.membus.trans_dist::ReadResp 292759 # Transaction distribution -system.membus.trans_dist::WriteReq 14052 # Transaction distribution -system.membus.trans_dist::WriteResp 14052 # Transaction distribution -system.membus.trans_dist::Writeback 120350 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution -system.membus.trans_dist::ReadExReq 122543 # Transaction distribution -system.membus.trans_dist::ReadExResp 121713 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21558 # Total snoops (count) -system.membus.snoop_fanout::samples 618592 # Request fanout histogram +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292720 # Transaction distribution +system.membus.trans_dist::WriteReq 14043 # Transaction distribution +system.membus.trans_dist::WriteResp 14043 # Transaction distribution +system.membus.trans_dist::Writeback 120393 # Transaction distribution +system.membus.trans_dist::CleanEvict 261901 # Transaction distribution +system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution +system.membus.trans_dist::ReadExReq 122456 # Transaction distribution +system.membus.trans_dist::ReadExResp 121630 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21449 # Total snoops (count) +system.membus.snoop_fanout::samples 880387 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 618592 # Request fanout histogram -system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 880387 # Request fanout histogram +system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 98552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 480853 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 8fa2e66de..5922aa080 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922414 # Number of seconds simulated -sim_ticks 1922413663500 # Number of ticks simulated -final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922397 # Number of seconds simulated +sim_ticks 1922397182500 # Number of ticks simulated +final_tick 1922397182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 912210 # Simulator instruction rate (inst/s) -host_op_rate 912209 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31217732593 # Simulator tick rate (ticks/s) -host_mem_usage 318584 # Number of bytes of host memory used -host_seconds 61.58 # Real time elapsed on the host -sim_insts 56174594 # Number of instructions simulated -sim_ops 56174594 # Number of ops (including micro ops) simulated +host_inst_rate 1085217 # Simulator instruction rate (inst/s) +host_op_rate 1085217 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37124537063 # Simulator tick rate (ticks/s) +host_mem_usage 372212 # Number of bytes of host memory used +host_seconds 51.78 # Real time elapsed on the host +sim_insts 56195121 # Number of instructions simulated +sim_ops 56195121 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 848768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858048 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25707776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 848768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 848768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7409088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7409088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13262 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388407 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401684 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115767 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115767 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 441515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12930756 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13372770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 441515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3854088 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3854088 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3854088 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 441515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12930756 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401737 # Number of read requests accepted -system.physmem.writeReqs 157245 # Number of write requests accepted -system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue -system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25230 # Per bank write bursts -system.physmem.perBankRdBursts::1 25660 # Per bank write bursts -system.physmem.perBankRdBursts::2 25603 # Per bank write bursts -system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24970 # Per bank write bursts -system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.bw_total::total 17226858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401684 # Number of read requests accepted +system.physmem.writeReqs 115767 # Number of write requests accepted +system.physmem.readBursts 401684 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115767 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25700352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 7407168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25707776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7409088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 41682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25233 # Per bank write bursts +system.physmem.perBankRdBursts::1 25641 # Per bank write bursts +system.physmem.perBankRdBursts::2 25574 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts +system.physmem.perBankRdBursts::4 24973 # Per bank write bursts +system.physmem.perBankRdBursts::5 24969 # Per bank write bursts system.physmem.perBankRdBursts::6 24206 # Per bank write bursts -system.physmem.perBankRdBursts::7 24492 # Per bank write bursts -system.physmem.perBankRdBursts::8 25173 # Per bank write bursts -system.physmem.perBankRdBursts::9 24777 # Per bank write bursts -system.physmem.perBankRdBursts::10 25267 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24505 # Per bank write bursts -system.physmem.perBankRdBursts::13 25378 # Per bank write bursts -system.physmem.perBankRdBursts::14 25651 # Per bank write bursts -system.physmem.perBankRdBursts::15 25357 # Per bank write bursts -system.physmem.perBankWrBursts::0 8677 # Per bank write bursts -system.physmem.perBankWrBursts::1 8490 # Per bank write bursts -system.physmem.perBankWrBursts::2 8972 # Per bank write bursts -system.physmem.perBankWrBursts::3 8549 # Per bank write bursts -system.physmem.perBankWrBursts::4 8030 # Per bank write bursts -system.physmem.perBankWrBursts::5 7962 # Per bank write bursts -system.physmem.perBankWrBursts::6 7256 # Per bank write bursts -system.physmem.perBankWrBursts::7 7133 # Per bank write bursts -system.physmem.perBankWrBursts::8 8241 # Per bank write bursts -system.physmem.perBankWrBursts::9 7447 # Per bank write bursts -system.physmem.perBankWrBursts::10 7887 # Per bank write bursts -system.physmem.perBankWrBursts::11 7738 # Per bank write bursts -system.physmem.perBankWrBursts::12 8187 # Per bank write bursts -system.physmem.perBankWrBursts::13 8962 # Per bank write bursts -system.physmem.perBankWrBursts::14 8876 # Per bank write bursts -system.physmem.perBankWrBursts::15 8644 # Per bank write bursts +system.physmem.perBankRdBursts::7 24501 # Per bank write bursts +system.physmem.perBankRdBursts::8 25169 # Per bank write bursts +system.physmem.perBankRdBursts::9 24770 # Per bank write bursts +system.physmem.perBankRdBursts::10 25259 # Per bank write bursts +system.physmem.perBankRdBursts::11 24898 # Per bank write bursts +system.physmem.perBankRdBursts::12 24500 # Per bank write bursts +system.physmem.perBankRdBursts::13 25360 # Per bank write bursts +system.physmem.perBankRdBursts::14 25653 # Per bank write bursts +system.physmem.perBankRdBursts::15 25359 # Per bank write bursts +system.physmem.perBankWrBursts::0 7624 # Per bank write bursts +system.physmem.perBankWrBursts::1 7642 # Per bank write bursts +system.physmem.perBankWrBursts::2 7864 # Per bank write bursts +system.physmem.perBankWrBursts::3 7542 # Per bank write bursts +system.physmem.perBankWrBursts::4 7123 # Per bank write bursts +system.physmem.perBankWrBursts::5 6988 # Per bank write bursts +system.physmem.perBankWrBursts::6 6319 # Per bank write bursts +system.physmem.perBankWrBursts::7 6328 # Per bank write bursts +system.physmem.perBankWrBursts::8 7314 # Per bank write bursts +system.physmem.perBankWrBursts::9 6525 # Per bank write bursts +system.physmem.perBankWrBursts::10 7109 # Per bank write bursts +system.physmem.perBankWrBursts::11 6927 # Per bank write bursts +system.physmem.perBankWrBursts::12 7069 # Per bank write bursts +system.physmem.perBankWrBursts::13 7821 # Per bank write bursts +system.physmem.perBankWrBursts::14 7867 # Per bank write bursts +system.physmem.perBankWrBursts::15 7675 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 1922401791500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 1922385313500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401737 # Read request sizes (log2) +system.physmem.readPktSize::6 401684 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157245 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115767 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401554 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,189 +148,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 39 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 514.603333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.690032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.700723 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15764 24.50% 24.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11265 17.51% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5118 7.96% 49.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3016 4.69% 54.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2317 3.60% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1789 2.78% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1464 2.28% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1374 2.14% 65.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22229 34.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64336 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5099 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.750735 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2955.508201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5096 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads -system.physmem.totQLat 2057087750 # Total ticks spent queuing -system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5099 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5099 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.697980 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.062005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.025558 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4477 87.80% 87.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 19 0.37% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 190 3.73% 91.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 14 0.27% 92.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 27 0.53% 92.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 1.04% 93.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.27% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.06% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.12% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.06% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 8 0.16% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.04% 94.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 10 0.20% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.08% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 16 0.31% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 21 0.41% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 18 0.35% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 148 2.90% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.24% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.10% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 4 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 5 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 5 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5099 # Writes before turning the bus around for reads +system.physmem.totQLat 2147063750 # Total ticks spent queuing +system.physmem.totMemAccLat 9676463750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5346.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24096.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing -system.physmem.readRowHits 360176 # Number of row buffer hits during reads -system.physmem.writeRowHits 107764 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes -system.physmem.avgGap 3439112.16 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.677845 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states -system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states +system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing +system.physmem.readRowHits 359411 # Number of row buffer hits during reads +system.physmem.writeRowHits 93558 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes +system.physmem.avgGap 3715106.00 # Average gap between requests +system.physmem.pageHitRate 87.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 236030760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128786625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1564680000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 372146400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64059295815 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1097244171000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289166540360 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.604667 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1825128497250 # Time in different power states +system.physmem_0.memoryStateTime::REF 64192960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33072782750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.732006 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states -system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states +system.physmem_1.actEnergy 250349400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136599375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567550400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 377829360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125561429760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65774789190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1095739352250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289407899735 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.730219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1822618194250 # Time in different power states +system.physmem_1.memoryStateTime::REF 64192960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35583085750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9063642 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9066440 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6355525 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6357400 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15419167 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15423840 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974414 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973902 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979424 # ITB accesses +system.cpu.itb.fetch_accesses 4978899 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,34 +349,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3844827327 # number of cpu cycles simulated +system.cpu.numCycles 3844794365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56174594 # Number of instructions committed -system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483106 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls -system.cpu.num_int_insts 52047018 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read -system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15471782 # number of memory refs -system.cpu.num_load_insts 9100493 # Number of load instructions -system.cpu.num_store_insts 6371289 # Number of store instructions -system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles -system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles -system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.933046 # Percentage of idle cycles -system.cpu.Branches 8421188 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.committedInsts 56195121 # Number of instructions committed +system.cpu.committedOps 56195121 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066883 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1483708 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469750 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066883 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71341331 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530727 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15476411 # number of memory refs +system.cpu.num_load_insts 9103258 # Number of load instructions +system.cpu.num_store_insts 6373153 # Number of store instructions +system.cpu.num_idle_cycles 3587818415.000134 # Number of idle cycles +system.cpu.num_busy_cycles 256975949.999866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066837 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933163 # Percentage of idle cycles +system.cpu.Branches 8423975 # Number of branches fetched +system.cpu.op_class::No_OpClass 3201032 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36240615 64.48% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61007 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction @@ -396,34 +402,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9330336 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6379227 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953006 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56186427 # Class of executed instruction +system.cpu.op_class::total 56206940 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 211964 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74896 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183176 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73529 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73529 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149121 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858096797000 96.66% 96.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 92317000 0.00% 96.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 743733500 0.04% 96.70% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63463601000 3.30% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922396448500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692253 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814086 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -459,10 +465,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175955 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -471,28 +477,28 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192894 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.callpal::total 192899 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2093 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323509 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1391374 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46413360000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5233781000 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870749305500 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4175 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1390740 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978175 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14051600 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391252 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099968 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978175 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -500,72 +506,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits -system.cpu.dcache.overall_hits::total 13664105 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses -system.cpu.dcache.overall_misses::total 1374617 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63162665 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63162665 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7816092 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7816092 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853262 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853262 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13669354 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13669354 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13669354 # number of overall hits +system.cpu.dcache.overall_hits::total 13669354 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069466 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069466 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304560 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304560 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374026 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374026 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374026 # number of overall misses +system.cpu.dcache.overall_misses::total 1374026 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30729736500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30729736500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11677039000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11677039000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228891000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228891000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42406775500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42406775500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42406775500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42406775500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885558 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157822 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157822 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043380 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043380 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043380 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043380 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120360 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28733.719913 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28733.719913 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38340.684923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38340.684923 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.660404 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.660404 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30863.153608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30863.153608 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30863.153608 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -574,120 +580,120 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks -system.cpu.dcache.writebacks::total 835634 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 835293 # number of writebacks +system.cpu.dcache.writebacks::total 835293 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069466 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069466 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304560 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374026 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374026 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374026 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374026 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 206747.330447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 206747.330447 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 209890.673575 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 209890.673575 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 208576.839566 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29660270500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29660270500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11372479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11372479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 211647000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 211647000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41032749500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 41032749500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41032749500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 41032749500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1450110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1450110500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2049565500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2049565500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3499676000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3499676000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120360 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120360 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27733.719913 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27733.719913 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37340.684923 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37340.684923 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12273.660404 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12273.660404 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29863.153608 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29863.153608 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209251.154401 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209251.154401 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212390.207254 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212390.207254 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 211078.166466 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 211078.166466 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928205 # number of replacements -system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928306 # number of replacements +system.cpu.icache.tags.tagsinuse 508.094938 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55277964 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928817 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.514376 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41861098500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.094938 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992373 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992373 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits -system.cpu.icache.overall_hits::total 55257552 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses -system.cpu.icache.overall_misses::total 928876 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57135918 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57135918 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55277964 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55277964 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55277964 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55277964 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55277964 # number of overall hits +system.cpu.icache.overall_hits::total 55277964 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928977 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928977 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928977 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928977 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928977 # number of overall misses +system.cpu.icache.overall_misses::total 928977 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13003041000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13003041000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13003041000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13003041000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13003041000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13003041000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56206941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56206941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56206941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56206941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56206941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56206941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016528 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016528 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016528 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016528 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016528 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016528 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13997.161394 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13997.161394 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13997.161394 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13997.161394 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13997.161394 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,135 +702,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928977 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928977 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928977 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928977 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928977 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928977 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12074064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12074064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12074064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12074064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12074064000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12074064000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016528 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016528 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016528 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12997.161394 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12997.161394 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12997.161394 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12997.161394 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12997.161394 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12997.161394 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336253 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336199 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65288.878091 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3929497 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401361 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.790431 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7193890000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55462.992848 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4782.516669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5043.368573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.846298 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072975 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.076956 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996229 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1014 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4931 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55807 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 37808402 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37808402 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 835293 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835293 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187720 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 915695 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 915695 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814736 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814736 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915695 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002456 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918151 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915695 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002456 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918151 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses -system.cpu.l2cache.overall_misses::total 402112 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928856 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2016391 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 835634 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116823 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116823 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13262 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13262 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13262 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388797 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402059 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13262 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388797 # number of overall misses +system.cpu.l2cache.overall_misses::total 402059 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 220000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8944042500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8944042500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1062602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1062602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19687124500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19687124500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1062602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28631167000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29693769000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1062602000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28631167000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29693769000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 835293 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835293 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304352 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304352 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928856 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391887 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320743 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928856 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391887 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320743 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304543 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304543 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 928957 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 928957 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086710 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086710 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928957 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391253 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320210 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928957 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391253 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320210 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383953 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383953 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173269 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173269 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80059.626815 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72857.294351 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16999.846154 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16999.846154 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73858.624913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383601 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383601 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014276 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014276 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250273 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250273 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014276 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279458 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173286 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014276 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279458 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173286 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16923.076923 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16923.076923 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76560.630184 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76560.630184 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80123.812396 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80123.812396 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72386.053446 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72386.053446 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73854.257708 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80123.812396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73640.401032 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73854.257708 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,114 +845,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks -system.cpu.l2cache.writebacks::total 74181 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74255 # number of writebacks +system.cpu.l2cache.writebacks::total 74255 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 280 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 280 # number of CleanEvict MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116823 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116823 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13262 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13262 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13262 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388797 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13262 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388797 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402059 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 364500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 364500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7775812500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7775812500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 929982000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 929982000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16967384500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16967384500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 929982000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24743197000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25673179000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 929982000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24743197000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25673179000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1363485500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1363485500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1938590500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1938590500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3302076000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3302076000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 192747.330447 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 192747.330447 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 196890.673575 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 196890.673575 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 195158.866104 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383601 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014276 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250273 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250273 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173286 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014276 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173286 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 28038.461538 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 28038.461538 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66560.630184 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66560.630184 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70123.812396 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70123.812396 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62386.053446 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62386.053446 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70123.812396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63640.401032 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63854.257708 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 196751.154401 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 196751.154401 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200890.207254 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 200890.207254 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 199160.193004 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 199160.193004 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022774 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 951075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1744381 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41937 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3214755 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012990 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113233 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304543 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304543 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 928977 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2786015 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205333 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6991348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59453248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142553556 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202006804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419801 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5075497 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.082676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.275393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3172994 98.70% 98.70% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41761 1.30% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4655873 91.73% 91.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 419624 8.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3214755 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5075497 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3168054500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1393465500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098643000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -957,8 +980,7 @@ system.disk2.dma_write_txs 1 # Nu system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 9650 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.trans_dist::WriteResp 51202 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -1013,23 +1035,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216066756 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342844 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756461860000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342844 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083928 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083928 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1037,49 +1059,49 @@ system.iocache.tags.tag_accesses 375525 # Nu system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21632883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21632883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4907244873 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4907244873 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21632883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21632883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21632883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21632883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125045.566474 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125045.566474 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118098.885084 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118098.885084 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125045.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125045.566474 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1087,79 +1109,81 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12982883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12982883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2829644873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2829644873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12982883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12982883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12982883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12982883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75045.566474 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68098.885084 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68098.885084 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75045.566474 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75045.566474 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292358 # Transaction distribution -system.membus.trans_dist::ReadResp 292358 # Transaction distribution +system.membus.trans_dist::ReadReq 6930 # Transaction distribution +system.membus.trans_dist::ReadResp 292339 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115693 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::Writeback 115767 # Transaction distribution +system.membus.trans_dist::CleanEvict 261512 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116738 # Transaction distribution -system.membus.trans_dist::ReadExResp 116738 # Transaction distribution +system.membus.trans_dist::ReadExReq 116704 # Transaction distribution +system.membus.trans_dist::ReadExResp 116704 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285409 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139625 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172785 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1297602 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30503700 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33161428 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 576169 # Request fanout histogram +system.membus.snoop_fanout::samples 837831 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 576169 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837831 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 576169 # Request fanout histogram -system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837831 # Request fanout histogram +system.membus.reqLayer0.occupancy 30056000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1285352189 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143948368 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72076390 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index a436908c3..52cc263b3 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,53 +4,53 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1057273 # Simulator instruction rate (inst/s) -host_op_rate 1287060 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20615299474 # Simulator tick rate (ticks/s) -host_mem_usage 562992 # Number of bytes of host memory used -host_seconds 135.04 # Real time elapsed on the host +host_inst_rate 1269332 # Simulator instruction rate (inst/s) +host_op_rate 1545209 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24750158617 # Simulator tick rate (ticks/s) +host_mem_usage 625572 # Number of bytes of host memory used +host_seconds 112.48 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory +system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -348,8 +348,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks -system.cpu.dcache.writebacks::total 682059 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks +system.cpu.dcache.writebacks::total 682040 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1699214 # number of replacements system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use @@ -401,22 +401,22 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 110026 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 109913 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id @@ -424,67 +424,73 @@ system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 147776 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163344 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181651 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses -system.cpu.l2cache.overall_misses::total 181764 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses +system.cpu.l2cache.overall_misses::total 181651 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses @@ -497,25 +503,27 @@ system.cpu.l2cache.overall_accesses::cpu.data 819930 system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,46 +532,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks -system.cpu.l2cache.writebacks::total 101897 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks +system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 22778 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -630,24 +640,24 @@ system.iocache.tags.tag_accesses 328176 # Nu system.iocache.tags.data_accesses 328176 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses system.iocache.overall_misses::total 240 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -663,46 +673,48 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74227 # Transaction distribution -system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::ReadReq 40087 # Transaction distribution +system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138087 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 146085 # Transaction distribution -system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.trans_dist::ReadExReq 145997 # Transaction distribution +system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 426678 # Request fanout histogram +system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426678 # Request fanout histogram +system.membus.snoop_fanout::total 434821 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 8cc51b925..eec67c0c4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,70 +4,66 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 935329 # Simulator instruction rate (inst/s) -host_op_rate 1139685 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17855077822 # Simulator tick rate (ticks/s) -host_mem_usage 572752 # Number of bytes of host memory used -host_seconds 156.98 # Real time elapsed on the host +host_inst_rate 1243628 # Simulator instruction rate (inst/s) +host_op_rate 1515342 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23740372608 # Simulator tick rate (ticks/s) +host_mem_usage 632596 # Number of bytes of host memory used +host_seconds 118.06 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1118628 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9439908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149524 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1084244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11793968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1118628 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149524 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1268152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8394176 # Number of bytes written to this memory +system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8411740 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25932 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193429 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131159 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135550 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 399097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3367914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4207781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 399097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53346 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 452444 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2994824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3001090 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2994824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 399097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3374166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7208872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -309,32 +305,32 @@ system.cpu0.dcache.tags.tag_accesses 74113887 # Nu system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690414 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690414 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798955 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798955 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145048 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145048 # number of overall hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145070 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295771 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295771 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668874 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668874 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769195 # number of overall misses -system.cpu0.dcache.overall_misses::total 769195 # number of overall misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses +system.cpu0.dcache.overall_misses::total 769173 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) @@ -351,18 +347,18 @@ system.cpu0.dcache.overall_accesses::cpu0.data 35914243 system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048348 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048348 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -371,8 +367,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511485 # number of writebacks -system.cpu0.dcache.writebacks::total 511485 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks +system.cpu0.dcache.writebacks::total 511204 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use @@ -429,123 +425,131 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252829 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16127.674334 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1809277 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 269026 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.725287 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252605 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8127.481443 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.302152 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.089300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4685.625756 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3313.175683 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.496062 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285988 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.202220 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984355 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16189 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5612 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7505 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2706 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988098 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39447877 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39447877 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7572 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065262 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 351770 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1427855 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511485 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511485 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94095 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94095 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7572 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065262 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 445865 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1521950 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7572 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065262 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 445865 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1521950 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 137 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44994 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128396 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173743 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 137 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 44994 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303824 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 349171 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 137 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 44994 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303824 # number of overall misses -system.cpu0.l2cache.overall_misses::total 349171 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7788 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3388 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480166 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601598 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511485 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511485 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7788 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3388 # number of demand (read+write) accesses +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871121 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7788 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3388 # number of overall (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871121 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040437 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040526 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267399 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108481 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650883 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650883 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040437 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040526 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.405267 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186611 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027735 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040437 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040526 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.405267 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186611 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,41 +558,44 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 193152 # number of writebacks -system.cpu0.l2cache.writebacks::total 193152 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks +system.cpu0.l2cache.writebacks::total 192999 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651838 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44692 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220081 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500273 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80905668 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152081412 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 327909 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2731172 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.090112 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.286342 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 327822 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2485061 90.99% 90.99% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 246111 9.01% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2731172 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -804,32 +811,32 @@ system.cpu1.dcache.tags.tag_accesses 39751979 # Nu system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397479 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397479 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72442 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72442 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256173 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256173 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306272 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306272 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306291 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92483 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92483 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22537 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22537 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229113 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229113 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259832 # number of overall misses -system.cpu1.dcache.overall_misses::total 259832 # number of overall misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses +system.cpu1.dcache.overall_misses::total 259813 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) @@ -846,18 +853,18 @@ system.cpu1.dcache.overall_accesses::cpu1.data 19566104 system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237284 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,8 +873,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120843 # number of writebacks -system.cpu1.dcache.writebacks::total 120843 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks +system.cpu1.dcache.writebacks::total 120813 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use @@ -923,121 +930,129 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48543 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15314.912528 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 717091 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63380 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.314153 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48465 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8302.426392 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.123905 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.034953 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3306.071742 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3701.255535 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.506740 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000191 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201787 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225907 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934748 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14808 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9377 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4900 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15213000 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15213000 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3125 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1708 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510060 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99394 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614287 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120843 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120843 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19811 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19811 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3125 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1708 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510060 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119205 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634098 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3125 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1708 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510060 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119205 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634098 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13825 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73273 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87709 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28859 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28859 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43805 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43805 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13825 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117078 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131514 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13825 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117078 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131514 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3469 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 701996 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120843 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120843 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22537 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22537 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634121 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131449 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3469 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 765612 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3469 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 765612 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135190 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026389 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424360 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.124942 # miss rate for ReadReq accesses +system.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688585 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688585 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135190 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026389 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495499 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171776 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099164 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135190 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026389 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495499 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171776 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1046,46 +1061,48 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks -system.cpu1.l2cache.writebacks::total 32966 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks +system.cpu1.l2cache.writebacks::total 32917 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120843 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51404 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707677 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774495 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22875246 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56441982 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 568922 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1446930 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.351508 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.477442 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 568500 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 938322 64.85% 64.85% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 508608 35.15% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1446930 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution -system.iobus.trans_dist::WriteResp 23195 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59419 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1152,24 +1169,24 @@ system.iocache.tags.tag_accesses 328284 # Nu system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -1185,183 +1202,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107655 # number of replacements -system.l2c.tags.tagsinuse 62149.484460 # Cycle average of tags in use -system.l2c.tags.total_refs 208536 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168097 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.240569 # Average number of references to valid blocks. +system.l2c.tags.replacements 106825 # number of replacements +system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use +system.l2c.tags.total_refs 288805 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48591.950970 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.942995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7375.890834 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3824.198641 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.861600 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1621.181926 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 731.426698 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741454 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.112547 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058353 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.024737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011161 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948326 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1845 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13049 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45441 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4909092 # Number of tag accesses -system.l2c.tags.data_accesses 4909092 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 78 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 76273 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11499 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11319 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127403 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 226118 # number of Writeback hits -system.l2c.Writeback_hits::total 226118 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 498 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 562 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 63 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 75 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 14019 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3098 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17117 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 90292 # number of demand (read+write) hits +system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5581048 # Number of tag accesses +system.l2c.tags.data_accesses 5581048 # Number of data accesses +system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits +system.l2c.Writeback_hits::total 225916 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11499 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14417 # number of demand (read+write) hits -system.l2c.demand_hits::total 144520 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28077 # number of overall hits -system.l2c.overall_hits::cpu0.data 90292 # number of overall hits +system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits +system.l2c.demand_hits::total 145090 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits +system.l2c.overall_hits::cpu0.data 90500 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11499 # number of overall hits -system.l2c.overall_hits::cpu1.data 14417 # number of overall hits -system.l2c.overall_hits::total 144520 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16917 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2326 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1158 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31739 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 10006 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13279 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1176 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1930 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136759 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152578 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses +system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits +system.l2c.overall_hits::cpu1.data 14467 # number of overall hits +system.l2c.overall_hits::total 145090 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16917 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2326 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16977 # number of demand (read+write) misses -system.l2c.demand_misses::total 184317 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses +system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses +system.l2c.demand_misses::total 183538 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16917 # number of overall misses -system.l2c.overall_misses::cpu0.data 148086 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2326 # number of overall misses -system.l2c.overall_misses::cpu1.data 16977 # number of overall misses -system.l2c.overall_misses::total 184317 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 44994 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13825 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12477 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 159142 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 226118 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 226118 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10504 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3337 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13841 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 817 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150778 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18917 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169695 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 44994 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238378 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13825 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31394 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328837 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 44994 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238378 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13825 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31394 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328837 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375983 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129304 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.168246 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.092811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199438 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952589 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980821 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.959396 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.922889 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.989899 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.962594 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907022 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836232 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899131 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375983 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.621223 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.168246 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.540772 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.560512 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375983 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.621223 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.168246 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.540772 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.560512 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses +system.l2c.overall_misses::cpu0.data 147794 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses +system.l2c.overall_misses::cpu1.data 16974 # number of overall misses +system.l2c.overall_misses::total 183538 # number of overall misses +system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150664 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18923 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169587 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1370,49 +1379,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94969 # number of writebacks -system.l2c.writebacks::total 94969 # number of writebacks +system.l2c.writebacks::writebacks 96236 # number of writebacks +system.l2c.writebacks::total 96236 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75988 # Transaction distribution -system.membus.trans_dist::ReadResp 75988 # Transaction distribution +system.membus.trans_dist::ReadReq 43997 # Transaction distribution +system.membus.trans_dist::ReadResp 75378 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::Writeback 131159 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::Writeback 132426 # Transaction distribution +system.membus.trans_dist::CleanEvict 15436 # Transaction distribution system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15595 # Transaction distribution -system.membus.trans_dist::ReadExReq 196283 # Transaction distribution -system.membus.trans_dist::ReadExResp 152192 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution +system.membus.trans_dist::ReadExReq 196055 # Transaction distribution +system.membus.trans_dist::ReadExResp 151973 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652086 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882612 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 788323 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 897717 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17906316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18096098 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22746722 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 571767 # Request fanout histogram +system.membus.snoop_fanout::samples 587643 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 571767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 587643 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 571767 # Request fanout histogram +system.membus.snoop_fanout::total 587643 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1444,33 +1455,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305452 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305452 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 226118 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60537 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40981 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101518 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1118722 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410600 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1529322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34707388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425906 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45133294 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 914196 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039900 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195723 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 877720 96.01% 96.01% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 3.99% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 914196 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 383222d5f..19a0730a6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,53 +4,53 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1032026 # Simulator instruction rate (inst/s) -host_op_rate 1256326 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20123025378 # Simulator tick rate (ticks/s) -host_mem_usage 560940 # Number of bytes of host memory used -host_seconds 138.34 # Real time elapsed on the host +host_inst_rate 1280569 # Simulator instruction rate (inst/s) +host_op_rate 1558887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24969250003 # Simulator tick rate (ticks/s) +host_mem_usage 621096 # Number of bytes of host memory used +host_seconds 111.49 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory +system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -348,8 +348,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks -system.cpu.dcache.writebacks::total 682059 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks +system.cpu.dcache.writebacks::total 682040 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1699214 # number of replacements system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use @@ -401,22 +401,22 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 110026 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 109913 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4564556 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.054294 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id @@ -424,67 +424,73 @@ system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 40896687 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40896687 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 147776 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 163344 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181651 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses -system.cpu.l2cache.overall_misses::total 181764 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses +system.cpu.l2cache.overall_misses::total 181651 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses @@ -497,25 +503,27 @@ system.cpu.l2cache.overall_accesses::cpu.data 819930 system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,46 +532,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks -system.cpu.l2cache.writebacks::total 101897 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks +system.cpu.l2cache.writebacks::total 101949 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1836576 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116722 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2582000 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7754152 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 5172848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012407 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.110693 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5108669 98.76% 98.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 64179 1.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5172848 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 22778 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -630,24 +640,24 @@ system.iocache.tags.tag_accesses 328176 # Nu system.iocache.tags.data_accesses 328176 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses system.iocache.overall_misses::total 240 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -663,46 +673,48 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74227 # Transaction distribution -system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::ReadReq 40087 # Transaction distribution +system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138087 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::Writeback 138139 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 146085 # Transaction distribution -system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.trans_dist::ReadExReq 145997 # Transaction distribution +system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 426678 # Request fanout histogram +system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426678 # Request fanout histogram +system.membus.snoop_fanout::total 434821 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 81dc58761..b0093ef47 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868578 # Number of seconds simulated -sim_ticks 2868577613500 # Number of ticks simulated -final_tick 2868577613500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868721 # Number of seconds simulated +sim_ticks 2868720569000 # Number of ticks simulated +final_tick 2868720569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 558438 # Simulator instruction rate (inst/s) -host_op_rate 675477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12195118142 # Simulator tick rate (ticks/s) -host_mem_usage 590596 # Number of bytes of host memory used -host_seconds 235.22 # Real time elapsed on the host -sim_insts 131357672 # Number of instructions simulated -sim_ops 158887964 # Number of ops (including micro ops) simulated +host_inst_rate 718623 # Simulator instruction rate (inst/s) +host_op_rate 869205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15661016649 # Simulator tick rate (ticks/s) +host_mem_usage 645712 # Number of bytes of host memory used +host_seconds 183.18 # Real time elapsed on the host +sim_insts 131634295 # Number of instructions simulated +sim_ops 159217322 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1167908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1250980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8365696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1149540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1292388 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8590592 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 137236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 508432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 356544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 585104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11788332 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1167908 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 137236 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1305144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8293056 # Number of bytes written to this memory +system.physmem.bytes_read::total 12171052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1149540 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1301432 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8736704 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8310620 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8754268 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26702 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 130714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26415 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20713 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134228 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7964 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5571 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193340 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129579 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199320 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136511 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133970 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 140902 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 407138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 436098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2916322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 400715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 450510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2994573 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 177242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 124293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 139413 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4109469 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 407138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 454979 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2890999 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4242676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 400715 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 453663 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3045505 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2897122 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2890999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3051628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3045505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 407138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 442207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2916322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 400715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 456619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2994573 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 177256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 124293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 139413 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7006592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193340 # Number of read requests accepted -system.physmem.writeReqs 170194 # Number of write requests accepted -system.physmem.readBursts 193340 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 170194 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12365312 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue -system.physmem.bytesWritten 9398080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11788332 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10628956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23320 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12970 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11741 # Per bank write bursts -system.physmem.perBankRdBursts::1 11572 # Per bank write bursts -system.physmem.perBankRdBursts::2 11914 # Per bank write bursts -system.physmem.perBankRdBursts::3 12194 # Per bank write bursts -system.physmem.perBankRdBursts::4 20279 # Per bank write bursts -system.physmem.perBankRdBursts::5 11715 # Per bank write bursts -system.physmem.perBankRdBursts::6 11292 # Per bank write bursts -system.physmem.perBankRdBursts::7 11716 # Per bank write bursts -system.physmem.perBankRdBursts::8 11966 # Per bank write bursts -system.physmem.perBankRdBursts::9 12328 # Per bank write bursts -system.physmem.perBankRdBursts::10 11336 # Per bank write bursts -system.physmem.perBankRdBursts::11 10554 # Per bank write bursts -system.physmem.perBankRdBursts::12 10992 # Per bank write bursts -system.physmem.perBankRdBursts::13 11462 # Per bank write bursts -system.physmem.perBankRdBursts::14 10907 # Per bank write bursts -system.physmem.perBankRdBursts::15 11240 # Per bank write bursts -system.physmem.perBankWrBursts::0 9545 # Per bank write bursts -system.physmem.perBankWrBursts::1 9662 # Per bank write bursts -system.physmem.perBankWrBursts::2 9792 # Per bank write bursts -system.physmem.perBankWrBursts::3 9578 # Per bank write bursts -system.physmem.perBankWrBursts::4 8974 # Per bank write bursts -system.physmem.perBankWrBursts::5 9217 # Per bank write bursts -system.physmem.perBankWrBursts::6 9112 # Per bank write bursts -system.physmem.perBankWrBursts::7 9138 # Per bank write bursts -system.physmem.perBankWrBursts::8 9280 # Per bank write bursts -system.physmem.perBankWrBursts::9 9864 # Per bank write bursts -system.physmem.perBankWrBursts::10 9143 # Per bank write bursts -system.physmem.perBankWrBursts::11 8671 # Per bank write bursts -system.physmem.perBankWrBursts::12 8940 # Per bank write bursts -system.physmem.perBankWrBursts::13 8704 # Per bank write bursts -system.physmem.perBankWrBursts::14 8686 # Per bank write bursts -system.physmem.perBankWrBursts::15 8539 # Per bank write bursts +system.physmem.bw_total::total 7294304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199320 # Number of read requests accepted +system.physmem.writeReqs 140902 # Number of write requests accepted +system.physmem.readBursts 199320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12746944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 8766656 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12171052 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8754268 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49030 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12070 # Per bank write bursts +system.physmem.perBankRdBursts::1 11831 # Per bank write bursts +system.physmem.perBankRdBursts::2 12274 # Per bank write bursts +system.physmem.perBankRdBursts::3 12388 # Per bank write bursts +system.physmem.perBankRdBursts::4 20676 # Per bank write bursts +system.physmem.perBankRdBursts::5 12594 # Per bank write bursts +system.physmem.perBankRdBursts::6 12033 # Per bank write bursts +system.physmem.perBankRdBursts::7 12197 # Per bank write bursts +system.physmem.perBankRdBursts::8 12580 # Per bank write bursts +system.physmem.perBankRdBursts::9 12376 # Per bank write bursts +system.physmem.perBankRdBursts::10 11749 # Per bank write bursts +system.physmem.perBankRdBursts::11 11049 # Per bank write bursts +system.physmem.perBankRdBursts::12 11595 # Per bank write bursts +system.physmem.perBankRdBursts::13 11646 # Per bank write bursts +system.physmem.perBankRdBursts::14 10943 # Per bank write bursts +system.physmem.perBankRdBursts::15 11170 # Per bank write bursts +system.physmem.perBankWrBursts::0 8793 # Per bank write bursts +system.physmem.perBankWrBursts::1 8761 # Per bank write bursts +system.physmem.perBankWrBursts::2 9161 # Per bank write bursts +system.physmem.perBankWrBursts::3 8988 # Per bank write bursts +system.physmem.perBankWrBursts::4 8395 # Per bank write bursts +system.physmem.perBankWrBursts::5 9123 # Per bank write bursts +system.physmem.perBankWrBursts::6 8851 # Per bank write bursts +system.physmem.perBankWrBursts::7 8630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9078 # Per bank write bursts +system.physmem.perBankWrBursts::9 8912 # Per bank write bursts +system.physmem.perBankWrBursts::10 8485 # Per bank write bursts +system.physmem.perBankWrBursts::11 8089 # Per bank write bursts +system.physmem.perBankWrBursts::12 8403 # Per bank write bursts +system.physmem.perBankWrBursts::13 8019 # Per bank write bursts +system.physmem.perBankWrBursts::14 7666 # Per bank write bursts +system.physmem.perBankWrBursts::15 7625 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 53 # Number of times write queue was full causing retry -system.physmem.totGap 2868577154000 # Total gap between requests +system.physmem.numWrRetry 43 # Number of times write queue was full causing retry +system.physmem.totGap 2868720108500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 183581 # Read request sizes (log2) +system.physmem.readPktSize::6 189561 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 165803 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 135144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 9961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136511 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -184,163 +184,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 259.284788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.169379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.901486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42814 51.01% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16839 20.06% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5671 6.76% 77.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3554 4.23% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2350 2.80% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1452 1.73% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1048 1.25% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 956 1.14% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9252 11.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83936 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.152937 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.980980 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6006 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6009 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6009 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.437510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.815074 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 42.361816 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5653 94.08% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 88 1.46% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 21 0.35% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 11 0.18% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 30 0.50% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 35 0.58% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 32 0.53% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 15 0.25% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 11 0.18% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 9 0.15% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.37% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 19 0.32% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 8 0.13% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.03% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 4 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.05% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.05% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.08% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 5 0.08% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.10% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.10% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 4 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6009 # Writes before turning the bus around for reads -system.physmem.totQLat 4585121898 # Total ticks spent queuing -system.physmem.totMemAccLat 8207771898 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 966040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23731.53 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 131 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.097791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.224347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.120448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46751 52.61% 52.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18086 20.35% 72.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6032 6.79% 79.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3695 4.16% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2426 2.73% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1553 1.75% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 926 1.04% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8346 9.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88863 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6835 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.139722 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.203282 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6833 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6835 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6835 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.040819 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.588322 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.942463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5790 84.71% 84.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 288 4.21% 88.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 181 2.65% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 61 0.89% 92.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 66 0.97% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 161 2.36% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.32% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.15% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.15% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.13% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.13% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.38% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.12% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6835 # Writes before turning the bus around for reads +system.physmem.totQLat 4713712824 # Total ticks spent queuing +system.physmem.totMemAccLat 8448169074 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 995855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23666.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42481.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.11 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42416.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 161661 # Number of row buffer hits during reads -system.physmem.writeRowHits 94455 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.31 # Row buffer hit rate for writes -system.physmem.avgGap 7890808.44 # Average gap between requests -system.physmem.pageHitRate 75.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 329026320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 179528250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 798891600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486116640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84057386715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647408374250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920620456175 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.538978 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740481725360 # Time in different power states -system.physmem_0.memoryStateTime::REF 95787900000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.14 # Average write queue length when enqueuing +system.physmem.readRowHits 166377 # Number of row buffer hits during reads +system.physmem.writeRowHits 80909 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.06 # Row buffer hit rate for writes +system.physmem.avgGap 8431906.54 # Average gap between requests +system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 348886440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 190364625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 827283600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 458148960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84523956795 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647087865500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920807300960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.569582 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739939393002 # Time in different power states +system.physmem_0.memoryStateTime::REF 95792840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32307893640 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32988240498 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 305529840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 166707750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 708123000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 465438960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82818901260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648494765000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920320598210 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.434445 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742293590423 # Time in different power states -system.physmem_1.memoryStateTime::REF 95787900000 # Time in different power states +system.physmem_1.actEnergy 322917840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176195250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 726242400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 429474960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83768933655 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647750166500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920544725645 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478051 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2741046257852 # Time in different power states +system.physmem_1.memoryStateTime::REF 95792840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30490063327 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31880394648 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -396,58 +389,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7618 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7618 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1341 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6277 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7618 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7618 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7618 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6224 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9157.575514 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8041.236075 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5531.388532 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6077 97.64% 97.64% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 137 2.20% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6224 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4922 79.08% 79.08% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1302 20.92% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6224 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7618 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 7828 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7828 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1457 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6371 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7828 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7828 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7828 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9317.145265 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5859.670820 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6278 97.58% 97.58% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 144 2.24% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5016 77.96% 77.96% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1418 22.04% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6434 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7828 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7618 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6224 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6434 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6224 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13842 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6434 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14262 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25125547 # DTB read hits -system.cpu0.dtb.read_misses 6527 # DTB read misses -system.cpu0.dtb.write_hits 18731781 # DTB write hits -system.cpu0.dtb.write_misses 1091 # DTB write misses +system.cpu0.dtb.read_hits 22804186 # DTB read hits +system.cpu0.dtb.read_misses 6713 # DTB read misses +system.cpu0.dtb.write_hits 17553531 # DTB write hits +system.cpu0.dtb.write_misses 1115 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1741 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1817 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25132074 # DTB read accesses -system.cpu0.dtb.write_accesses 18732872 # DTB write accesses +system.cpu0.dtb.read_accesses 22810899 # DTB read accesses +system.cpu0.dtb.write_accesses 17554646 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43857328 # DTB hits -system.cpu0.dtb.misses 7618 # DTB misses -system.cpu0.dtb.accesses 43864946 # DTB accesses +system.cpu0.dtb.hits 40357717 # DTB hits +system.cpu0.dtb.misses 7828 # DTB misses +system.cpu0.dtb.accesses 40365545 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,20 +477,21 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9422.169811 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8126.335555 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5925.919906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 980 42.02% 42.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1299 55.70% 97.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.93% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9538.524469 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5751.182189 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 887 38.04% 38.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1322 56.69% 94.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 85 3.64% 98.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 28 1.20% 99.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.30% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated @@ -509,7 +502,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 118901491 # ITB inst hits +system.cpu0.itb.inst_hits 108563333 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -526,172 +519,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 118904839 # ITB inst accesses -system.cpu0.itb.hits 118901491 # DTB hits +system.cpu0.itb.inst_accesses 108566681 # ITB inst accesses +system.cpu0.itb.hits 108563333 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 118904839 # DTB accesses -system.cpu0.numCycles 5737155227 # number of cpu cycles simulated +system.cpu0.itb.accesses 108566681 # DTB accesses +system.cpu0.numCycles 5737441138 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 115236645 # Number of instructions committed -system.cpu0.committedOps 139243080 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123236123 # Number of integer alu accesses +system.cpu0.committedInsts 105480509 # Number of instructions committed +system.cpu0.committedOps 127164191 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 112285314 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12671679 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15683932 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123236123 # number of integer instructions +system.cpu0.num_func_calls 10414111 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14574473 # number of instructions that are conditional controls +system.cpu0.num_int_insts 112285314 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 226877119 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85629478 # number of times the integer registers were written +system.cpu0.num_int_register_reads 205015592 # number of times the integer registers were read +system.cpu0.num_int_register_writes 77505457 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 504430555 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52228186 # number of times the CC registers were written -system.cpu0.num_mem_refs 44991026 # number of memory refs -system.cpu0.num_load_insts 25375377 # Number of load instructions -system.cpu0.num_store_insts 19615649 # Number of store instructions -system.cpu0.num_idle_cycles 5465784255.910094 # Number of idle cycles -system.cpu0.num_busy_cycles 271370971.089905 # Number of busy cycles -system.cpu0.not_idle_fraction 0.047301 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.952699 # Percentage of idle cycles -system.cpu0.Branches 29094451 # Number of branches fetched +system.cpu0.num_cc_register_reads 459494635 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 48916829 # number of times the CC registers were written +system.cpu0.num_mem_refs 41493426 # number of memory refs +system.cpu0.num_load_insts 23055800 # Number of load instructions +system.cpu0.num_store_insts 18437626 # Number of store instructions +system.cpu0.num_idle_cycles 5489199817.904087 # Number of idle cycles +system.cpu0.num_busy_cycles 248241320.095913 # Number of busy cycles +system.cpu0.not_idle_fraction 0.043267 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.956733 # Percentage of idle cycles +system.cpu0.Branches 25703635 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97895605 68.46% 68.46% # Class of executed instruction -system.cpu0.op_class::IntMult 108367 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8067 0.01% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction -system.cpu0.op_class::MemRead 25375377 17.74% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19615649 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 88750967 68.09% 68.09% # Class of executed instruction +system.cpu0.op_class::IntMult 92819 0.07% 68.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8217 0.01% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction +system.cpu0.op_class::MemRead 23055800 17.69% 85.86% # Class of executed instruction +system.cpu0.op_class::MemWrite 18437626 14.14% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143005338 # Class of executed instruction +system.cpu0.op_class::total 130347702 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 691902 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.788529 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42987184 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 692414 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.083066 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1147014500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.788529 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964431 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.964431 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 694931 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.123274 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 39503506 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 695443 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.803370 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1135131000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.123274 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965085 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965085 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88350780 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88350780 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23864345 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23864345 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18002045 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18002045 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319294 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319294 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365178 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365178 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362317 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362317 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41866390 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41866390 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42185684 # number of overall hits -system.cpu0.dcache.overall_hits::total 42185684 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 396651 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396651 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 323350 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 323350 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127092 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127092 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21763 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21763 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19681 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19681 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 720001 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 720001 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847093 # number of overall misses -system.cpu0.dcache.overall_misses::total 847093 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5048891005 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5048891005 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5105410053 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5105410053 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330377500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330377500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 436252524 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 436252524 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1279500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1279500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10154301058 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10154301058 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10154301058 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10154301058 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24260996 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24260996 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18325395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18325395 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446386 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446386 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386941 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386941 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381998 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381998 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42586391 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42586391 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43032777 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43032777 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016349 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016349 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017645 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017645 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284713 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284713 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056244 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056244 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051521 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051521 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016907 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016907 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019685 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019685 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15789.114127 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15789.114127 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15180.696595 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15180.696595 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22166.176719 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22166.176719 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81393420 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81393420 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 21551304 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21551304 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16831338 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16831338 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318322 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318322 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365658 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365658 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362750 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362750 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 38382642 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 38382642 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 38700964 # number of overall hits +system.cpu0.dcache.overall_hits::total 38700964 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 398253 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 398253 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 324071 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 324071 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128299 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 128299 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21791 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21791 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19751 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19751 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 722324 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 722324 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 850623 # number of overall misses +system.cpu0.dcache.overall_misses::total 850623 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5056802000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5056802000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5106772500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5106772500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332740500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 332740500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 437773500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 437773500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1801500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1801500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10163574500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10163574500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10163574500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10163574500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21949557 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21949557 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17155409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17155409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446621 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446621 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387449 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387449 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382501 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382501 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 39104966 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 39104966 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39551587 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39551587 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018144 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.018144 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018890 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018890 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287266 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287266 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056242 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056242 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051636 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051636 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018471 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.018471 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021507 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.021507 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14103.176326 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11987.232875 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,147 +693,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 505765 # number of writebacks -system.cpu0.dcache.writebacks::total 505765 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25164 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25164 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15036 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15036 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25164 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25164 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25164 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25164 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371487 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 371487 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323350 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323350 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100065 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100065 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6727 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6727 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19681 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19681 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694837 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694837 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794902 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794902 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31775 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28452 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60227 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4098614569 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4098614569 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4609386947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4609386947 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1545410442 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1545410442 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97646500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 406311476 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 406311476 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1224000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1224000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8708001516 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8708001516 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10253411958 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10253411958 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6180823750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6180823750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4817819000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4817819000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10998642750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10998642750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015312 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017645 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017645 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224167 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224167 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017385 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017385 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051521 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051521 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016316 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016316 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018472 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018472 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11032.995957 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11032.995957 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14255.101120 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14255.101120 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15444.065777 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15444.065777 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14515.608741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14515.608741 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20644.859306 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20644.859306 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 507088 # number of writebacks +system.cpu0.dcache.writebacks::total 507088 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25317 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25317 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15125 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15125 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25317 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25317 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372936 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 372936 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324071 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324071 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100997 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100997 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6666 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6666 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19751 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 697007 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697007 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 798004 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 798004 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19686 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40796 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291277500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291277500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4782701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4782701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1606991500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1606991500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101428000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101428000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 418075500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 418075500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1748500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1748500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9073979000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9073979000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10680970500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10680970500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4433767500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4433767500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3394597500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3394597500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7828365000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7828365000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016991 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016991 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018890 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018890 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226136 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226136 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017205 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051636 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017824 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.017824 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020176 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020176 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12532.437847 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12532.437847 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12898.963593 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12898.963593 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194518.450039 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194518.450039 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169331.470547 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169331.470547 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182619.800920 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182619.800920 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1099684 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.454126 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117801286 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1100196 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.073000 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13491746250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454126 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998934 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998934 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1106064 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.455953 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 107456748 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1106576 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 97.107427 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13496677000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.455953 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998937 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998937 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 238903187 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 238903187 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 117801286 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117801286 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117801286 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117801286 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117801286 # number of overall hits -system.cpu0.icache.overall_hits::total 117801286 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1100205 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1100205 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1100205 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1100205 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1100205 # number of overall misses -system.cpu0.icache.overall_misses::total 1100205 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10864366523 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10864366523 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10864366523 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10864366523 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10864366523 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10864366523 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 118901491 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 118901491 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 118901491 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 118901491 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 118901491 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 118901491 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009253 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009253 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009253 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009253 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009253 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009253 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9874.856525 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9874.856525 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9874.856525 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9874.856525 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 218233251 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 218233251 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 107456748 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 107456748 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 107456748 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 107456748 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 107456748 # number of overall hits +system.cpu0.icache.overall_hits::total 107456748 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1106585 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1106585 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1106585 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1106585 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1106585 # number of overall misses +system.cpu0.icache.overall_misses::total 1106585 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10879255500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10879255500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10879255500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10879255500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10879255500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10879255500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 108563333 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 108563333 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 108563333 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 108563333 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 108563333 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 108563333 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010193 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010193 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010193 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010193 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010193 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010193 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9831.378069 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9831.378069 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9831.378069 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9831.378069 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,228 +842,239 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100205 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1100205 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100205 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1100205 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100205 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1100205 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106585 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1106585 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106585 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1106585 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106585 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1106585 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9757723477 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9757723477 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9757723477 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9757723477 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9757723477 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9757723477 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009253 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009253 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8869.004846 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8869.004846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8869.004846 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88911.272445 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88911.272445 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10325963000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10325963000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10325963000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10325963000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10325963000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10325963000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 800795500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010193 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010193 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010193 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9331.378069 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850277 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1850277 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850657 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1850711 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 45 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 235795 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 266928 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16114.496747 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1972101 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 283159 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.964642 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7721.313532 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.317590 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.113534 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4537.329831 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1964.577716 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1889.844545 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.471272 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276937 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119908 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.115347 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983551 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15100 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 368 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 474 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 237577 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266648 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16090.167348 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3241094 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282873 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.457771 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2844827650500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7840.907632 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.369036 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.138555 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4562.781634 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1957.525775 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1727.444715 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.478571 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278490 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119478 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.105435 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982066 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1088 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15130 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 359 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3254 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7638 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4052 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921631 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39669375 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39669375 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7528 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3363 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053127 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 384165 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1448183 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 505760 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 505760 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28149 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28149 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1715 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1715 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225012 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 225012 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7528 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3363 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1053127 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609177 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1673195 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7528 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3363 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1053127 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609177 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1673195 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 209 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47078 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 94114 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 141524 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26175 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26175 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44014 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44014 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 209 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 47078 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 138128 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 185538 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 209 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 47078 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 138128 # number of overall misses -system.cpu0.l2cache.overall_misses::total 185538 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4805250 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2807500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2358005477 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2765454494 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5131072721 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 482009840 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 482009840 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365934287 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365934287 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1185998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1185998 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1958932743 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1958932743 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4805250 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2807500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2358005477 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4724387237 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7090005464 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4805250 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2807500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2358005477 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4724387237 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7090005464 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7737 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3486 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100205 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 478279 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1589707 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 505760 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 505760 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54324 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54324 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19676 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19676 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269026 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269026 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7737 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3486 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1100205 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 747305 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1858733 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7737 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3486 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1100205 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 747305 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1858733 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035284 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042790 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.196776 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.089025 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.481831 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.481831 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.912838 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.912838 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7855 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3884 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066406 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923462 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 60109727 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 60109727 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8002 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3594 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 11596 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 507087 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 507087 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28350 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28350 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1666 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1666 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 228036 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 228036 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059903 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1059903 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 386161 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 386161 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8002 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3594 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1059903 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 614197 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1685696 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8002 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3594 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1059903 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 614197 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1685696 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 229 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 110 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26033 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26033 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18081 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18081 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41652 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 41652 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46682 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 46682 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94438 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94438 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 229 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 110 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 46682 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 136090 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 183111 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 229 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 110 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 46682 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 136090 # number of overall misses +system.cpu0.l2cache.overall_misses::total 183111 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5419000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2507000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 7926000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 480959500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 480959500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 368223000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 368223000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1666996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1666996 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1951085500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1951085500 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2317097000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2317097000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2767769000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2767769000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5419000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2507000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2317097000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4718854500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7043877500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5419000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2507000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2317097000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4718854500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7043877500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8231 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3704 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 11935 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 507087 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 507087 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54383 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54383 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19747 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19747 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269688 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269688 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1106585 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1106585 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480599 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480599 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8231 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3704 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1106585 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 750287 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1868807 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8231 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3704 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1106585 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 750287 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1868807 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029698 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.028404 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478697 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478697 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.915633 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.915633 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163605 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163605 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035284 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042790 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.184835 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.099820 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035284 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042790 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.184835 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.099820 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22825.203252 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 50087.205850 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29384.092632 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36255.848626 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18414.893601 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18414.893601 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20373.825901 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20373.825901 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 237199.600000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 237199.600000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44507.037374 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44507.037374 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22825.203252 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 50087.205850 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34202.965633 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 38213.225668 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22825.203252 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 50087.205850 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34202.965633 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 38213.225668 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154445 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154445 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.042186 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.042186 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196501 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196501 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029698 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042186 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.181384 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097983 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027822 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029698 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042186 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.181384 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097983 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22790.909091 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23380.530973 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18474.993278 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18474.993278 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20365.189978 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20365.189978 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 416749 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 416749 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46842.540574 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46842.540574 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49635.769676 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49635.769676 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29307.789237 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29307.789237 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22790.909091 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49635.769676 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34674.513190 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38467.800951 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23663.755459 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22790.909091 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49635.769676 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34674.513190 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38467.800951 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1079,192 +1083,207 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 194963 # number of writebacks -system.cpu0.l2cache.writebacks::total 194963 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 34 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1200 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1200 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1234 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1234 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1234 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1234 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 209 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 123 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47078 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94080 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 141490 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245498 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 245498 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26175 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26175 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42814 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 42814 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 209 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 123 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47078 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136894 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 184304 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 209 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 123 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47078 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136894 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245498 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 429802 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 195259 # number of writebacks +system.cpu0.l2cache.writebacks::total 195259 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1202 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1202 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 29 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1231 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1231 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1231 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1231 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 229 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 110 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8231 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 8231 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 244881 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 244881 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26033 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26033 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18081 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18081 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40450 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 40450 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46682 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46682 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94409 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94409 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 229 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 110 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46682 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 134859 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 181880 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 229 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 110 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46682 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 134859 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 244881 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 426761 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40797 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28452 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 30132 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19686 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69249 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2008000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2045556523 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2147080077 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4198090850 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13523341666 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13523341666 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 511152796 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 511152796 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258980524 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258980524 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 945498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 945498 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1561585422 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1561585422 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2008000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2045556523 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3708665499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5759676272 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2008000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2045556523 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3708665499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13523341666 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19283017938 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5926417500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6656671000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4604429000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4604429000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10530846500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11261100000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.196705 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089004 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 49818 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1847000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5892000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13903852400 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13903852400 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 522651500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 522651500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 269507500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 269507500 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1348996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1348996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1589383000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1589383000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2037005000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2037005000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2197124000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2197124000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1847000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2037005000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3786507000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5829404000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4045000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1847000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2037005000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3786507000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13903852400 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19733256400 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 733130500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4264886500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4998017000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3246952500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3246952500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 733130500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7511839000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8244969500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028404 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.481831 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.481831 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912838 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912838 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478697 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478697 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915633 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915633 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159144 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159144 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.183184 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099156 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.183184 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149988 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149988 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196440 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196440 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097324 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231234 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22821.854560 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29670.583433 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19528.282560 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36473.710048 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36473.710048 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31250.956420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44864.886478 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186511.959087 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163165.698458 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161831.470547 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161831.470547 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 174852.582729 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228360 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 337249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1738254 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1687491 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28452 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 505760 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88185 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111549 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 297072 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284592 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218454 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2369943 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9884 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21632 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4619913 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70449208 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84455860 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 30948 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154949960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 641653 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3048291 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.181009 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.385025 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 64679 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1685922 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 869596 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1383128 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312557 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298532 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285304 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106585 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3316089 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2519725 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10102 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22430 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5868346 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70857528 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84663704 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14816 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32924 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 155568972 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1147635 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4840235 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.218671 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.413345 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2496524 81.90% 81.90% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 551767 18.10% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3781818 78.13% 78.13% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1058417 21.87% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3048291 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1778395498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4840235 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2418139995 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114075998 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114234000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1664668023 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1668899500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1210905566 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1193519480 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 13895250 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14203990 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1295,59 +1314,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3295 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 601 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9355.742574 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8433.023249 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5123.717679 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 905 35.84% 35.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1497 59.29% 95.13% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.46% 97.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 54 2.14% 99.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.16% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1642630968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1642630968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1642630968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1932 76.51% 76.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 593 23.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3364 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3364 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 665 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3364 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3364 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3364 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2594 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9203.479719 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5035.039152 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1036 39.94% 39.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1440 55.51% 95.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 55 2.12% 97.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.16% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.23% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2594 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1650887468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1650887468 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1650887468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.67% 74.67% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 657 25.33% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2594 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3364 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3364 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2594 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2594 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5958 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3921520 # DTB read hits -system.cpu1.dtb.read_misses 2787 # DTB read misses -system.cpu1.dtb.write_hits 3403460 # DTB write hits -system.cpu1.dtb.write_misses 508 # DTB write misses +system.cpu1.dtb.read_hits 6310579 # DTB read hits +system.cpu1.dtb.read_misses 2859 # DTB read misses +system.cpu1.dtb.write_hits 4631996 # DTB write hits +system.cpu1.dtb.write_misses 505 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2006 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2036 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 344 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3924307 # DTB read accesses -system.cpu1.dtb.write_accesses 3403968 # DTB write accesses +system.cpu1.dtb.read_accesses 6313438 # DTB read accesses +system.cpu1.dtb.write_accesses 4632501 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7324980 # DTB hits -system.cpu1.dtb.misses 3295 # DTB misses -system.cpu1.dtb.accesses 7328275 # DTB accesses +system.cpu1.dtb.hits 10942575 # DTB hits +system.cpu1.dtb.misses 3364 # DTB misses +system.cpu1.dtb.accesses 10945939 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1377,43 +1395,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1740 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9831.970936 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8728.225186 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5541.612386 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.71% 16.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 162 14.71% 31.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 45.14% 76.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.54% 97.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.73% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1642083968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1642083968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1642083968 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9680.648713 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5669.589944 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 351 31.71% 31.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 484 43.72% 75.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 202 18.25% 93.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 20 1.81% 95.48% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.08% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.36% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.54% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1650350468 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1650350468 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1650350468 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16475856 # ITB inst hits -system.cpu1.itb.inst_misses 1740 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 27093131 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1422,178 +1439,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16477596 # ITB inst accesses -system.cpu1.itb.hits 16475856 # DTB hits -system.cpu1.itb.misses 1740 # DTB misses -system.cpu1.itb.accesses 16477596 # DTB accesses -system.cpu1.numCycles 5736236800 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 27094877 # ITB inst accesses +system.cpu1.itb.hits 27093131 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 27094877 # DTB accesses +system.cpu1.numCycles 5736521358 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 16121027 # Number of instructions committed -system.cpu1.committedOps 19644884 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17715670 # Number of integer alu accesses +system.cpu1.committedInsts 26153786 # Number of instructions committed +system.cpu1.committedOps 32053131 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 28968286 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 1024357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1805296 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17715670 # number of integer instructions +system.cpu1.num_func_calls 3299674 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2947168 # number of instructions that are conditional controls +system.cpu1.num_int_insts 28968286 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 32157611 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12423544 # number of times the integer registers were written +system.cpu1.num_int_register_reads 54552282 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20759353 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 71811842 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6390929 # number of times the CC registers were written -system.cpu1.num_mem_refs 7557236 # number of memory refs -system.cpu1.num_load_insts 4032278 # Number of load instructions -system.cpu1.num_store_insts 3524958 # Number of store instructions -system.cpu1.num_idle_cycles 5685648636.968273 # Number of idle cycles -system.cpu1.num_busy_cycles 50588163.031727 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008819 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991181 # Percentage of idle cycles -system.cpu1.Branches 2908306 # Number of branches fetched +system.cpu1.num_cc_register_reads 117965505 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9826508 # number of times the CC registers were written +system.cpu1.num_mem_refs 11178844 # number of memory refs +system.cpu1.num_load_insts 6422284 # Number of load instructions +system.cpu1.num_store_insts 4756560 # Number of store instructions +system.cpu1.num_idle_cycles 5660914446.273914 # Number of idle cycles +system.cpu1.num_busy_cycles 75606911.726086 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013180 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986820 # Percentage of idle cycles +system.cpu1.Branches 6348758 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12407832 62.06% 62.06% # Class of executed instruction -system.cpu1.op_class::IntMult 25890 0.13% 62.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3309 0.02% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4032278 20.17% 82.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 3524958 17.63% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 21763864 65.97% 65.97% # Class of executed instruction +system.cpu1.op_class::IntMult 43243 0.13% 66.10% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3315 0.01% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction +system.cpu1.op_class::MemRead 6422284 19.47% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 4756560 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 19994333 # Class of executed instruction +system.cpu1.op_class::total 32989332 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 185399 # number of replacements -system.cpu1.dcache.tags.tagsinuse 466.419324 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7065195 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 185751 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.035838 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104846956000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 466.419324 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.910975 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.910975 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 84 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14867676 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14867676 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3611065 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3611065 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3216741 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3216741 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48524 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48524 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78212 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78212 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70143 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70143 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6827806 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6827806 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6876330 # number of overall hits -system.cpu1.dcache.overall_hits::total 6876330 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133141 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133141 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 90456 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 90456 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30283 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30283 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17238 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17238 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23491 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23491 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 223597 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 223597 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 253880 # number of overall misses -system.cpu1.dcache.overall_misses::total 253880 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1928381738 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1928381738 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2296114353 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2296114353 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319996750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 319996750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 553086757 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 553086757 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2433500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2433500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4224496091 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4224496091 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4224496091 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4224496091 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3744206 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3744206 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3307197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3307197 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78807 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 78807 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95450 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95450 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93634 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93634 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7051403 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7051403 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7130210 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7130210 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035559 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035559 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027351 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027351 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384268 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384268 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250881 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250881 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031710 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031710 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035606 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035606 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.755853 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14483.755853 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25383.770596 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25383.770596 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18563.449936 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18563.449936 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 185916 # number of replacements +system.cpu1.dcache.tags.tagsinuse 465.807736 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 10656106 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 186281 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 57.204471 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104850302500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.807736 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.909781 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.909781 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 66 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 22064450 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 22064450 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 5988472 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5988472 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4434786 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4434786 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48931 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48931 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78766 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78766 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70801 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70801 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 10423258 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 10423258 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 10472189 # number of overall hits +system.cpu1.dcache.overall_hits::total 10472189 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133050 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133050 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91601 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91601 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30372 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30372 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17242 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17242 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23381 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23381 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 224651 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 224651 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255023 # number of overall misses +system.cpu1.dcache.overall_misses::total 255023 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1943965500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1943965500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2376775500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2376775500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 323304000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 323304000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547906000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 547906000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2312500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2312500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4320741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4320741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4320741000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4320741000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121522 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6121522 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4526387 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4526387 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79303 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79303 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96008 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96008 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94182 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94182 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 10647909 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 10647909 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 10727212 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 10727212 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021735 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.021735 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020237 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.020237 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382987 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382987 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179589 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179589 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248253 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248253 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021098 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.021098 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023773 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.023773 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1602,147 +1619,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 114520 # number of writebacks -system.cpu1.dcache.writebacks::total 114520 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 275 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12066 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12066 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132866 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 132866 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90456 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90456 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29572 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29572 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5172 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5172 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23491 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23491 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 223322 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 223322 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 252894 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 252894 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3084 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5521 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1717533750 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1717533750 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2155103647 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2155103647 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 472304765 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 472304765 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84734500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84734500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 516677243 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 516677243 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2366000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2366000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3872637397 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3872637397 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344942162 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4344942162 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406850750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406850750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 279944500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279944500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 686795250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 686795250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035486 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035486 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027351 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027351 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.375246 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.375246 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054185 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054185 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250881 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250881 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031671 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031671 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035468 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 116022 # number of writebacks +system.cpu1.dcache.writebacks::total 116022 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12054 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12054 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 266 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 266 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 266 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132784 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 132784 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91601 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91601 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29597 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29597 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5188 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23381 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23381 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 224385 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 224385 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 253982 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 253982 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13773 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13773 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11227 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 25000 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 25000 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1804303500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1804303500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2285174500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2285174500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494107000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494107000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90251000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90251000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524565000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524565000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2272500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2272500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4089478000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4089478000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4583585000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4583585000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2232716000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2232716000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1768357000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1768357000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4001073000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4001073000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021691 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021691 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020237 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020237 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373214 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373214 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248253 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248253 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021073 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.021073 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023676 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.023676 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13588.259881 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13588.259881 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24947.047521 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24947.047521 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16694.496064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16694.496064 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17396.106399 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17396.106399 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22435.524571 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22435.524571 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160042.920000 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160042.920000 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 502966 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.575795 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15972373 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 503478 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.724073 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84694032500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.575795 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973781 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973781 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 505537 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.573002 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 26587077 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506049 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 52.538543 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84702248000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573002 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973775 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973775 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33455180 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33455180 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15972373 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15972373 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15972373 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15972373 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15972373 # number of overall hits -system.cpu1.icache.overall_hits::total 15972373 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 503478 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 503478 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 503478 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 503478 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 503478 # number of overall misses -system.cpu1.icache.overall_misses::total 503478 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4406075262 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4406075262 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4406075262 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4406075262 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4406075262 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4406075262 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16475851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16475851 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16475851 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16475851 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16475851 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16475851 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030559 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030559 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030559 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030559 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030559 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030559 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8751.276644 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8751.276644 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8751.276644 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8751.276644 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 54692301 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 54692301 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 26587077 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26587077 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26587077 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26587077 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26587077 # number of overall hits +system.cpu1.icache.overall_hits::total 26587077 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506049 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506049 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506049 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506049 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506049 # number of overall misses +system.cpu1.icache.overall_misses::total 506049 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4455517000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4455517000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4455517000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4455517000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4455517000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4455517000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 27093126 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 27093126 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 27093126 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 27093126 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 27093126 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 27093126 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018678 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018678 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.018678 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018678 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.018678 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8804.516954 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8804.516954 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8804.516954 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8804.516954 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1751,224 +1768,237 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503478 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 503478 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 503478 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 503478 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 503478 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 503478 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506049 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506049 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506049 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506049 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506049 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506049 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3901799738 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3901799738 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3901799738 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3901799738 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3901799738 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3901799738 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15252750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15252750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15252750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15252750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030559 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030559 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030559 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7749.692614 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86173.728814 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86173.728814 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4202492500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4202492500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4202492500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4202492500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4202492500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4202492500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15340000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15340000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15340000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15340000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018678 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.018678 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018678 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.018678 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8304.516954 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8304.516954 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8304.516954 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8304.516954 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86666.666667 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86666.666667 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86666.666667 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 195194 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 195194 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199458 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199458 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 57534 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 39835 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14698.947760 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 703731 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 54406 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.934805 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58862 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 46506 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15029.734126 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1265349 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 61182 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.681720 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8839.546228 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.119643 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.076473 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.274029 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1936.419828 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 726.511560 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.539523 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 8657.593794 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.281679 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079815 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3148.961374 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2173.187241 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1044.630222 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.528418 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194841 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.118190 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044343 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.897153 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1124 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13429 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1096 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.192197 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132641 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.063759 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.917342 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1197 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13460 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 35 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1156 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1612 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11521 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068604 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819641 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 14679345 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 14679345 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3122 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1719 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 490518 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 100742 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 596101 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 114520 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 114520 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1111 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1111 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 866 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 866 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27369 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27369 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3122 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1719 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 490518 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 128111 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 623470 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3122 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1719 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 490518 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 128111 # number of overall hits -system.cpu1.l2cache.overall_hits::total 623470 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 12960 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 66868 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 80413 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27915 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 27915 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22615 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22615 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34061 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34061 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12960 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 100929 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 114474 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 12960 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 100929 # number of overall misses -system.cpu1.l2cache.overall_misses::total 114474 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6443750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5338500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 460251238 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1451446014 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1923479502 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 535355877 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 535355877 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 456012560 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 456012560 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2321000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2321000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1258488445 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1258488445 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6443750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5338500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 460251238 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2709934459 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3181967947 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6443750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5338500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 460251238 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2709934459 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3181967947 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3440 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1986 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 503478 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 167610 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 676514 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 114520 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 114520 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29026 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29026 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23481 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23481 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61430 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 61430 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3440 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1986 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 503478 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 229040 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 737944 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3440 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1986 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 503478 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 229040 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 737944 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134441 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.025741 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.398950 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.118864 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.961724 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.961724 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.963119 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.963119 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1596 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11590 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073059 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.821533 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23794594 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23794594 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1709 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 4800 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 116022 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 116022 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1472 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1472 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 842 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 842 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27319 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27319 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492294 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 492294 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99296 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99296 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1709 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 492294 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 126615 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 623709 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1709 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 492294 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 126615 # number of overall hits +system.cpu1.l2cache.overall_hits::total 623709 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 314 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 266 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 580 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28095 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28095 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22537 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22537 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34715 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34715 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13755 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13755 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68273 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 68273 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 314 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 266 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13755 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 102988 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 117323 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 314 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 266 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13755 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 102988 # number of overall misses +system.cpu1.l2cache.overall_misses::total 117323 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6334500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5311000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 11645500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 538209000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 538209000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 450797500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 450797500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2212500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2212500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1336972500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1336972500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 492390500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 492390500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1491495000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1491495000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6334500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5311000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 492390500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2828467500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3332503500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6334500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5311000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 492390500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2828467500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3332503500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3405 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1975 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 116022 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 116022 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29567 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29567 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23379 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23379 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62034 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62034 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 506049 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 506049 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167569 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 167569 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3405 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1975 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 506049 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 229603 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 741032 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3405 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1975 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 506049 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 229603 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 741032 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134684 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.107807 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950215 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950215 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.963985 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.963985 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554469 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554469 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134441 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025741 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.440661 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155126 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134441 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025741 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.440661 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155126 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19994.382022 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35513.212809 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21706.137674 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23920.006740 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19178.071897 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19178.071897 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20164.163608 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20164.163608 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 232100 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232100 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36948.076833 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36948.076833 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19994.382022 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35513.212809 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26849.908936 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27796.424926 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19994.382022 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35513.212809 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26849.908936 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27796.424926 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.559612 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.559612 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027181 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027181 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.407432 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.407432 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134684 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027181 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.448548 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.158324 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.092217 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134684 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027181 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.448548 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.158324 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19966.165414 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20078.448276 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19156.753871 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19156.753871 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20002.551360 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20002.551360 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1106250 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1106250 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38512.818666 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38512.818666 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35797.201018 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35797.201018 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21846.044556 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21846.044556 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19966.165414 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35797.201018 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27464.049210 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 28404.520000 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20173.566879 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19966.165414 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35797.201018 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27464.049210 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 28404.520000 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1977,196 +2007,210 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 25678 # number of writebacks -system.cpu1.l2cache.writebacks::total 25678 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 69 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 69 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 69 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 69 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 12960 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66868 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 80413 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22290 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 22290 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27915 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27915 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22615 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22615 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 10 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33992 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 33992 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12960 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100860 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 114405 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12960 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100860 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22290 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 136695 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 30696 # number of writebacks +system.cpu1.l2cache.writebacks::total 30696 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 90 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 90 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 90 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 90 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 314 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 266 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 580 # number of ReadReq MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2031 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 2031 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23725 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 23725 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28095 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28095 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22537 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22537 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34625 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34625 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13755 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13755 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68273 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68273 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 314 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 266 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13755 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102898 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 117233 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 314 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 266 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13755 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102898 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23725 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 140958 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3261 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 13773 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 13950 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11227 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5698 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3603000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 375210762 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1016628986 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1399818998 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 742843274 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 742843274 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439552298 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439552298 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340829757 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340829757 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2028500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2028500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1027563755 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1027563755 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3603000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 375210762 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2044192741 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2427382753 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3603000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 375210762 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2044192741 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 742843274 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3170226027 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13847750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382171500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396019250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 261667000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 261667000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13847750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 643838500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 657686250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.398950 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118864 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 25000 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25177 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3715000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8165500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 839425646 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 839425646 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 455073500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 455073500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 349086500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 349086500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1972500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1972500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1119618000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1119618000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 409860500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 409860500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1081857000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1081857000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3715000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 409860500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2201475000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2619501000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4450500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3715000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 409860500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2201475000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 839425646 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3458926646 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14012500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2122532000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2136544500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1684154500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1684154500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14012500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3806686500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3820699000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107807 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.961724 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.961724 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963119 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963119 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950215 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950215 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963985 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963985 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.553345 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.553345 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440360 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155032 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440360 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.558162 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.558162 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027181 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407432 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407432 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.448156 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158202 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.092217 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.134684 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027181 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.448156 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185238 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 202850 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 202850 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190219 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14078.448276 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35381.481391 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16197.668624 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16197.668624 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15489.483960 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 986250 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 986250 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21394.730704 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22344.399614 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14173.566879 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13966.165414 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21394.730704 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 151753.544902 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1060646 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 722071 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2437 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 114520 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 27384 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84086 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66129 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1007310 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 764894 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5302 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9429 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1786935 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32223300 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24770860 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7944 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13760 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57015864 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 636167 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1470628 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.384445 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.486464 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 53469 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 734633 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 478531 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 680350 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29761 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 73690 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41411 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85868 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66733 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506049 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 504061 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1509072 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 874243 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5299 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9468 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2398082 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32387844 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24934344 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7900 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13620 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57343708 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1094784 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2530004 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.405048 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.490902 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 905253 61.56% 61.56% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 565375 38.44% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1505230 59.50% 59.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1024774 40.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1470628 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 573017999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2530004 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 878944000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81259000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80122000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 755831512 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759250500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 377529095 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 390308000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 5989250 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6063998 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 23198 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2257,23 +2301,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 199086925 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187549442 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36785519 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.391068 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.390664 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288263513000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.391068 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899442 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899442 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288350117000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.390664 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899417 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899417 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2281,49 +2325,49 @@ system.iocache.tags.tag_accesses 328311 # Nu system.iocache.tags.data_accesses 328311 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32671377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32671377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655899029 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6655899029 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32671377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32671377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32671377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32671377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32656876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32656876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4281964566 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4281964566 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32656876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32656876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32656876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32656876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128123.047059 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128123.047059 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183742.795633 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183742.795633 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128123.047059 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128123.047059 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23173 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128066.180392 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128066.180392 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128066.180392 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3543 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.540502 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 132.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2331,325 +2375,325 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19404377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19404377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772213067 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772213067 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19404377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19404377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19404377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19404377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19906876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19906876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2470764566 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2470764566 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19906876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19906876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19906876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19906876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76095.596078 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76095.596078 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131741.747653 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131741.747653 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78066.180392 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78066.180392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78066.180392 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78066.180392 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 122211 # number of replacements -system.l2c.tags.tagsinuse 63914.238063 # Cycle average of tags in use -system.l2c.tags.total_refs 336222 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 186592 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.801910 # Average number of references to valid blocks. +system.l2c.tags.replacements 130439 # number of replacements +system.l2c.tags.tagsinuse 63983.082008 # Cycle average of tags in use +system.l2c.tags.total_refs 387954 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 194793 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.991622 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11496.547602 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049900 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.062133 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7182.549375 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2988.985612 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38830.864169 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955834 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1379.188596 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 342.352201 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1689.682641 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.175423 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12138.175325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.910023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041062 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7215.667264 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2903.196215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37504.021978 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955808 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1528.247767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 561.168860 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2127.697705 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.185214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.109597 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045608 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.592512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110102 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044299 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572266 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.005224 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.975254 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32922 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31453 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4653 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.023319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.032466 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976304 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32301 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32046 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4667 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27470 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 241 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1916 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29284 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.502350 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.479935 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4784413 # Number of tag accesses -system.l2c.tags.data_accesses 4784413 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 62 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29385 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 44972 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45934 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 27 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 29 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 10817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 7566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4637 # number of ReadReq hits -system.l2c.ReadReq_hits::total 143498 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 220641 # number of Writeback hits -system.l2c.Writeback_hits::total 220641 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2604 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 702 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3306 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 145 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 242 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 387 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4135 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1764 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5899 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 62 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29385 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45934 # number of demand (read+write) hits +system.l2c.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1924 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29877 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.492874 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.488983 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5300600 # Number of tag accesses +system.l2c.tags.data_accesses 5300600 # Number of data accesses +system.l2c.Writeback_hits::writebacks 225955 # number of Writeback hits +system.l2c.Writeback_hits::total 225955 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2137 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 661 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2798 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 135 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 280 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1461 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5282 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 91 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 51 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 29278 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45470 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 44948 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11381 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 8374 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5310 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 144957 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 91 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 51 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29278 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49291 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 44948 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 27 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 10817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9330 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4637 # number of demand (read+write) hits -system.l2c.demand_hits::total 149397 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 62 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29385 # number of overall hits -system.l2c.overall_hits::cpu0.data 49107 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45934 # number of overall hits +system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11381 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9835 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5310 # number of demand (read+write) hits +system.l2c.demand_hits::total 150239 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 91 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 51 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29278 # number of overall hits +system.l2c.overall_hits::cpu0.data 49291 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 44948 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 27 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits -system.l2c.overall_hits::cpu1.inst 10817 # number of overall hits -system.l2c.overall_hits::cpu1.data 9330 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4637 # number of overall hits -system.l2c.overall_hits::total 149397 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17693 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8817 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130884 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2143 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 691 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5571 # number of ReadReq misses -system.l2c.ReadReq_misses::total 165808 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8462 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2686 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11148 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 478 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1247 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1725 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10966 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18234 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses +system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11381 # number of overall hits +system.l2c.overall_hits::cpu1.data 9835 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5310 # number of overall hits +system.l2c.overall_hits::total 150239 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8391 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2650 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11041 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 492 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1207 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1699 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11580 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8214 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19794 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17402 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8820 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134398 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2367 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 170188 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17693 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 19783 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 130884 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17402 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20400 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134398 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2143 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7959 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5571 # number of demand (read+write) misses -system.l2c.demand_misses::total 184042 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2367 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9156 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses +system.l2c.demand_misses::total 189982 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17693 # number of overall misses -system.l2c.overall_misses::cpu0.data 19783 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 130884 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17402 # number of overall misses +system.l2c.overall_misses::cpu0.data 20400 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134398 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2143 # number of overall misses -system.l2c.overall_misses::cpu1.data 7959 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5571 # number of overall misses -system.l2c.overall_misses::total 184042 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 466750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1430972014 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 766150824 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 96750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 177373250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 73282238 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15872503197 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11409175 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2717413 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 14126588 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1225466 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 966969 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2192435 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 964303159 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 590306733 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1554609892 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 466750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1430972014 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1730453983 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 96750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 177373250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 663588971 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17427113089 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 466750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1430972014 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1730453983 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 96750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 177373250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 663588971 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17427113089 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 75 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 47078 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 53789 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 176818 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 29 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 12960 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 8257 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10208 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 309306 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 220641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 220641 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11066 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3388 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14454 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 623 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1489 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15101 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9032 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24133 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 75 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 47078 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 68890 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 176818 # number of demand (read+write) accesses +system.l2c.overall_misses::cpu1.inst 2367 # number of overall misses +system.l2c.overall_misses::cpu1.data 9156 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses +system.l2c.overall_misses::total 189982 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 8210000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2280000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10490000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1358000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1106500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2464500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1018907000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 666031500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1684938500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 606500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 166000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1402771500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 762849500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 13087577967 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 194012000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 84119500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 16261208649 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 606500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1402771500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1781756500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13087577967 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 194012000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 750151000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17946147149 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 606500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1402771500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1781756500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13087577967 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 194012000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 750151000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 729023182 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17946147149 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 225955 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225955 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10528 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3311 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13839 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 627 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1352 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1979 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9675 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25076 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 98 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 53 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 46680 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 54290 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179346 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 28 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 27 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13748 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 9316 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11559 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 315145 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 98 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 53 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 46680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 69691 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179346 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 29 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 12960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 17289 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10208 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 333439 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 75 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 47078 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 68890 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 176818 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13748 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 18991 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11559 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 340221 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 98 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 53 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 46680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 69691 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179346 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 29 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 12960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 17289 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10208 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 333439 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.031250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375823 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.163918 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.165355 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.536065 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.764685 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792798 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.771274 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.767255 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.837475 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.816761 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.726177 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.804694 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.755563 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.031250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375823 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.287168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for demand accesses +system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13748 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 18991 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11559 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 340221 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797017 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800362 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.797818 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784689 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.892751 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.858514 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.751899 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.848992 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.789360 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.037736 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.372793 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162461 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172170 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.101116 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.540031 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.037736 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.372793 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.292721 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.165355 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.460351 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.551951 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.031250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.287168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.inst 0.172170 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.482123 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.558408 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.071429 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.037736 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.372793 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.292721 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.749378 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.165355 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.460351 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.551951 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80877.862092 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 86894.728819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 96750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82768.665422 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 106052.442836 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 95728.210925 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1348.283503 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1011.695086 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1267.185863 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2563.736402 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 775.436247 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1270.976812 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87935.724877 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81219.968767 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 85258.851157 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80877.862092 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 87471.767831 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 96750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 82768.665422 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83375.922980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 94690.956896 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80877.862092 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 87471.767831 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 96750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 82768.665422 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83375.922980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 94690.956896 # average overall miss latency +system.l2c.overall_miss_rate::cpu1.inst 0.172170 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.482123 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.540618 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.558408 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 978.429269 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 860.377358 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 950.095100 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2760.162602 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 916.735708 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1450.559152 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87988.514680 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81084.915997 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85123.699101 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80609.786231 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86490.873016 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 81965.356992 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89298.832272 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 95548.503120 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80609.786231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87341.004902 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81965.356992 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81929.991263 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94462.355113 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86642.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80609.786231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87341.004902 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97379.261351 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81965.356992 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81929.991263 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116662.375100 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94462.355113 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2658,265 +2702,271 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 93389 # number of writebacks -system.l2c.writebacks::total 93389 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17687 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8817 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130884 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2134 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 691 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5571 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 165793 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8462 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2686 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11148 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 478 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1247 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1725 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 10966 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7268 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18234 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.writebacks::writebacks 100321 # number of writebacks +system.l2c.writebacks::total 100321 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 4 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 6 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3050 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3050 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8391 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2650 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11041 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 492 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1207 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1699 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11580 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8214 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19794 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17400 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8820 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2363 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 170182 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17687 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 19783 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130884 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17400 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20400 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2134 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 7959 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5571 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 184027 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9156 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 189976 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17687 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 19783 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130884 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17400 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20400 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134398 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2134 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 7959 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5571 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 184027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2363 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9156 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 189976 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3080 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44054 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30889 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 13769 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44078 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11227 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5517 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74943 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 391750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1208996486 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 655819176 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11160223644 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 83750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 149987000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 64618762 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 579886727 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 13820147295 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 151117443 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47855180 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 198972623 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8594976 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22191743 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 30786719 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 828734841 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 499414267 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1328149108 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 391750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1208996486 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1484554017 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11160223644 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 83750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 149987000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 564033029 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 579886727 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15148296403 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 391750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1208996486 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1484554017 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11160223644 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 83750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 149987000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 564033029 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 579886727 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15148296403 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306043500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10310750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321686500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6187851250 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4077783000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216378500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4294161500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9383826500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10310750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538065000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10482012750 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163918 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083687 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.536016 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.764685 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792798 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.771274 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.767255 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837475 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.816761 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726177 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.804694 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.755563 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.287168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for demand accesses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 74991 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 174583000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 55064000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 229647000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10311000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25083500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35394500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 903107000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 583891500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1486998500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 536500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 146000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1228508000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 674649500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 72500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 170183500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 74699500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 14558926649 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 536500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 146000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1228508000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1577756500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 72500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 170183500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 658591000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16045925149 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 536500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 146000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1228508000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1577756500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11743597967 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 72500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 170183500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 658591000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 666533182 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16045925149 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 570734000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3884897500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10826500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1874631500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6341089500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2912289500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1493293500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4405583000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 570734000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6797187000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10826500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3367925000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10746672500 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797017 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800362 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.797818 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784689 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.892751 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.858514 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.751899 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848992 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.789360 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162461 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.101116 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.540012 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.292721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.460351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.551906 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.287168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.482123 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.558390 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.071429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037736 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372751 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.292721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.749378 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.460351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.551906 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74381.215379 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 93514.850941 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 83357.845597 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17858.360080 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17816.522710 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17848.279781 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17981.121339 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.105052 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17847.373333 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75573.120646 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68714.125894 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72839.152572 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516 # average overall mshr uncacheable latency +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171880 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.482123 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.540618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.558390 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20805.982600 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20778.867925 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20799.474685 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20957.317073 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20781.690141 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20832.548558 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77988.514680 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71084.915997 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75123.699101 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 210102 # Transaction distribution -system.membus.trans_dist::ReadResp 210102 # Transaction distribution -system.membus.trans_dist::WriteReq 30889 # Transaction distribution -system.membus.trans_dist::WriteResp 30889 # Transaction distribution -system.membus.trans_dist::Writeback 129579 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 77022 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40122 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12986 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 38648 # Transaction distribution -system.membus.trans_dist::ReadExResp 18121 # Transaction distribution +system.membus.trans_dist::ReadReq 44078 # Transaction distribution +system.membus.trans_dist::ReadResp 214515 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::Writeback 136511 # Transaction distribution +system.membus.trans_dist::CleanEvict 15728 # Transaction distribution +system.membus.trans_dist::UpgradeReq 75283 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40251 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12822 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 40262 # Transaction distribution +system.membus.trans_dist::ReadExResp 19712 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170437 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13636 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 639843 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 761429 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 870337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672670 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 794352 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 903273 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17781832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17971968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22607424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125322 # Total snoops (count) -system.membus.snoop_fanout::samples 562672 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18608200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18798528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21115648 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123870 # Total snoops (count) +system.membus.snoop_fanout::samples 589976 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562672 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 589976 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562672 # Request fanout histogram -system.membus.reqLayer0.occupancy 88118500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 589976 # Request fanout histogram +system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11425000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1114763998 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1021914451 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1110191376 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1141120383 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37521481 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64390592 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2949,44 +2999,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 475433 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 475418 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 220641 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 80215 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40509 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 120724 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50702 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50702 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1061225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 262179 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1323404 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31467168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4256160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 35723328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 289388 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 934737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039071 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.193764 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 44082 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 479204 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 362509 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 82484 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77999 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40531 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 118530 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 93 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51218 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51218 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 435137 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1069100 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 319954 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1389054 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31596740 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4900924 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36497664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 452334 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1194337 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.170309 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.375904 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 898216 96.09% 96.09% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36521 3.91% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 990931 82.97% 82.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 203406 17.03% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 934737 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 749457686 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1194337 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 799819351 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 652203239 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 609335323 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 220037759 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 239074701 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index c544f96e6..21bc80649 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903548 # Number of seconds simulated -sim_ticks 2903547931500 # Number of ticks simulated -final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903468 # Number of seconds simulated +sim_ticks 2903467553500 # Number of ticks simulated +final_tick 2903467553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 571103 # Simulator instruction rate (inst/s) -host_op_rate 688575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14743405801 # Simulator tick rate (ticks/s) -host_mem_usage 560940 # Number of bytes of host memory used -host_seconds 196.94 # Real time elapsed on the host -sim_insts 112472279 # Number of instructions simulated -sim_ops 135607130 # Number of ops (including micro ops) simulated +host_inst_rate 736333 # Simulator instruction rate (inst/s) +host_op_rate 887789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19005878440 # Simulator tick rate (ticks/s) +host_mem_usage 619548 # Number of bytes of host memory used +host_seconds 152.77 # Real time elapsed on the host +sim_insts 112487279 # Number of instructions simulated +sim_ops 135624752 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1189412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9042916 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory +system.physmem.bytes_read::total 10233864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1189412 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189412 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7647616 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory +system.physmem.bytes_written::total 7665140 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141815 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168877 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119494 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123875 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 409652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3114523 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3524704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 409652 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409652 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2633960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6036 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2639995 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2633960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 409652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3120558 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168876 # Number of read requests accepted -system.physmem.writeReqs 160010 # Number of write requests accepted -system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10030 # Per bank write bursts -system.physmem.perBankRdBursts::1 9665 # Per bank write bursts -system.physmem.perBankRdBursts::2 10302 # Per bank write bursts -system.physmem.perBankRdBursts::3 9920 # Per bank write bursts +system.physmem.bw_total::total 6164699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168877 # Number of read requests accepted +system.physmem.writeReqs 123875 # Number of write requests accepted +system.physmem.readBursts 168877 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123875 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10799552 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7677760 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10233864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7665140 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10018 # Per bank write bursts +system.physmem.perBankRdBursts::1 9658 # Per bank write bursts +system.physmem.perBankRdBursts::2 10300 # Per bank write bursts +system.physmem.perBankRdBursts::3 9945 # Per bank write bursts system.physmem.perBankRdBursts::4 18863 # Per bank write bursts -system.physmem.perBankRdBursts::5 10093 # Per bank write bursts -system.physmem.perBankRdBursts::6 10296 # Per bank write bursts +system.physmem.perBankRdBursts::5 10091 # Per bank write bursts +system.physmem.perBankRdBursts::6 10302 # Per bank write bursts system.physmem.perBankRdBursts::7 10601 # Per bank write bursts -system.physmem.perBankRdBursts::8 9928 # Per bank write bursts -system.physmem.perBankRdBursts::9 10198 # Per bank write bursts -system.physmem.perBankRdBursts::10 9956 # Per bank write bursts -system.physmem.perBankRdBursts::11 9036 # Per bank write bursts -system.physmem.perBankRdBursts::12 9857 # Per bank write bursts -system.physmem.perBankRdBursts::13 10481 # Per bank write bursts -system.physmem.perBankRdBursts::14 9974 # Per bank write bursts -system.physmem.perBankRdBursts::15 9528 # Per bank write bursts -system.physmem.perBankWrBursts::0 8313 # Per bank write bursts -system.physmem.perBankWrBursts::1 8253 # Per bank write bursts -system.physmem.perBankWrBursts::2 9067 # Per bank write bursts -system.physmem.perBankWrBursts::3 8494 # Per bank write bursts -system.physmem.perBankWrBursts::4 8419 # Per bank write bursts -system.physmem.perBankWrBursts::5 8394 # Per bank write bursts -system.physmem.perBankWrBursts::6 8676 # Per bank write bursts -system.physmem.perBankWrBursts::7 8975 # Per bank write bursts -system.physmem.perBankWrBursts::8 8824 # Per bank write bursts -system.physmem.perBankWrBursts::9 8984 # Per bank write bursts -system.physmem.perBankWrBursts::10 8586 # Per bank write bursts -system.physmem.perBankWrBursts::11 8136 # Per bank write bursts -system.physmem.perBankWrBursts::12 8548 # Per bank write bursts -system.physmem.perBankWrBursts::13 8715 # Per bank write bursts -system.physmem.perBankWrBursts::14 8203 # Per bank write bursts -system.physmem.perBankWrBursts::15 7843 # Per bank write bursts +system.physmem.perBankRdBursts::8 9921 # Per bank write bursts +system.physmem.perBankRdBursts::9 10207 # Per bank write bursts +system.physmem.perBankRdBursts::10 9962 # Per bank write bursts +system.physmem.perBankRdBursts::11 9026 # Per bank write bursts +system.physmem.perBankRdBursts::12 9868 # Per bank write bursts +system.physmem.perBankRdBursts::13 10473 # Per bank write bursts +system.physmem.perBankRdBursts::14 9981 # Per bank write bursts +system.physmem.perBankRdBursts::15 9527 # Per bank write bursts +system.physmem.perBankWrBursts::0 7412 # Per bank write bursts +system.physmem.perBankWrBursts::1 7255 # Per bank write bursts +system.physmem.perBankWrBursts::2 8123 # Per bank write bursts +system.physmem.perBankWrBursts::3 7537 # Per bank write bursts +system.physmem.perBankWrBursts::4 7355 # Per bank write bursts +system.physmem.perBankWrBursts::5 7348 # Per bank write bursts +system.physmem.perBankWrBursts::6 7577 # Per bank write bursts +system.physmem.perBankWrBursts::7 7905 # Per bank write bursts +system.physmem.perBankWrBursts::8 7603 # Per bank write bursts +system.physmem.perBankWrBursts::9 7853 # Per bank write bursts +system.physmem.perBankWrBursts::10 7551 # Per bank write bursts +system.physmem.perBankWrBursts::11 6940 # Per bank write bursts +system.physmem.perBankWrBursts::12 7397 # Per bank write bursts +system.physmem.perBankWrBursts::13 7831 # Per bank write bursts +system.physmem.perBankWrBursts::14 7359 # Per bank write bursts +system.physmem.perBankWrBursts::15 6919 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 2903547607000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2903467231500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159304 # Read request sizes (log2) +system.physmem.readPktSize::6 159305 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 155629 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119494 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,163 +159,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads -system.physmem.totQLat 1499821694 # Total ticks spent queuing -system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 59281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.689209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.095727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.740944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21592 36.42% 36.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15113 25.49% 61.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5696 9.61% 71.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3272 5.52% 77.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2400 4.05% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1627 2.74% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1059 1.79% 85.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 986 1.66% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7536 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59281 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5916 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.520960 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 582.774923 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5915 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5916 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5916 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.278059 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.578317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.228760 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5122 86.58% 86.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 35 0.59% 87.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 194 3.28% 90.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 61 1.03% 91.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 61 1.03% 92.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 181 3.06% 95.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.24% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.08% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.12% 96.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.08% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.76% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.03% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.12% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.29% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5916 # Writes before turning the bus around for reads +system.physmem.totQLat 1515248250 # Total ticks spent queuing +system.physmem.totMemAccLat 4679179500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8979.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27729.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing -system.physmem.readRowHits 138826 # Number of row buffer hits during reads -system.physmem.writeRowHits 106054 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes -system.physmem.avgGap 8828431.76 # Average gap between requests -system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.525264 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states -system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states +system.physmem.avgWrQLen 27.93 # Average write queue length when enqueuing +system.physmem.readRowHits 138696 # Number of row buffer hits during reads +system.physmem.writeRowHits 90730 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.62 # Row buffer hit rate for writes +system.physmem.avgGap 9917839.10 # Average gap between requests +system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229068000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 124987500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700268400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392117760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87025634640 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665738759750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943850825810 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.494214 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770947478500 # Time in different power states +system.physmem_0.memoryStateTime::REF 96952960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35561301500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.425095 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states -system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states +system.physmem_1.actEnergy 219096360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119546625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615919200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385255440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189639989760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85786607970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666825625250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943592040605 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.405084 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772773591250 # Time in different power states +system.physmem_1.memoryStateTime::REF 96952960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33740904250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -365,57 +361,56 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9545 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9548 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9548 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1269 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8279 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9548 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9548 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9548 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7384 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11763.949079 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9756.046308 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7392.958780 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 5809 78.67% 78.67% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1570 21.26% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7384 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 925393500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 925393500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 925393500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6162 83.45% 83.45% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1222 16.55% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7384 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9548 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9548 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7384 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7384 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16932 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24524755 # DTB read hits -system.cpu.dtb.read_misses 8132 # DTB read misses -system.cpu.dtb.write_hits 19610055 # DTB write hits -system.cpu.dtb.write_misses 1413 # DTB write misses +system.cpu.dtb.read_hits 24527083 # DTB read hits +system.cpu.dtb.read_misses 8134 # DTB read misses +system.cpu.dtb.write_hits 19611642 # DTB write hits +system.cpu.dtb.write_misses 1414 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1680 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24532887 # DTB read accesses -system.cpu.dtb.write_accesses 19611468 # DTB write accesses +system.cpu.dtb.read_accesses 24535217 # DTB read accesses +system.cpu.dtb.write_accesses 19613056 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44134810 # DTB hits -system.cpu.dtb.misses 9545 # DTB misses -system.cpu.dtb.accesses 44144355 # DTB accesses +system.cpu.dtb.hits 44138725 # DTB hits +system.cpu.dtb.misses 9548 # DTB misses +system.cpu.dtb.accesses 44148273 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -453,18 +448,18 @@ system.cpu.itb.walker.walkWaitTime::samples 4762 # system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11752.816221 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9620.437143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7446.323545 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1417 45.61% 45.61% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1012 32.57% 78.18% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 676 21.76% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated @@ -475,7 +470,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115569545 # ITB inst hits +system.cpu.itb.inst_hits 115585268 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -492,38 +487,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115574307 # ITB inst accesses -system.cpu.itb.hits 115569545 # DTB hits +system.cpu.itb.inst_accesses 115590030 # ITB inst accesses +system.cpu.itb.hits 115585268 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115574307 # DTB accesses -system.cpu.numCycles 5807095863 # number of cpu cycles simulated +system.cpu.itb.accesses 115590030 # DTB accesses +system.cpu.numCycles 5806935107 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112472279 # Number of instructions committed -system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses +system.cpu.committedInsts 112487279 # Number of instructions committed +system.cpu.committedOps 135624752 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119926396 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9892504 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls -system.cpu.num_int_insts 119910547 # number of integer instructions +system.cpu.num_func_calls 9895067 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15234125 # number of instructions that are conditional controls +system.cpu.num_int_insts 119926396 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read -system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written +system.cpu.num_int_register_reads 218121828 # number of times the integer registers were read +system.cpu.num_int_register_writes 82669566 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written -system.cpu.num_mem_refs 45415290 # number of memory refs -system.cpu.num_load_insts 24846976 # Number of load instructions -system.cpu.num_store_insts 20568314 # Number of store instructions -system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles -system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles -system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927424 # Percentage of idle cycles -system.cpu.Branches 25918910 # Number of branches fetched +system.cpu.num_cc_register_reads 489877250 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51907763 # number of times the CC registers were written +system.cpu.num_mem_refs 45420046 # number of memory refs +system.cpu.num_load_insts 24850080 # Number of load instructions +system.cpu.num_store_insts 20569966 # Number of store instructions +system.cpu.num_idle_cycles 5385437399.888144 # Number of idle cycles +system.cpu.num_busy_cycles 421497707.111855 # Number of busy cycles +system.cpu.not_idle_fraction 0.072585 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927415 # Percentage of idle cycles +system.cpu.Branches 25923230 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93200379 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114573 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -547,260 +542,260 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24850080 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20569966 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138727463 # Class of executed instruction +system.cpu.op_class::total 138745790 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 820494 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3030 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 820821 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.829842 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43246183 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821333 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.653653 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.829842 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits -system.cpu.dcache.overall_hits::total 42336045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177159261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177159261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23117842 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23117842 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18828857 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18828857 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392869 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392869 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443457 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460420 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460420 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41946699 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41946699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42339568 # number of overall hits +system.cpu.dcache.overall_hits::total 42339568 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 401262 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 401262 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298702 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298702 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118314 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118314 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22748 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22748 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses -system.cpu.dcache.overall_misses::total 817925 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 699964 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 699964 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 818278 # number of overall misses +system.cpu.dcache.overall_misses::total 818278 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5968529500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5968529500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12574790000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12574790000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 282012000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 282012000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 18543319500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18543319500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18543319500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18543319500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23519104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23519104 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19127559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19127559 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511183 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511183 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466205 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466205 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460422 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460422 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42646663 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42646663 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43157846 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43157846 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015616 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231451 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231451 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048794 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048794 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016413 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016413 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018960 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018960 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14874.395034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14874.395034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42098.111161 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42098.111161 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12397.221734 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12397.221734 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26491.818865 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26491.818865 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22661.393194 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22661.393194 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks -system.cpu.dcache.writebacks::total 683915 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 682374 # number of writebacks +system.cpu.dcache.writebacks::total 682374 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14211 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14211 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400582 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 400582 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298702 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298702 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116284 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116284 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8537 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8537 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 699284 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 699284 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 815568 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 815568 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31142 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27594 # number of WriteReq MSHR uncacheable +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58736 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5554957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5554957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12276088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12276088000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1529661500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1529661500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110084000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110084000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17831045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17831045000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19360706500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19360706500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5907914500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5907914500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4572592500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4572592500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10480507000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10480507000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017032 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017032 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015616 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227480 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227480 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018312 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018312 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016397 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016397 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018897 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018897 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13867.215701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13867.215701 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41098.111161 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41098.111161 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13154.531148 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13154.531148 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12894.927961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12894.927961 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25499.003266 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25499.003266 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23738.923670 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23738.923670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189708.897951 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189708.897951 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165709.665145 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165709.665145 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178434.128984 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178434.128984 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1698619 # number of replacements -system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1698833 # number of replacements +system.cpu.icache.tags.tagsinuse 510.737457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113885917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699345 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.017537 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 25666177500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.737457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997534 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997534 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits -system.cpu.icache.overall_hits::total 113870408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses -system.cpu.icache.overall_misses::total 1699137 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 117284619 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117284619 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113885917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113885917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113885917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113885917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113885917 # number of overall hits +system.cpu.icache.overall_hits::total 113885917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699351 # number of overall misses +system.cpu.icache.overall_misses::total 1699351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23351891000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23351891000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23351891000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23351891000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23351891000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23351891000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115585268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115585268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115585268 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115585268 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115585268 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115585268 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13741.652549 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13741.652549 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13741.652549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13741.652549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13741.652549 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -809,200 +804,212 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1699351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1699351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1699351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1699351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1699351 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21652540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21652540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21652540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21652540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21652540000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21652540000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 676974000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12741.652549 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12741.652549 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12741.652549 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12741.652549 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75035.912215 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 89783 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 89784 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64924.949267 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4551273 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 155017 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.359832 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50366.375395 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012270 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9623.804573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4930.949297 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768530 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146848 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.990676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 40578005 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578005 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6930 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3595 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 10525 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682374 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682374 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits -system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164955 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164955 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681308 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681308 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513083 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 513083 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6930 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3595 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681308 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 678038 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2369871 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6930 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3595 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681308 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 678038 # number of overall hits +system.cpu.l2cache.overall_hits::total 2369871 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2713 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2713 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131011 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131011 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18023 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 18023 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12320 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 12320 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18023 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143331 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 161363 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses -system.cpu.l2cache.overall_misses::total 161360 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 18023 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143331 # number of overall misses +system.cpu.l2cache.overall_misses::total 161363 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 592500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 166000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 758500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 523000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10012178500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10012178500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1443290000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1443290000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1018929500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1018929500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 592500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 166000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1443290000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11031108000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12475156500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 592500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 166000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1443290000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11031108000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12475156500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6937 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3597 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 10534 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682374 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682374 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2736 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2736 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295966 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295966 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699331 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699331 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525403 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 525403 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6937 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3597 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699331 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 821369 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2531234 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6937 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3597 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699331 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 821369 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2531234 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001009 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000854 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991594 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991594 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442656 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.442656 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010606 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010606 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023449 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023449 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001009 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010606 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.174503 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063749 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001009 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010606 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.174503 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063749 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84642.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84277.777778 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 192.775525 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 192.775525 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76422.426361 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76422.426361 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80080.452755 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80080.452755 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82705.316558 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82705.316558 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84642.857143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80080.452755 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76962.471482 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77311.133903 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84642.857143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80080.452755 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76962.471482 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77311.133903 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1011,167 +1018,177 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks -system.cpu.l2cache.writebacks::total 83215 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83304 # number of writebacks +system.cpu.l2cache.writebacks::total 83304 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2713 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2713 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131011 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131011 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 18023 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 18023 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12320 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12320 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 18023 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 161363 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 18023 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143331 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161363 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31142 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27594 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58736 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 522500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 146000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 668500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56418000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56418000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8702068500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8702068500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1263060000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1263060000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 895729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 895729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 522500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1263060000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9597798000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10861526500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 522500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1263060000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9597798000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10861526500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 564199000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5518638500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6082837500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4255261500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4255261500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 564199000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9773900000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10338099000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000854 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991594 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442656 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010606 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023449 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023449 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063749 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010606 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063749 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74277.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20795.429414 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66422.426361 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66422.426361 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70080.452755 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70080.452755 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72705.316558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72705.316558 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74642.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70080.452755 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66962.471482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67311.133903 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177208.865840 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 151449.992531 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154209.665145 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154209.665145 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62535.912215 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166403.909017 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 152573.851058 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2292179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1805693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2736 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53413 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3338113 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.019032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.136637 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699351 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2579570 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12812 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7701560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108793272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96436737 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14388 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27748 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205272145 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 179423 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5300588 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.035792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.185771 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3274582 98.10% 98.10% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 63531 1.90% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5110870 96.42% 96.42% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 189718 3.58% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3338113 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5300588 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3265127000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2558048500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1278361999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17827000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1262,23 +1279,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187438974 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134160 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 299040065000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134160 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070885 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070885 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1286,49 +1303,49 @@ system.iocache.tags.tag_accesses 328122 # Nu system.iocache.tags.data_accesses 328122 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4271537097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4271537097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117920.083287 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117920.083287 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1336,88 +1353,90 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460337097 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2460337097 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67920.083287 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67920.083287 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70719 # Transaction distribution -system.membus.trans_dist::ReadResp 70719 # Transaction distribution -system.membus.trans_dist::WriteReq 27589 # Transaction distribution -system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::Writeback 119405 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution +system.membus.trans_dist::ReadReq 40164 # Transaction distribution +system.membus.trans_dist::ReadResp 70750 # Transaction distribution +system.membus.trans_dist::WriteReq 27594 # Transaction distribution +system.membus.trans_dist::WriteResp 27594 # Transaction distribution +system.membus.trans_dist::Writeback 119494 # Transaction distribution +system.membus.trans_dist::CleanEvict 6493 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution -system.membus.trans_dist::ReadExReq 129241 # Transaction distribution -system.membus.trans_dist::ReadExResp 129241 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 129215 # Transaction distribution +system.membus.trans_dist::ReadExResp 129215 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30586 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662077 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15581884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15745273 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18062393 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 387734 # Request fanout histogram +system.membus.snoop_fanout::samples 394512 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 387734 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 394512 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 387734 # Request fanout histogram -system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 394512 # Request fanout histogram +system.membus.reqLayer0.occupancy 90495000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 834776313 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 964479239 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64484992 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 2cf9c3fee..948865e8c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,70 +4,70 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 898221 # Simulator instruction rate (inst/s) -host_op_rate 1093441 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17514028577 # Simulator tick rate (ticks/s) -host_mem_usage 560944 # Number of bytes of host memory used -host_seconds 158.95 # Real time elapsed on the host +host_inst_rate 1197854 # Simulator instruction rate (inst/s) +host_op_rate 1458195 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23356431621 # Simulator tick rate (ticks/s) +host_mem_usage 621348 # Number of bytes of host memory used +host_seconds 119.19 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 728356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 725796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660896 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 481216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 728356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837184 # Number of bytes written to this memory +system.physmem.bytes_read::total 11533000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 725796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 481216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8854708 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73345 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7519 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189289 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138081 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189176 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142462 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1674252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 172859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174427 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260715 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 172859 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175623 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180722 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181918 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680544 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 172859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034446 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324716 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -393,8 +393,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682283 # number of writebacks -system.cpu0.dcache.writebacks::total 682283 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682264 # number of writebacks +system.cpu0.dcache.writebacks::total 682264 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1699214 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use @@ -661,8 +661,7 @@ system.cpu1.kern.inst.quiesce 0 # nu system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 22778 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -729,24 +728,24 @@ system.iocache.tags.tag_accesses 328176 # Nu system.iocache.tags.data_accesses 328176 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses system.iocache.demand_misses::total 240 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 240 # number of overall misses system.iocache.overall_misses::total 240 # number of overall misses system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -762,28 +761,28 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 110020 # number of replacements -system.l2c.tags.tagsinuse 65155.309107 # Cycle average of tags in use -system.l2c.tags.total_refs 2731325 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175301 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.580772 # Average number of references to valid blocks. +system.l2c.tags.replacements 109907 # number of replacements +system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use +system.l2c.tags.total_refs 4567770 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.073532 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.438134 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.354241 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.333214 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5143.224775 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4734.504525 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4020.194257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.086137 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4025.377664 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2484.226979 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.076971 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078479 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072243 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061343 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037599 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061422 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037906 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id @@ -791,90 +790,90 @@ system.l2c.tags.age_task_id_blocks_1023::4 4 # system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26231874 # Number of tag accesses -system.l2c.tags.data_accesses 26231874 # Number of data accesses +system.l2c.tags.tag_accesses 40922425 # Number of tag accesses +system.l2c.tags.data_accesses 40922425 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847646 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 259121 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201277 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682283 # number of Writeback hits -system.l2c.Writeback_hits::total 682283 # number of Writeback hits +system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits +system.l2c.Writeback_hits::total 682264 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78543 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151058 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78631 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151146 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833751 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847665 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246350 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 259095 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.dtb.walker 4700 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833751 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318865 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 5001 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847646 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337664 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352335 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847665 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337726 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352448 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 4700 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833711 # number of overall hits -system.l2c.overall_hits::cpu0.data 318873 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833751 # number of overall hits +system.l2c.overall_hits::cpu0.data 318865 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847646 # number of overall hits -system.l2c.overall_hits::cpu1.data 337664 # number of overall hits -system.l2c.overall_hits::total 2352335 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847665 # number of overall hits +system.l2c.overall_hits::cpu1.data 337726 # number of overall hits +system.l2c.overall_hits::total 2352448 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10819 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 7538 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5759 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33894 # number of ReadReq misses +system.l2c.ReadReq_misses::total 8 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 63964 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83900 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83812 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 10779 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 7519 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9778 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5785 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10819 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73734 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10779 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73742 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7538 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89659 # number of demand (read+write) misses -system.l2c.demand_misses::total 181758 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7519 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89597 # number of demand (read+write) misses +system.l2c.demand_misses::total 181645 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10819 # number of overall misses -system.l2c.overall_misses::cpu0.data 73734 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10779 # number of overall misses +system.l2c.overall_misses::cpu0.data 73742 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7538 # number of overall misses -system.l2c.overall_misses::cpu1.data 89659 # number of overall misses -system.l2c.overall_misses::total 181758 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7519 # number of overall misses +system.l2c.overall_misses::cpu1.data 89597 # number of overall misses +system.l2c.overall_misses::total 181645 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 4705 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844530 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256128 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855184 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264880 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2235171 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682283 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682283 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) @@ -883,6 +882,12 @@ system.l2c.SCUpgradeReq_accesses::total 2 # nu system.l2c.ReadExReq_accesses::cpu0.data 136479 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 162443 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 844530 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855184 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 256128 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264880 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 4705 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.inst 844530 # number of demand (read+write) accesses @@ -903,36 +908,38 @@ system.l2c.overall_accesses::cpu1.data 427323 # nu system.l2c.overall_accesses::total 2534093 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.012811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038145 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008814 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000554 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.516489 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515947 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012763 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008792 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038176 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021840 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012763 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187827 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008814 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209816 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071725 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008792 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209670 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071680 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012763 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187827 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008814 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209816 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071725 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008792 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209670 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071680 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -941,49 +948,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101891 # number of writebacks -system.l2c.writebacks::total 101891 # number of writebacks +system.l2c.writebacks::writebacks 101943 # number of writebacks +system.l2c.writebacks::total 101943 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74221 # Transaction distribution -system.membus.trans_dist::ReadResp 74221 # Transaction distribution +system.membus.trans_dist::ReadReq 40087 # Transaction distribution +system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::Writeback 138081 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::Writeback 138133 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 146085 # Transaction distribution -system.membus.trans_dist::ReadExResp 146085 # Transaction distribution +system.membus.trans_dist::ReadExReq 145997 # Transaction distribution +system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606133 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095548 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258521 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091644 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254617 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586137 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 426666 # Request fanout histogram +system.membus.snoop_fanout::samples 434809 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 426666 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 434809 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426666 # Request fanout histogram +system.membus.snoop_fanout::total 434809 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1015,37 +1024,40 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682283 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1836352 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444881 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116722 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2582000 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924703 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7761036 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3339957 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.020246 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.140841 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 5176290 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013064 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.113547 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3272336 97.98% 97.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 67621 2.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5108669 98.69% 98.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 67621 1.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3339957 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5176290 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 5b65637a2..505a1af3b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903641 # Number of seconds simulated -sim_ticks 2903640922500 # Number of ticks simulated -final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903518 # Number of seconds simulated +sim_ticks 2903517798500 # Number of ticks simulated +final_tick 2903517798500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 541770 # Simulator instruction rate (inst/s) -host_op_rate 653210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13988619879 # Simulator tick rate (ticks/s) -host_mem_usage 561968 # Number of bytes of host memory used -host_seconds 207.57 # Real time elapsed on the host -sim_insts 112456119 # Number of instructions simulated -sim_ops 135587804 # Number of ops (including micro ops) simulated +host_inst_rate 707460 # Simulator instruction rate (inst/s) +host_op_rate 852978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18263496849 # Simulator tick rate (ticks/s) +host_mem_usage 621100 # Number of bytes of host memory used +host_seconds 158.98 # Real time elapsed on the host +sim_insts 112471533 # Number of instructions simulated +sim_ops 135605825 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 588836 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3938784 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 600704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5102020 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory +system.physmem.bytes_read::total 10231944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 588836 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 600704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1189540 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7646016 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7663540 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17654 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 62062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 79720 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168847 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119469 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 123850 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 202801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1356556 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 206888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1757186 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3523982 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 202801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 206888 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 409689 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2633363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6033 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2639398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2633363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 202801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1362589 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 206888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1757188 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165551 # Number of read requests accepted -system.physmem.writeReqs 156772 # Number of write requests accepted -system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9899 # Per bank write bursts -system.physmem.perBankRdBursts::1 9526 # Per bank write bursts -system.physmem.perBankRdBursts::2 9759 # Per bank write bursts -system.physmem.perBankRdBursts::3 9793 # Per bank write bursts -system.physmem.perBankRdBursts::4 18999 # Per bank write bursts -system.physmem.perBankRdBursts::5 10033 # Per bank write bursts -system.physmem.perBankRdBursts::6 10462 # Per bank write bursts -system.physmem.perBankRdBursts::7 10803 # Per bank write bursts -system.physmem.perBankRdBursts::8 9925 # Per bank write bursts -system.physmem.perBankRdBursts::9 10243 # Per bank write bursts -system.physmem.perBankRdBursts::10 9858 # Per bank write bursts -system.physmem.perBankRdBursts::11 9250 # Per bank write bursts -system.physmem.perBankRdBursts::12 9247 # Per bank write bursts -system.physmem.perBankRdBursts::13 9475 # Per bank write bursts -system.physmem.perBankRdBursts::14 9028 # Per bank write bursts -system.physmem.perBankRdBursts::15 9149 # Per bank write bursts -system.physmem.perBankWrBursts::0 8258 # Per bank write bursts -system.physmem.perBankWrBursts::1 8244 # Per bank write bursts -system.physmem.perBankWrBursts::2 8572 # Per bank write bursts -system.physmem.perBankWrBursts::3 8149 # Per bank write bursts -system.physmem.perBankWrBursts::4 8563 # Per bank write bursts -system.physmem.perBankWrBursts::5 8536 # Per bank write bursts -system.physmem.perBankWrBursts::6 8718 # Per bank write bursts -system.physmem.perBankWrBursts::7 9117 # Per bank write bursts -system.physmem.perBankWrBursts::8 8657 # Per bank write bursts -system.physmem.perBankWrBursts::9 8771 # Per bank write bursts -system.physmem.perBankWrBursts::10 8610 # Per bank write bursts -system.physmem.perBankWrBursts::11 7990 # Per bank write bursts -system.physmem.perBankWrBursts::12 7949 # Per bank write bursts -system.physmem.perBankWrBursts::13 7964 # Per bank write bursts -system.physmem.perBankWrBursts::14 7531 # Per bank write bursts -system.physmem.perBankWrBursts::15 7537 # Per bank write bursts +system.physmem.bw_total::total 6163380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168847 # Number of read requests accepted +system.physmem.writeReqs 123850 # Number of write requests accepted +system.physmem.readBursts 168847 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123850 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10798016 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue +system.physmem.bytesWritten 7677504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10231944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7663540 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40733 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10014 # Per bank write bursts +system.physmem.perBankRdBursts::1 9659 # Per bank write bursts +system.physmem.perBankRdBursts::2 10299 # Per bank write bursts +system.physmem.perBankRdBursts::3 9948 # Per bank write bursts +system.physmem.perBankRdBursts::4 18863 # Per bank write bursts +system.physmem.perBankRdBursts::5 10091 # Per bank write bursts +system.physmem.perBankRdBursts::6 10301 # Per bank write bursts +system.physmem.perBankRdBursts::7 10599 # Per bank write bursts +system.physmem.perBankRdBursts::8 9915 # Per bank write bursts +system.physmem.perBankRdBursts::9 10209 # Per bank write bursts +system.physmem.perBankRdBursts::10 9947 # Per bank write bursts +system.physmem.perBankRdBursts::11 9027 # Per bank write bursts +system.physmem.perBankRdBursts::12 9869 # Per bank write bursts +system.physmem.perBankRdBursts::13 10471 # Per bank write bursts +system.physmem.perBankRdBursts::14 9980 # Per bank write bursts +system.physmem.perBankRdBursts::15 9527 # Per bank write bursts +system.physmem.perBankWrBursts::0 7419 # Per bank write bursts +system.physmem.perBankWrBursts::1 7262 # Per bank write bursts +system.physmem.perBankWrBursts::2 8122 # Per bank write bursts +system.physmem.perBankWrBursts::3 7539 # Per bank write bursts +system.physmem.perBankWrBursts::4 7355 # Per bank write bursts +system.physmem.perBankWrBursts::5 7348 # Per bank write bursts +system.physmem.perBankWrBursts::6 7576 # Per bank write bursts +system.physmem.perBankWrBursts::7 7905 # Per bank write bursts +system.physmem.perBankWrBursts::8 7603 # Per bank write bursts +system.physmem.perBankWrBursts::9 7846 # Per bank write bursts +system.physmem.perBankWrBursts::10 7540 # Per bank write bursts +system.physmem.perBankWrBursts::11 6940 # Per bank write bursts +system.physmem.perBankWrBursts::12 7394 # Per bank write bursts +system.physmem.perBankWrBursts::13 7835 # Per bank write bursts +system.physmem.perBankWrBursts::14 7358 # Per bank write bursts +system.physmem.perBankWrBursts::15 6919 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 32 # Number of times write queue was full causing retry -system.physmem.totGap 2903640597500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2903517476500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155979 # Read request sizes (log2) +system.physmem.readPktSize::6 159275 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 152391 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see +system.physmem.writePktSize::6 119469 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,183 +161,178 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 195 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 59278 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.674753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.487125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.482596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21806 36.79% 36.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14989 25.29% 62.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5586 9.42% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3267 5.51% 77.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2330 3.93% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1628 2.75% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1108 1.87% 85.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1064 1.79% 87.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7500 12.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59278 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5882 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.683781 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 547.352228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5880 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads -system.physmem.totQLat 1437662314 # Total ticks spent queuing -system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5882 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.394594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.624984 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.894436 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.27% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 8 0.14% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 7 0.12% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.17% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4921 83.66% 84.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 66 1.12% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 241 4.10% 89.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 88 1.50% 91.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 77 1.31% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 178 3.03% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 14 0.24% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 13 0.22% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 174 2.96% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.24% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads +system.physmem.totQLat 1493162250 # Total ticks spent queuing +system.physmem.totMemAccLat 4656643500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8849.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27599.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.64 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing -system.physmem.readRowHits 136363 # Number of row buffer hits during reads -system.physmem.writeRowHits 104375 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes -system.physmem.avgGap 9008480.93 # Average gap between requests -system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.506799 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states -system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem.avgWrQLen 12.20 # Average write queue length when enqueuing +system.physmem.readRowHits 138806 # Number of row buffer hits during reads +system.physmem.writeRowHits 90595 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.52 # Row buffer hit rate for writes +system.physmem.avgGap 9919874.40 # Average gap between requests +system.physmem.pageHitRate 79.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229302360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125115375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700237200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392208480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87298782345 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665531858750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943921054190 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.505834 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770598960250 # Time in different power states +system.physmem_0.memoryStateTime::REF 96954780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35962503500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.365444 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states -system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states +system.physmem_1.actEnergy 218839320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119406375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615763200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385138800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189643549680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 86123693430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666562638500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943669029305 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.419034 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772326743250 # Time in different power states +system.physmem_1.memoryStateTime::REF 96954780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34236177250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -387,56 +382,60 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6899 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6827 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6827 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2216 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4610 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6826 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6826 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12342.983063 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10713.852920 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6703.217150 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4631 80.04% 80.04% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1152 19.91% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -1209080312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.765375 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 925400000 -76.54% -76.54% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -2134480312 176.54% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -1209080312 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3595 62.14% 62.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2190 37.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5785 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6827 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6827 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5785 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5785 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12612 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12462635 # DTB read hits -system.cpu0.dtb.read_misses 5988 # DTB read misses -system.cpu0.dtb.write_hits 9832923 # DTB write hits -system.cpu0.dtb.write_misses 911 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12507441 # DTB read hits +system.cpu0.dtb.read_misses 5917 # DTB read misses +system.cpu0.dtb.write_hits 9856816 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4603 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12468623 # DTB read accesses -system.cpu0.dtb.write_accesses 9833834 # DTB write accesses +system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12513358 # DTB read accesses +system.cpu0.dtb.write_accesses 9857726 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22295558 # DTB hits -system.cpu0.dtb.misses 6899 # DTB misses -system.cpu0.dtb.accesses 22302457 # DTB accesses +system.cpu0.dtb.hits 22364257 # DTB hits +system.cpu0.dtb.misses 6827 # DTB misses +system.cpu0.dtb.accesses 22371084 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -466,456 +465,457 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3577 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3521 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3521 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 830 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2691 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3521 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3521 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3521 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2670 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12834.082397 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11032.722243 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6917.920498 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 769 28.80% 28.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1283 48.05% 76.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 616 23.07% 99.93% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 2670 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 925066000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 925066000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 925066000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1840 68.91% 68.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 830 31.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2670 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3521 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3521 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58414032 # ITB inst hits -system.cpu0.itb.inst_misses 3577 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6191 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58595537 # ITB inst hits +system.cpu0.itb.inst_misses 3521 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 486 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2691 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses -system.cpu0.itb.hits 58414032 # DTB hits -system.cpu0.itb.misses 3577 # DTB misses -system.cpu0.itb.accesses 58417609 # DTB accesses -system.cpu0.numCycles 2904051621 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58599058 # ITB inst accesses +system.cpu0.itb.hits 58595537 # DTB hits +system.cpu0.itb.misses 3521 # DTB misses +system.cpu0.itb.accesses 58599058 # DTB accesses +system.cpu0.numCycles 2904052506 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56844590 # Number of instructions committed -system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses -system.cpu0.num_func_calls 5072041 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60556147 # number of integer instructions -system.cpu0.num_fp_insts 5891 # number of float instructions -system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written -system.cpu0.num_mem_refs 22952183 # number of memory refs -system.cpu0.num_load_insts 12628752 # Number of load instructions -system.cpu0.num_store_insts 10323431 # Number of store instructions -system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles -system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles -system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles -system.cpu0.Branches 13135796 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction -system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction +system.cpu0.committedInsts 57017963 # Number of instructions committed +system.cpu0.committedOps 68702056 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60736686 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5415 # Number of float alu accesses +system.cpu0.num_func_calls 5101109 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7710665 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60736686 # number of integer instructions +system.cpu0.num_fp_insts 5415 # number of float instructions +system.cpu0.num_int_register_reads 110496547 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42022968 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4193 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 248490103 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26091255 # number of times the CC registers were written +system.cpu0.num_mem_refs 23020484 # number of memory refs +system.cpu0.num_load_insts 12672781 # Number of load instructions +system.cpu0.num_store_insts 10347703 # Number of store instructions +system.cpu0.num_idle_cycles 2689228469.175671 # Number of idle cycles +system.cpu0.num_busy_cycles 214824036.824329 # Number of busy cycles +system.cpu0.not_idle_fraction 0.073974 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.926026 # Percentage of idle cycles +system.cpu0.Branches 13203328 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2205 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 47217639 67.16% 67.16% # Class of executed instruction +system.cpu0.op_class::IntMult 59885 0.09% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4420 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 12672781 18.03% 85.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 10347703 14.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 70074060 # Class of executed instruction +system.cpu0.op_class::total 70304633 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 821716 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3029 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 820099 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.829843 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43241744 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 820611 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.694570 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 996611500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 401.515698 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 110.314145 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.784210 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.215457 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392193 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230728 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212742 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443470 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239351 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220930 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21180712 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20754848 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935560 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21381097 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20946656 # number of overall hits -system.cpu0.dcache.overall_hits::total 42327753 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 202379 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199779 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402158 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155169 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298475 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 60388 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58192 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118580 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11633 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 10971 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22604 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 177137427 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177137427 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11786116 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11329399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23115515 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9461522 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9365348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18826870 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201006 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191753 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392759 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 231308 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212173 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443481 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239891 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220488 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460379 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 21247638 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20694747 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41942385 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21448644 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 20886500 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335144 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 202704 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 197921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 400625 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 143580 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155041 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298621 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 59413 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58849 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118262 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11581 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11100 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22681 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345685 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 354948 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 700633 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 406073 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 413140 # number of overall misses -system.cpu0.dcache.overall_misses::total 819213 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2998718242 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2978169130 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5976887372 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5523492960 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6886936529 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12410429489 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144593750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 135344000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 279937750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 346284 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 352962 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 699246 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 405697 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 411811 # number of overall misses +system.cpu0.dcache.overall_misses::total 817508 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3011302500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2950015000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5961317500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5623507500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6931365000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12554872500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144229500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 137062000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 281291500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 164000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8522211202 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9865105659 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18387316861 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8522211202 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9865105659 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18387316861 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11944486 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11568092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23512578 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9581911 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9541704 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19123615 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260773 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250000 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 510773 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242361 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223713 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466074 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239353 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220930 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21526397 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21109796 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42636193 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21787170 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21359796 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43146966 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016943 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017270 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017104 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014956 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016262 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015608 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231573 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.232768 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232158 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047999 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_latency::cpu0.data 8634810000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9881380000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18516190000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8634810000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9881380000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18516190000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11988820 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11527320 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23516140 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9605102 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9520389 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19125491 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260419 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250602 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511021 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223273 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466162 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239893 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220488 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460381 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21593922 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21047709 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42641631 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21854341 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21298311 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43152652 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016908 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017170 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017036 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014948 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016285 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015614 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.228144 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.234831 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231423 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047680 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049715 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048655 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016059 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016814 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016433 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018638 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019342 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018987 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016036 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016770 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018564 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019335 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018945 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14855.663924 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14905.012606 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14880.043682 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39166.370664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44706.658239 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42042.831884 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12453.976341 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12347.927928 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12402.076628 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24935.630869 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27995.591593 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26480.222983 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21283.889208 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23994.939426 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22649.552053 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 687030 # number of writebacks -system.cpu0.dcache.writebacks::total 687030 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 373 # number of ReadReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 683625 # number of writebacks +system.cpu0.dcache.writebacks::total 683625 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 291 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 369 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 660 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7066 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7026 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14092 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 373 # number of demand (read+write) MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7077 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7054 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14131 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 291 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 369 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 373 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 291 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 369 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202092 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199406 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 401498 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143306 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155169 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298475 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 59468 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57033 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116501 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4567 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 3945 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8512 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202413 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 197552 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 399965 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143580 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155041 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298621 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58532 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57717 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116249 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4504 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4046 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8550 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 345398 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 354575 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 699973 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5284681040 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6621405971 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11906087011 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 749127008 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 719245636 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1468372644 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55884250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 49619250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 105503500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7972531040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9293189221 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17265720261 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8721658048 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10012434857 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 345993 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 352593 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 698586 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404525 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 410310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 814835 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15867 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15271 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15968 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11621 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31835 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26892 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2803165500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2746358000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5549523500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5479927500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6776324000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12256251500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 768422500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 755594500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1524017000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 57248500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52551500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109800000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 162000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8283093000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9522682000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17805775000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9051515500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10278276500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 19329792000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2904028500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3003756000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5907784500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2320925500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2251479500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4572405000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5224954000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5255235500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10480189500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016883 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017138 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017008 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014948 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015614 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224761 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.230313 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227484 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.018121 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018341 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016023 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016383 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018510 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019265 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018883 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13848.742423 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13901.949866 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13875.022814 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38166.370664 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43706.658239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41042.831884 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13128.246088 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13091.368228 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13109.936430 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12710.590586 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12988.507168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12842.105263 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23940.059481 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27007.575306 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25488.307810 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22375.664050 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25050.026809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23722.338878 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183023.161278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196696.745465 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189729.093070 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145348.540832 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 193742.319938 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165732.900794 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 164126.087639 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 195420.031980 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178456.067907 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1701384 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1697906 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.737364 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113870601 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698418 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.045098 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25672110500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 416.223441 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.513923 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.812936 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184598 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997534 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits -system.cpu0.icache.overall_hits::total 113852033 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses -system.cpu0.icache.overall_misses::total 1701902 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117267449 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117267449 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57739156 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56131445 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113870601 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57739156 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56131445 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113870601 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57739156 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56131445 # number of overall hits +system.cpu0.icache.overall_hits::total 113870601 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 856381 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 842043 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1698424 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 856381 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 842043 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1698424 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 856381 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 842043 # number of overall misses +system.cpu0.icache.overall_misses::total 1698424 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11736376500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11602280500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23338657000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11736376500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11602280500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23338657000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11736376500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11602280500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23338657000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 58595537 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 56973488 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115569025 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 58595537 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 56973488 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115569025 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58595537 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 56973488 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115569025 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014615 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014780 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014615 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014780 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014615 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014780 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13704.620373 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.726858 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13741.360814 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13704.620373 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.726858 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13741.360814 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13704.620373 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.726858 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13741.360814 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,54 +924,54 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856381 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 842043 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698424 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856381 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 842043 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698424 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856381 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 842043 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698424 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10879995500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10760237500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21640233000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10879995500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10760237500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21640233000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10879995500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10760237500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21640233000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 676974000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 676974000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 676974000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014615 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014780 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12741.360814 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12704.620373 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12778.726858 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12741.360814 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75035.912215 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75035.912215 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75035.912215 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1002,60 +1002,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6646 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6604 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6604 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1835 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4768 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::samples 6603 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6603 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6603 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12293.559569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10651.112974 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6472.015315 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1651 30.12% 30.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2769 50.52% 80.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1058 19.30% 99.95% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkCompletionTime::total 5481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1004634564 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.995586 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::0 1000200000 -99.56% -99.56% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -2004834564 199.56% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1004634564 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3666 66.90% 66.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1814 33.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5480 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6604 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6604 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5480 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12084 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12057381 # DTB read hits -system.cpu1.dtb.read_misses 5757 # DTB read misses -system.cpu1.dtb.write_hits 9774636 # DTB write hits -system.cpu1.dtb.write_misses 889 # DTB write misses -system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12016469 # DTB read hits +system.cpu1.dtb.read_misses 5667 # DTB read misses +system.cpu1.dtb.write_hits 9752712 # DTB write hits +system.cpu1.dtb.write_misses 937 # DTB write misses +system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4084 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12063138 # DTB read accesses -system.cpu1.dtb.write_accesses 9775525 # DTB write accesses +system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12022136 # DTB read accesses +system.cpu1.dtb.write_accesses 9753649 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 21832017 # DTB hits -system.cpu1.dtb.misses 6646 # DTB misses -system.cpu1.dtb.accesses 21838663 # DTB accesses +system.cpu1.dtb.hits 21769181 # DTB hits +system.cpu1.dtb.misses 6604 # DTB misses +system.cpu1.dtb.accesses 21775785 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1085,124 +1085,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3230 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walks 3234 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3234 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 677 # Level at which table walker walks with short descriptors terminate system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::samples 3234 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3234 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3234 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2430 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12793.004115 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11015.336185 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6613.791032 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 712 29.30% 29.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.04% 29.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.70% 57.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 477 19.63% 76.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 16 0.66% 77.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 551 22.67% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2430 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1753 72.14% 72.14% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 677 27.86% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3234 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3234 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 57139903 # ITB inst hits -system.cpu1.itb.inst_misses 3230 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5664 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 56973488 # ITB inst hits +system.cpu1.itb.inst_misses 3234 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 431 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2428 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses -system.cpu1.itb.hits 57139903 # DTB hits -system.cpu1.itb.misses 3230 # DTB misses -system.cpu1.itb.accesses 57143133 # DTB accesses -system.cpu1.numCycles 2903230224 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 56976722 # ITB inst accesses +system.cpu1.itb.hits 56973488 # DTB hits +system.cpu1.itb.misses 3234 # DTB misses +system.cpu1.itb.accesses 56976722 # DTB accesses +system.cpu1.numCycles 2902983091 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55611529 # Number of instructions committed -system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses -system.cpu1.num_func_calls 4819801 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59336824 # number of integer instructions -system.cpu1.num_fp_insts 5270 # number of float instructions -system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read -system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written -system.cpu1.num_mem_refs 22456627 # number of memory refs -system.cpu1.num_load_insts 12214155 # Number of load instructions -system.cpu1.num_store_insts 10242472 # Number of store instructions -system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles -system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles -system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles -system.cpu1.Branches 12781357 # Number of branches fetched -system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction -system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction -system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction -system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55453570 # Number of instructions committed +system.cpu1.committedOps 66903769 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59172733 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5746 # Number of float alu accesses +system.cpu1.num_func_calls 4791563 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7521701 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59172733 # number of integer instructions +system.cpu1.num_fp_insts 5746 # number of float instructions +system.cpu1.num_int_register_reads 107592864 # number of times the integer registers were read +system.cpu1.num_int_register_writes 40634379 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4256 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 241317525 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25809860 # number of times the CC registers were written +system.cpu1.num_mem_refs 22393766 # number of memory refs +system.cpu1.num_load_insts 12173697 # Number of load instructions +system.cpu1.num_store_insts 10220069 # Number of store instructions +system.cpu1.num_idle_cycles 2697480671.520393 # Number of idle cycles +system.cpu1.num_busy_cycles 205502419.479607 # Number of busy cycles +system.cpu1.not_idle_fraction 0.070790 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.929210 # Percentage of idle cycles +system.cpu1.Branches 12715726 # Number of branches fetched +system.cpu1.op_class::No_OpClass 132 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 45969122 67.18% 67.19% # Class of executed instruction +system.cpu1.op_class::IntMult 54656 0.08% 67.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4033 0.01% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu1.op_class::MemRead 12173697 17.79% 85.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 10220069 14.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 68634629 # Class of executed instruction +system.cpu1.op_class::total 68421709 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1293,23 +1293,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187451467 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079135 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309074032000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079135 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067446 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067446 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1317,49 +1317,49 @@ system.iocache.tags.tag_accesses 328122 # Nu system.iocache.tags.data_accesses 328122 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28776877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28776877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4271859590 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4271859590 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28776877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28776877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28776877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28776877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 122978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122978.106838 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117928.986031 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117928.986031 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 122978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1367,272 +1367,284 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17076877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17076877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2460659590 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2460659590 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17076877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17076877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17076877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72501.611111 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72501.611111 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72978.106838 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72978.106838 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67928.986031 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67928.986031 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72978.106838 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72978.106838 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 86345 # number of replacements -system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use -system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. +system.l2c.tags.replacements 89754 # number of replacements +system.l2c.tags.tagsinuse 64926.218037 # Cycle average of tags in use +system.l2c.tags.total_refs 4554949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154987 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.389233 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50375.736083 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.809030 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965062 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4670.410821 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2880.132547 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.905198 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4955.443121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2037.816176 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.768673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.068705 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.071265 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043947 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.078707 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.032658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990548 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26318997 # Number of tag accesses -system.l2c.tags.data_accesses 26318997 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits -system.l2c.Writeback_hits::total 687030 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits -system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits -system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits -system.l2c.overall_hits::cpu0.data 347622 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits -system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits -system.l2c.overall_hits::cpu1.data 334576 # number of overall hits -system.l2c.overall_hits::total 2385600 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.075614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990695 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2130 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6959 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56093 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995285 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40606108 # Number of tag accesses +system.l2c.tags.data_accesses 40606108 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3120 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5525 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2899 # number of ReadReq hits +system.l2c.ReadReq_hits::total 17310 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 683625 # number of Writeback hits +system.l2c.Writeback_hits::total 683625 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 85842 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 79037 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 164879 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 847732 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 832646 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1680378 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 259316 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 253156 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 512472 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5766 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3120 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 847732 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 345158 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5525 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2899 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 832646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 332193 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375039 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5766 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3120 # number of overall hits +system.l2c.overall_hits::cpu0.inst 847732 # number of overall hits +system.l2c.overall_hits::cpu0.data 345158 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5525 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2899 # number of overall hits +system.l2c.overall_hits::cpu1.inst 832646 # number of overall hits +system.l2c.overall_hits::cpu1.data 332193 # number of overall hits +system.l2c.overall_hits::total 2375039 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8541 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5976 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9421 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6147 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30094 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2703 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 10 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1366 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1349 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 54481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73452 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 127933 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 56359 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 74645 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 131004 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 8639 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 9386 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 18025 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 6133 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 6159 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 12292 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8541 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 60457 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8639 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 62492 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9421 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 79599 # number of demand (read+write) misses -system.l2c.demand_misses::total 158027 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.demand_misses::cpu1.inst 9386 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 80804 # number of demand (read+write) misses +system.l2c.demand_misses::total 161331 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8541 # number of overall misses -system.l2c.overall_misses::cpu0.data 60457 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8639 # number of overall misses +system.l2c.overall_misses::cpu0.data 62492 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9421 # number of overall misses -system.l2c.overall_misses::cpu1.data 79599 # number of overall misses -system.l2c.overall_misses::total 158027 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 261750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 166000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 681157002 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 494631258 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 330000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 753847500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 510531136 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2440924646 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 341989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 434486 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 776475 # number of UpgradeReq miss cycles +system.l2c.overall_misses::cpu1.inst 9386 # number of overall misses +system.l2c.overall_misses::cpu1.data 80804 # number of overall misses +system.l2c.overall_misses::total 161331 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 331000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 405000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 901500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 277500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 246000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 523500 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu0.data 159000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4180870378 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5579789336 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9760659714 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 261750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 681157002 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4675501636 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 330000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 753847500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6090320472 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12201584360 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 261750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 681157002 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4675501636 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 330000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 753847500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6090320472 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12201584360 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 6508 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3516 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 856639 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 266127 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6221 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3258 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 845231 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 260384 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2247884 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 687030 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 687030 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1378 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2732 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_miss_latency::cpu0.data 4321008500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5672212000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9993220500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 690948000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 751164500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1442112500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 507685500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 507256000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1014941500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 331000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 165500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 690948000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4828694000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 405000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 751164500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6179468000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12451176000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 331000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 165500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 690948000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4828694000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 405000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 751164500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6179468000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12451176000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5770 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3122 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5529 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2899 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 17320 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 683625 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 683625 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1379 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2738 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141952 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 153791 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295743 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 6508 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 856639 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 408079 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6221 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3258 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 845231 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 414175 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2543627 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6508 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 856639 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 408079 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6221 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3258 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 845231 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 414175 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2543627 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000569 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009970 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.022455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011146 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023607 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013388 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988183 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990566 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989385 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 142201 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 153682 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295883 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 856371 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 842032 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1698403 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 265449 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 259315 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 524764 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5770 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3122 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 856371 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 407650 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5529 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2899 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 842032 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 412997 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2536370 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5770 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3122 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 856371 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 407650 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5529 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2899 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 842032 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 412997 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2536370 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000693 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000641 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000723 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000577 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990573 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992642 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991600 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.383799 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.477609 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.432582 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000569 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009970 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.148150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011146 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.192187 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062127 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000569 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009970 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.148150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011146 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.192187 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062127 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 82769.621486 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 81110.010168 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 255.597160 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 318.304762 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 287.264151 # average UpgradeReq miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.396333 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.485711 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.442756 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010088 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011147 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010613 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.023104 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.023751 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023424 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000693 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010088 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.153298 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011147 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.195653 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063607 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000693 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010088 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.153298 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011147 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.195653 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063607 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 82750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 101250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 90150 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 203.147877 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 182.357302 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 192.817680 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76295.089727 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 77212.023009 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 77212.023009 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76669.360705 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75989.175430 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76281.796739 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 79980.090288 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80030.311102 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 80006.241331 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 82779.308658 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82360.123397 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 82569.272698 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79980.090288 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77268.994431 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80030.311102 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76474.778476 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77177.826952 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79980.090288 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77268.994431 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80030.311102 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76474.778476 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77177.826952 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1641,221 +1653,231 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79977 # number of writebacks -system.l2c.writebacks::total 79977 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 83279 # number of writebacks +system.l2c.writebacks::total 83279 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 8541 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5976 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9421 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6147 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 30094 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1338 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2703 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1366 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1349 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2715 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 54481 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73452 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 127933 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 56359 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 74645 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 131004 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8639 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9386 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 18025 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6133 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6159 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 12292 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8541 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 60457 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8639 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 62492 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9421 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 79599 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 158027 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9386 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 80804 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 161331 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8541 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 60457 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8639 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 62492 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9386 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 80804 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 161331 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15867 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15271 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15968 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11621 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 419922242 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 635806000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 433639364 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2064154854 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 23826338 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24325865 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 48152203 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3498745622 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4660357664 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8159103286 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 223750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 141000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 574142498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3918667864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 280000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 635806000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5093997028 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10223258140 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 223750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 141000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 574142498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3918667864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 280000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 635806000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5093997028 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10223258140 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 546237750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2603822250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 546237750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4658294250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4892937500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.022455 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990566 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31835 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26892 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 291000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 365000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 801500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 28392000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28047500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 56439500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 139000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3757418500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4925762000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8683180500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 604558000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 657304500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1261862500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 446355500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 445666000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 892021500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 291000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 604558000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4203774000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 365000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 657304500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5371428000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10837866000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 291000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 604558000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4203774000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 365000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 657304500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5371428000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10837866000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 564199000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2705690000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2812868500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6082757500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2137293500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2117838000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4255131500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 564199000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4842983500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4930706500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10337889000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000577 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990573 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992642 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.485711 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.442756 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010613 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.023104 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.023751 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023424 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063607 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.153298 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000723 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011147 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.195653 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063607 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 80150 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20784.773060 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.326909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20788.029466 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66669.360705 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65989.175430 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66281.796739 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70006.241331 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 72779.308658 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72360.123397 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 72569.272698 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69980.090288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 67268.994431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70030.311102 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66474.778476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67177.826952 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170523.098254 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184196.745465 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151463.085159 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133848.540832 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182242.319938 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154232.900794 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62535.912215 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152127.642532 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 183352.167931 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 152591.019794 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70492 # Transaction distribution -system.membus.trans_dist::ReadResp 70492 # Transaction distribution -system.membus.trans_dist::WriteReq 27594 # Transaction distribution -system.membus.trans_dist::WriteResp 27594 # Transaction distribution -system.membus.trans_dist::Writeback 116167 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution +system.membus.trans_dist::ReadReq 40160 # Transaction distribution +system.membus.trans_dist::ReadResp 70721 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 119469 # Transaction distribution +system.membus.trans_dist::CleanEvict 6488 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution -system.membus.trans_dist::ReadExReq 126147 # Transaction distribution -system.membus.trans_dist::ReadExResp 126147 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 129210 # Transaction distribution +system.membus.trans_dist::ReadExResp 129210 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30561 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 445477 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 553069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 661969 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15578364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15741717 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18058837 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 381147 # Request fanout histogram +system.membus.snoop_fanout::samples 394437 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 394437 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 381147 # Request fanout histogram -system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 394437 # Request fanout histogram +system.membus.reqLayer0.occupancy 90486000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1696500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 834684564 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 964305240 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64480996 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1888,50 +1910,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74970 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2298377 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 803098 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1802826 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 52269 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295883 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295883 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1698424 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 524998 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5081680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2577380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7711190 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108733880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96470557 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24084 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45196 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205273717 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180370 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5305015 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.037219 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.189299 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5107565 96.28% 96.28% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 197450 3.72% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5305015 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3268607000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2556658000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1277273499 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12003000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22807000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 131e14cd8..fee5e3090 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,50 +4,50 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1219492 # Simulator instruction rate (inst/s) -host_op_rate 2496566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31160731508 # Simulator tick rate (ticks/s) -host_mem_usage 598628 # Number of bytes of host memory used -host_seconds 164.06 # Real time elapsed on the host +host_inst_rate 1340669 # Simulator instruction rate (inst/s) +host_op_rate 2744641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34257071569 # Simulator tick rate (ticks/s) +host_mem_usage 654012 # Number of bytes of host memory used +host_seconds 149.23 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 854656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10616192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 853568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10615616 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11499584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 854656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 854656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9265728 # Number of bytes written to this memory -system.physmem.bytes_written::total 9265728 # Number of bytes written to this memory +system.physmem.bytes_read::total 11497920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 853568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 853568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9269440 # Number of bytes written to this memory +system.physmem.bytes_written::total 9269440 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165878 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 13337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165869 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179681 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144777 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144777 # Number of write requests responded to by this memory +system.physmem.num_reads::total 179655 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144835 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144835 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 167181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2076658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2076545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2249460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 167181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 167181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1812491 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1812491 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1812491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2249135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1813217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813217 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1813217 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 167181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2076658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 166968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2076545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4061951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4062352 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 10224308568 # number of cpu cycles simulated @@ -176,8 +176,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535783 # number of writebacks -system.cpu.dcache.writebacks::total 1535783 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535779 # number of writebacks +system.cpu.dcache.writebacks::total 1535779 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use @@ -335,22 +335,22 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 106219 # number of replacements +system.cpu.l2cache.tags.replacements 106193 # number of replacements system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3459867 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170177 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.330991 # Average number of references to valid blocks. +system.cpu.l2cache.tags.total_refs 4345511 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.539145 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132289 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2455.813677 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792375 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2531.452775 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.791178 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037473 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.159285 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038627 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.159327 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id @@ -359,59 +359,62 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32212786 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32212786 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6656 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2896 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779367 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1275199 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 39306136 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39306136 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179780 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179780 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779384 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 779384 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275199 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1284751 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779367 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454970 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2243889 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779384 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454979 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2243915 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779367 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454970 # number of overall hits -system.cpu.l2cache.overall_hits::total 2243889 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.inst 779384 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454979 # number of overall hits +system.cpu.l2cache.overall_hits::total 2243915 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 134641 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 134641 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13338 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 13338 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32163 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 32169 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 13355 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 166813 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 180174 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 13338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 166804 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 180148 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 13355 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 166813 # number of overall misses -system.cpu.l2cache.overall_misses::total 180174 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6657 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2901 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 792722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307362 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109642 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 13338 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 166804 # number of overall misses +system.cpu.l2cache.overall_misses::total 180148 # number of overall misses +system.cpu.l2cache.Writeback_accesses::writebacks 1538777 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1538777 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792722 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 792722 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6657 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2901 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307362 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1316920 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses @@ -422,25 +425,26 @@ system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428219 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428219 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016826 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024601 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024427 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016847 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102858 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074327 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016826 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102852 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074317 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016847 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102858 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074327 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016826 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102852 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074317 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,47 +453,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98110 # number of writebacks -system.cpu.l2cache.writebacks::total 98110 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks +system.cpu.l2cache.writebacks::total 98168 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 15971490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1538781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 886676 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585470 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32527769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20367 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 34143061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377686 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613888 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35029733 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550521 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 49698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 17890240 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.002757 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.052432 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18776912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051183 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 17840921 99.72% 99.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49319 0.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 18727593 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 49319 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 17890240 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18776912 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution -system.iobus.trans_dist::WriteResp 11004 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::WriteResp 57724 # Transaction distribution system.iobus.trans_dist::MessageReq 1696 # Transaction distribution system.iobus.trans_dist::MessageResp 1696 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) @@ -556,24 +562,24 @@ system.iocache.tags.tag_accesses 428607 # Nu system.iocache.tags.data_accesses 428607 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses system.iocache.ReadReq_misses::total 903 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses system.iocache.demand_misses::total 903 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses system.iocache.overall_misses::total 903 # number of overall misses system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses @@ -589,49 +595,51 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 13903764 # Transaction distribution -system.membus.trans_dist::ReadResp 13903764 # Transaction distribution +system.membus.trans_dist::ReadReq 13857337 # Transaction distribution +system.membus.trans_dist::ReadResp 13903747 # Transaction distribution system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution -system.membus.trans_dist::Writeback 144777 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::Writeback 144835 # Transaction distribution +system.membus.trans_dist::CleanEvict 9844 # Transaction distribution system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution -system.membus.trans_dist::ReadExReq 134369 # Transaction distribution -system.membus.trans_dist::ReadExResp 134364 # Transaction distribution +system.membus.trans_dist::ReadExReq 134360 # Transaction distribution +system.membus.trans_dist::ReadExResp 134355 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 46410 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution system.membus.trans_dist::MessageResp 1696 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462531 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205091 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28350396 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 471480 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28214040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28360246 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17791872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43216633 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17793920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43218681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14247815 # Request fanout histogram +system.membus.snoop_fanout::samples 14257691 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.010910 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14246119 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14255995 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14247815 # Request fanout histogram +system.membus.snoop_fanout::total 14257691 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 999af0daa..2f3799b17 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,124 +1,124 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.184750 # Number of seconds simulated -sim_ticks 5184749789500 # Number of ticks simulated -final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.184733 # Number of seconds simulated +sim_ticks 5184732721500 # Number of ticks simulated +final_tick 5184732721500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812427 # Simulator instruction rate (inst/s) -host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32734861616 # Simulator tick rate (ticks/s) -host_mem_usage 599680 # Number of bytes of host memory used -host_seconds 158.39 # Real time elapsed on the host -sim_insts 128677191 # Number of instructions simulated -sim_ops 248045844 # Number of ops (including micro ops) simulated +host_inst_rate 808289 # Simulator instruction rate (inst/s) +host_op_rate 1558079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32570584041 # Simulator tick rate (ticks/s) +host_mem_usage 654268 # Number of bytes of host memory used +host_seconds 159.18 # Real time elapsed on the host +sim_insts 128667033 # Number of instructions simulated +sim_ops 248022101 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 825344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9044928 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory -system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory +system.physmem.bytes_read::total 9898944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 825344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 825344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8133056 # Number of bytes written to this memory +system.physmem.bytes_written::total 8133056 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141327 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154671 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127079 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127079 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1744531 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1909249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159187 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159187 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568655 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1568655 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 159187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1744531 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154244 # Number of read requests accepted -system.physmem.writeReqs 173690 # Number of write requests accepted -system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue -system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9927 # Per bank write bursts -system.physmem.perBankRdBursts::1 9220 # Per bank write bursts -system.physmem.perBankRdBursts::2 9906 # Per bank write bursts -system.physmem.perBankRdBursts::3 9744 # Per bank write bursts -system.physmem.perBankRdBursts::4 9716 # Per bank write bursts -system.physmem.perBankRdBursts::5 9338 # Per bank write bursts -system.physmem.perBankRdBursts::6 9475 # Per bank write bursts -system.physmem.perBankRdBursts::7 9515 # Per bank write bursts -system.physmem.perBankRdBursts::8 8926 # Per bank write bursts -system.physmem.perBankRdBursts::9 9405 # Per bank write bursts -system.physmem.perBankRdBursts::10 9702 # Per bank write bursts -system.physmem.perBankRdBursts::11 9402 # Per bank write bursts -system.physmem.perBankRdBursts::12 9788 # Per bank write bursts -system.physmem.perBankRdBursts::13 10193 # Per bank write bursts -system.physmem.perBankRdBursts::14 9798 # Per bank write bursts -system.physmem.perBankRdBursts::15 10094 # Per bank write bursts -system.physmem.perBankWrBursts::0 9407 # Per bank write bursts -system.physmem.perBankWrBursts::1 8748 # Per bank write bursts -system.physmem.perBankWrBursts::2 9677 # Per bank write bursts -system.physmem.perBankWrBursts::3 9718 # Per bank write bursts -system.physmem.perBankWrBursts::4 9428 # Per bank write bursts -system.physmem.perBankWrBursts::5 9072 # Per bank write bursts -system.physmem.perBankWrBursts::6 8868 # Per bank write bursts -system.physmem.perBankWrBursts::7 9192 # Per bank write bursts -system.physmem.perBankWrBursts::8 8615 # Per bank write bursts -system.physmem.perBankWrBursts::9 8711 # Per bank write bursts -system.physmem.perBankWrBursts::10 9601 # Per bank write bursts -system.physmem.perBankWrBursts::11 9113 # Per bank write bursts -system.physmem.perBankWrBursts::12 9702 # Per bank write bursts -system.physmem.perBankWrBursts::13 9421 # Per bank write bursts -system.physmem.perBankWrBursts::14 9363 # Per bank write bursts -system.physmem.perBankWrBursts::15 8959 # Per bank write bursts +system.physmem.bw_total::total 3477903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154671 # Number of read requests accepted +system.physmem.writeReqs 127079 # Number of write requests accepted +system.physmem.readBursts 154671 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127079 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9888768 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.physmem.bytesWritten 8131392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9898944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8133056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48348 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9772 # Per bank write bursts +system.physmem.perBankRdBursts::1 9412 # Per bank write bursts +system.physmem.perBankRdBursts::2 9829 # Per bank write bursts +system.physmem.perBankRdBursts::3 9622 # Per bank write bursts +system.physmem.perBankRdBursts::4 9563 # Per bank write bursts +system.physmem.perBankRdBursts::5 9355 # Per bank write bursts +system.physmem.perBankRdBursts::6 9720 # Per bank write bursts +system.physmem.perBankRdBursts::7 9664 # Per bank write bursts +system.physmem.perBankRdBursts::8 9219 # Per bank write bursts +system.physmem.perBankRdBursts::9 9313 # Per bank write bursts +system.physmem.perBankRdBursts::10 9431 # Per bank write bursts +system.physmem.perBankRdBursts::11 9415 # Per bank write bursts +system.physmem.perBankRdBursts::12 9985 # Per bank write bursts +system.physmem.perBankRdBursts::13 10194 # Per bank write bursts +system.physmem.perBankRdBursts::14 10163 # Per bank write bursts +system.physmem.perBankRdBursts::15 9855 # Per bank write bursts +system.physmem.perBankWrBursts::0 8316 # Per bank write bursts +system.physmem.perBankWrBursts::1 7960 # Per bank write bursts +system.physmem.perBankWrBursts::2 8144 # Per bank write bursts +system.physmem.perBankWrBursts::3 8236 # Per bank write bursts +system.physmem.perBankWrBursts::4 8504 # Per bank write bursts +system.physmem.perBankWrBursts::5 7731 # Per bank write bursts +system.physmem.perBankWrBursts::6 7974 # Per bank write bursts +system.physmem.perBankWrBursts::7 7835 # Per bank write bursts +system.physmem.perBankWrBursts::8 7118 # Per bank write bursts +system.physmem.perBankWrBursts::9 7555 # Per bank write bursts +system.physmem.perBankWrBursts::10 7609 # Per bank write bursts +system.physmem.perBankWrBursts::11 7637 # Per bank write bursts +system.physmem.perBankWrBursts::12 8092 # Per bank write bursts +system.physmem.perBankWrBursts::13 8095 # Per bank write bursts +system.physmem.perBankWrBursts::14 8240 # Per bank write bursts +system.physmem.perBankWrBursts::15 8007 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 68 # Number of times write queue was full causing retry -system.physmem.totGap 5184749726000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 5184732588500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154244 # Read request sizes (log2) +system.physmem.readPktSize::6 154671 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173690 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127079 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see @@ -152,194 +152,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.466912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.971568 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.231986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19566 35.01% 35.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13855 24.79% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5752 10.29% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3280 5.87% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2436 4.36% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1597 2.86% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1106 1.98% 85.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 958 1.71% 86.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7332 13.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55882 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5902 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.177906 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 623.301246 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5901 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads -system.physmem.totQLat 1425306951 # Total ticks spent queuing -system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5902 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5902 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.527109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.363013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.814592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4841 82.02% 82.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 0.83% 82.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 261 4.42% 87.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 70 1.19% 88.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 69 1.17% 89.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 251 4.25% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 22 0.37% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.22% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 15 0.25% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.08% 94.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 235 3.98% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.14% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.46% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5902 # Writes before turning the bus around for reads +system.physmem.totQLat 1454171981 # Total ticks spent queuing +system.physmem.totMemAccLat 4351271981 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9411.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28161.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing -system.physmem.readRowHits 126892 # Number of row buffer hits during reads -system.physmem.writeRowHits 117801 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes -system.physmem.avgGap 15810345.15 # Average gap between requests -system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.758961 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states -system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 126926 # Number of row buffer hits during reads +system.physmem.writeRowHits 98756 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.71 # Row buffer hit rate for writes +system.physmem.avgGap 18401890.29 # Average gap between requests +system.physmem.pageHitRate 80.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 207522000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 113231250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 600100800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 419256000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 134001495225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2993293881750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3467276945505 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.747605 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4979520185732 # Time in different power states +system.physmem_0.memoryStateTime::REF 173129580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32082834268 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.782314 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states -system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states +system.physmem_1.actEnergy 214945920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 117282000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 605085000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 404047440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338641458480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134530881300 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2992829508000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3467343208140 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.760386 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4978746411720 # Time in different power states +system.physmem_1.memoryStateTime::REF 173129580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32855777030 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10369499579 # number of cpu cycles simulated +system.cpu.numCycles 10369465443 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128677191 # Number of instructions committed -system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses +system.cpu.committedInsts 128667033 # Number of instructions committed +system.cpu.committedOps 248022101 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232599125 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2317433 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls -system.cpu.num_int_insts 232619140 # number of integer instructions +system.cpu.num_func_calls 2317363 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23194478 # number of instructions that are conditional controls +system.cpu.num_int_insts 232599125 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read -system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written +system.cpu.num_int_register_reads 435753384 # number of times the integer registers were read +system.cpu.num_int_register_writes 198362025 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written -system.cpu.num_mem_refs 22361713 # number of memory refs -system.cpu.num_load_insts 13951833 # Number of load instructions -system.cpu.num_store_insts 8409880 # Number of store instructions -system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942121 # Percentage of idle cycles -system.cpu.Branches 26373024 # Number of branches fetched -system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133133176 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95670461 # number of times the CC registers were written +system.cpu.num_mem_refs 22356642 # number of memory refs +system.cpu.num_load_insts 13946240 # Number of load instructions +system.cpu.num_store_insts 8410402 # Number of store instructions +system.cpu.num_idle_cycles 9769457503.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600007939.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057863 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942137 # Percentage of idle cycles +system.cpu.Branches 26370667 # Number of branches fetched +system.cpu.op_class::No_OpClass 172538 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225235379 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140393 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123647 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -366,214 +361,215 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13941273 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8410402 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248047391 # Class of executed instruction +system.cpu.op_class::total 248023648 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1622522 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1621027 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20151381 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1621539 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.427318 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54359500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996962 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits -system.cpu.dcache.overall_hits::total 20150865 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses -system.cpu.dcache.overall_misses::total 1634737 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88751069 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88751069 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12012436 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12012436 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077606 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077606 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59170 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59170 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20090042 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20090042 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20149212 # number of overall hits +system.cpu.dcache.overall_hits::total 20149212 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905821 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905821 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324802 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 324802 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402538 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402538 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1230623 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1230623 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1633161 # number of overall misses +system.cpu.dcache.overall_misses::total 1633161 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12812474000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12812474000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12127378479 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12127378479 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24939852479 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24939852479 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24939852479 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24939852479 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12918257 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12918257 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8402408 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8402408 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461708 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461708 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21320665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21320665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21782373 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21782373 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070119 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070119 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038656 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038656 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871845 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871845 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057720 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057720 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074976 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074976 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14144.598105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14144.598105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37337.758016 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37337.758016 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20266.037998 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20266.037998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15270.908673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15270.908673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5798 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 80.527778 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks -system.cpu.dcache.writebacks::total 1539491 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable +system.cpu.dcache.writebacks::writebacks 1537873 # number of writebacks +system.cpu.dcache.writebacks::total 1537873 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9093 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9093 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9381 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9381 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9381 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9381 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 905533 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 905533 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315709 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315709 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402504 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402504 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1221242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1221242 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623746 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623746 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable +system.cpu.dcache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11904745500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11904745500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11312729479 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11312729479 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5814985000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5814985000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23217474979 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23217474979 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29032459979 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29032459979 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94684333500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94684333500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2622247500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2622247500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97306581000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97306581000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070097 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070097 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037574 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037574 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871772 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871772 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057280 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057280 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074544 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074544 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13146.672181 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13146.672181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35832.774736 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35832.774736 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14447.024129 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14447.024129 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19011.363005 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19011.363005 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17879.927020 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17879.927020 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 165256.431581 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165256.431581 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188433.996838 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188433.996838 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 165806.023480 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 165806.023480 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7782 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.044171 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13071 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7797 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.676414 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5158049844500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.044171 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315261 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315261 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 53116 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53116 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13073 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13073 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13073 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13073 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13073 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13073 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8990 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8990 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8990 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8990 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8990 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8990 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97324000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97324000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97324000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 97324000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97324000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 97324000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22063 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22063 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22063 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22063 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22063 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22063 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407470 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407470 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407470 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407470 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407470 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407470 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10825.806452 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10825.806452 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10825.806452 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10825.806452 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -582,86 +578,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8990 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8990 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8990 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8990 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8990 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8990 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 88334000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 88334000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 88334000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 88334000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 88334000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 88334000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407470 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407470 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407470 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407470 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9825.806452 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9825.806452 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9825.806452 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 794465 # number of replacements -system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 792637 # number of replacements +system.cpu.icache.tags.tagsinuse 510.330403 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144952019 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 793149 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.755093 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161555480500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.330403 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996739 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits -system.cpu.icache.overall_hits::total 144962865 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses -system.cpu.icache.overall_misses::total 794984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146538331 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146538331 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144952019 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144952019 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144952019 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144952019 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144952019 # number of overall hits +system.cpu.icache.overall_hits::total 144952019 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793156 # number of overall misses +system.cpu.icache.overall_misses::total 793156 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11221653000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11221653000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11221653000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11221653000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11221653000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11221653000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145745175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145745175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145745175 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145745175 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145745175 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145745175 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005442 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005442 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005442 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005442 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005442 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005442 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14148.103274 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14148.103274 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14148.103274 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14148.103274 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14148.103274 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -670,88 +666,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793156 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 793156 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 793156 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793156 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793156 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793156 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10428497000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10428497000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10428497000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10428497000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10428497000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10428497000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005442 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005442 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005442 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005442 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13148.103274 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13148.103274 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13148.103274 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13148.103274 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 3538 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.060279 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7930 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3549 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.234432 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161245744500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.060279 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191267 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191267 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 29062 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29062 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7929 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7929 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7931 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7931 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7931 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7931 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4400 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4400 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4400 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4400 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4400 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4400 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45407000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45407000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45407000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 45407000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45407000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 45407000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12329 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12329 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12331 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12331 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12331 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12331 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356882 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356882 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356824 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.356824 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356824 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.356824 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10319.772727 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10319.772727 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10319.772727 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10319.772727 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -760,163 +756,169 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 43592750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.430066 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.430066 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.429996 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.429996 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8218.844268 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 796 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 796 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4400 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4400 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4400 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4400 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 41007000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 41007000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 41007000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 41007000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 41007000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 41007000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356882 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356882 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356824 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356824 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9319.772727 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9319.772727 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9319.772727 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87146 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64741.188816 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3494549 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151845 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.013922 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87263 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64757.225173 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4369524 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151965 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 28.753489 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141667 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3260.512095 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.769879 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50419.617435 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.145028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3328.329800 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11009.132909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.769342 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.168239 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64699 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2964 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5133 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56510 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987228 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32250710 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits -system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167986 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.988117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64702 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5302 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56392 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987274 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39224493 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39224493 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 1541775 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1541775 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199754 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 780246 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 780246 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6724 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 3018 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1278797 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1288539 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6724 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3018 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 780246 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1478551 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2268539 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6724 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3018 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 780246 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1478551 # number of overall hits +system.cpu.l2cache.overall_hits::total 2268539 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1367 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1367 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113781 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113781 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12897 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 12897 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28476 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 28481 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12897 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 142257 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155159 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses -system.cpu.l2cache.overall_misses::total 154732 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 12897 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 142257 # number of overall misses +system.cpu.l2cache.overall_misses::total 155159 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21508500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21508500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8694302000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8694302000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1043096500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1043096500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 401500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2328492500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2328894000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 401500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1043096500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11022794500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12066292500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 401500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1043096500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11022794500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12066292500 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 1541775 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1541775 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 313408 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 313408 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3333 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 794971 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1622279 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2427725 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313535 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313535 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 793143 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 793143 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6724 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 3023 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307273 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1317020 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6724 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3023 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 793143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1620808 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423698 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6724 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3023 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 793143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1620808 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423698 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816607 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816607 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362897 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362897 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016261 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016261 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001654 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021783 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021625 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001654 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016261 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087769 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.064017 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001654 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016261 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087769 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.064017 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15734.089247 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15734.089247 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76412.599643 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76412.599643 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80879.002869 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80879.002869 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 80300 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81770.350471 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81770.092342 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77767.274215 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80300 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80879.002869 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77485.076306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77767.274215 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -925,143 +927,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks -system.cpu.l2cache.writebacks::total 80303 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80412 # number of writebacks +system.cpu.l2cache.writebacks::total 80412 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 30 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 30 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1367 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1367 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12897 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12897 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28476 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28481 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12897 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155159 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12897 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155159 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 572954 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 572954 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872160717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887274749 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 586870 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 586870 # number of overall MSHR uncacheable misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29036000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29036000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7556492000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7556492000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 914126500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 914126500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 351500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2043732500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2044084000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 914126500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9600224500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10514702500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 351500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 914126500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9600224500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10514702500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 87522404500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 87522404500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2462213500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2462213500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89984618000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89984618000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816607 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816607 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362897 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362897 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016261 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021783 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021625 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.064017 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016261 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087769 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.064017 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21240.673007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21240.673007 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66412.599643 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66412.599643 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70879.002869 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70879.002869 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 70300 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71770.350471 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71770.092342 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70879.002869 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67485.076306 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67767.274215 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 152756.424600 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152756.424600 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 176933.996838 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176933.996838 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 153329.728901 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 153329.728901 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 572954 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2687857 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1668857 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 884964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 793156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322272 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55819 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378925 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6040657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20226 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8448782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50761152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203819691 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 244416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 629120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255454379 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 189246 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5626152 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.032703 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.177859 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5442159 96.73% 96.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 183993 3.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5626152 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4269812500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 480000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1189734000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3013374987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6600000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13485000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 228399 # Transaction distribution -system.iobus.trans_dist::ReadResp 228399 # Transaction distribution +system.iobus.trans_dist::ReadReq 226549 # Transaction distribution +system.iobus.trans_dist::ReadResp 226549 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution -system.iobus.trans_dist::WriteResp 11006 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::WriteResp 57726 # Transaction distribution system.iobus.trans_dist::MessageReq 1652 # Transaction distribution system.iobus.trans_dist::MessageResp 1652 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) @@ -1072,7 +1084,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 429188 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1082,12 +1094,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 473420 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95130 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95130 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 571854 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1096,7 +1108,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 214594 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1106,13 +1118,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 242990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027304 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) +system.iobus.pkt_size::total 3276902 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3939784 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1130,7 +1142,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 214595000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1148,169 +1160,171 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 242362178 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 462414000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50042000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47502 # number of replacements -system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use +system.iocache.tags.replacements 47510 # number of replacements +system.iocache.tags.tagsinuse 0.095938 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5046145075000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095938 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005996 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005996 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428013 # Number of tag accesses -system.iocache.tags.data_accesses 428013 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 837 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses -system.iocache.demand_misses::total 837 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses -system.iocache.overall_misses::total 837 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses +system.iocache.tags.tag_accesses 428085 # Number of tag accesses +system.iocache.tags.data_accesses 428085 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 845 # number of ReadReq misses +system.iocache.ReadReq_misses::total 845 # number of ReadReq misses +system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses +system.iocache.demand_misses::pc.south_bridge.ide 845 # number of demand (read+write) misses +system.iocache.demand_misses::total 845 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 845 # number of overall misses +system.iocache.overall_misses::total 845 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 134017694 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 134017694 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5509470484 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5509470484 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 134017694 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 134017694 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 134017694 # number of overall miss cycles +system.iocache.overall_miss_latency::total 134017694 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 845 # number of ReadReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 845 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 845 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 845 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 845 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158600.821302 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 117925.310017 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117925.310017 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158600.821302 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158600.821302 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158600.821302 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.178571 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 845 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 845 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 845 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 845 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 845 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 91767694 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3173470484 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3173470484 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 91767694 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 91767694 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 91767694 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 108600.821302 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 67925.310017 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67925.310017 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 108600.821302 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 108600.821302 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 617109 # Transaction distribution -system.membus.trans_dist::ReadResp 617109 # Transaction distribution +system.membus.trans_dist::ReadReq 572954 # Transaction distribution +system.membus.trans_dist::ReadResp 615177 # Transaction distribution system.membus.trans_dist::WriteReq 13916 # Transaction distribution system.membus.trans_dist::WriteResp 13916 # Transaction distribution -system.membus.trans_dist::Writeback 126970 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution -system.membus.trans_dist::ReadExReq 112993 # Transaction distribution -system.membus.trans_dist::ReadExResp 112993 # Transaction distribution +system.membus.trans_dist::Writeback 127079 # Transaction distribution +system.membus.trans_dist::CleanEvict 7222 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1646 # Transaction distribution +system.membus.trans_dist::ReadExReq 113502 # Transaction distribution +system.membus.trans_dist::ReadExResp 113502 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42223 # Transaction distribution system.membus.trans_dist::MessageReq 1652 # Transaction distribution system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 473420 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 400152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1573892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1718963 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242990 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1583 # Total snoops (count) -system.membus.snoop_fanout::samples 921584 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15016960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16660587 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19682235 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1580 # Total snoops (count) +system.membus.snoop_fanout::samples 927896 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001780 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.042157 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::1 926244 99.82% 99.82% # Request fanout histogram system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 921584 # Request fanout histogram -system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 927896 # Request fanout histogram +system.membus.reqLayer0.occupancy 359896000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527973000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 848970266 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2157850870 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 85904679 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |