diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/quick/fs/10.linux-boot | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
13 files changed, 6574 insertions, 6498 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 90f1f17e3..8d5fa3758 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357988000 # Number of ticks simulated -final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357999000 # Number of ticks simulated +final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1670594 # Simulator instruction rate (inst/s) -host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48045239456 # Simulator tick rate (ticks/s) -host_mem_usage 332628 # Number of bytes of host memory used -host_seconds 38.91 # Real time elapsed on the host +host_inst_rate 1770526 # Simulator instruction rate (inst/s) +host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50919239991 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 36.71 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -49,7 +49,7 @@ system.physmem.bw_total::cpu0.data 35592763 # To system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -83,7 +83,7 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738722771 # number of cpu cycles simulated +system.cpu0.numCycles 3738722793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -101,12 +101,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -172,7 +172,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed @@ -191,7 +191,7 @@ system.cpu0.num_fp_register_writes 98967 # nu system.cpu0.num_mem_refs 12536107 # number of memory refs system.cpu0.num_load_insts 7783754 # Number of load instructions system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles @@ -231,13 +231,13 @@ system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Cl system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781371 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781367 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,32 +245,32 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) @@ -301,8 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks -system.cpu0.dcache.writebacks::total 633127 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks +system.cpu0.dcache.writebacks::total 633126 # number of writebacks system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -383,7 +383,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738296587 # number of cpu cycles simulated +system.cpu1.numCycles 3738296609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -457,7 +457,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed system.cpu1.committedInsts 15522159 # Number of instructions committed system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed @@ -474,8 +474,8 @@ system.cpu1.num_fp_register_writes 104129 # nu system.cpu1.num_mem_refs 4961786 # number of memory refs system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles system.cpu1.Branches 2214163 # Number of branches fetched @@ -515,12 +515,12 @@ system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id @@ -590,7 +590,7 @@ system.cpu1.icache.tags.tagsinuse 453.133719 # Cy system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy @@ -679,7 +679,7 @@ system.iocache.tags.tagsinuse 0.434096 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy @@ -721,16 +721,16 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.l2c.tags.replacements 999922 # number of replacements -system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use -system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use +system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy @@ -744,37 +744,37 @@ system.l2c.tags.age_task_id_blocks_1024::2 6047 # system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46377222 # Number of tag accesses -system.l2c.tags.data_accesses 46377222 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.tags.tag_accesses 46377199 # Number of tag accesses +system.l2c.tags.data_accesses 46377199 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738194 # number of overall hits +system.l2c.overall_hits::cpu0.data 738192 # number of overall hits system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910410 # number of overall hits +system.l2c.overall_hits::cpu1.data 185615 # number of overall hits +system.l2c.overall_hits::total 1910407 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses @@ -800,57 +800,57 @@ system.l2c.overall_misses::cpu0.data 1040486 # nu system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses system.l2c.overall_misses::cpu1.data 12101 # number of overall misses system.l2c.overall_misses::total 1066093 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses @@ -862,6 +862,12 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 80923 # number of writebacks system.l2c.writebacks::total 80923 # number of writebacks +system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution @@ -871,17 +877,17 @@ system.membus.trans_dist::CleanEvict 918012 # Tr system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution +system.membus.trans_dist::ReadExReq 125244 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) @@ -889,61 +895,61 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2204372 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 2204371 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram +system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2204372 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204371 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083516 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram +system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1000943 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 84bdf9ee5..1cd81f116 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829331993500 # Number of ticks simulated final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1840131 # Simulator instruction rate (inst/s) -host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56067507873 # Simulator tick rate (ticks/s) -host_mem_usage 330836 # Number of bytes of host memory used -host_seconds 32.63 # Real time elapsed on the host +host_inst_rate 1838030 # Simulator instruction rate (inst/s) +host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56003449171 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 32.66 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e58364a4b..d99331f2d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982593 # Number of seconds simulated -sim_ticks 1982592736000 # Number of ticks simulated -final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.963613 # Number of seconds simulated +sim_ticks 1963612574000 # Number of ticks simulated +final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1178528 # Simulator instruction rate (inst/s) -host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38301918928 # Simulator tick rate (ticks/s) -host_mem_usage 332884 # Number of bytes of host memory used -host_seconds 51.76 # Real time elapsed on the host -sim_insts 61003209 # Number of instructions simulated -sim_ops 61003209 # Number of ops (including micro ops) simulated +host_inst_rate 993881 # Simulator instruction rate (inst/s) +host_op_rate 993880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32036346352 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 61.29 # Real time elapsed on the host +sim_insts 60918165 # Number of instructions simulated +sim_ops 60918165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407341 # Number of read requests accepted -system.physmem.writeReqs 120928 # Number of write requests accepted -system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406688 # Number of read requests accepted +system.physmem.writeReqs 120457 # Number of write requests accepted +system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25226 # Per bank write bursts -system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25423 # Per bank write bursts -system.physmem.perBankRdBursts::3 24855 # Per bank write bursts -system.physmem.perBankRdBursts::4 25157 # Per bank write bursts -system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25497 # Per bank write bursts -system.physmem.perBankRdBursts::7 25338 # Per bank write bursts -system.physmem.perBankRdBursts::8 25239 # Per bank write bursts -system.physmem.perBankRdBursts::9 25589 # Per bank write bursts -system.physmem.perBankRdBursts::10 25733 # Per bank write bursts -system.physmem.perBankRdBursts::11 25917 # Per bank write bursts -system.physmem.perBankRdBursts::12 25947 # Per bank write bursts -system.physmem.perBankRdBursts::13 25572 # Per bank write bursts -system.physmem.perBankRdBursts::14 25277 # Per bank write bursts -system.physmem.perBankRdBursts::15 25644 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7778 # Per bank write bursts -system.physmem.perBankWrBursts::2 7471 # Per bank write bursts -system.physmem.perBankWrBursts::3 6886 # Per bank write bursts -system.physmem.perBankWrBursts::4 7104 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7144 # Per bank write bursts -system.physmem.perBankWrBursts::8 7161 # Per bank write bursts -system.physmem.perBankWrBursts::9 7315 # Per bank write bursts -system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8150 # Per bank write bursts -system.physmem.perBankWrBursts::12 8256 # Per bank write bursts -system.physmem.perBankWrBursts::13 7924 # Per bank write bursts -system.physmem.perBankWrBursts::14 7541 # Per bank write bursts -system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.perBankRdBursts::0 25130 # Per bank write bursts +system.physmem.perBankRdBursts::1 25381 # Per bank write bursts +system.physmem.perBankRdBursts::2 25483 # Per bank write bursts +system.physmem.perBankRdBursts::3 24909 # Per bank write bursts +system.physmem.perBankRdBursts::4 25165 # Per bank write bursts +system.physmem.perBankRdBursts::5 25252 # Per bank write bursts +system.physmem.perBankRdBursts::6 25797 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25672 # Per bank write bursts +system.physmem.perBankRdBursts::9 25333 # Per bank write bursts +system.physmem.perBankRdBursts::10 25279 # Per bank write bursts +system.physmem.perBankRdBursts::11 25593 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25645 # Per bank write bursts +system.physmem.perBankRdBursts::14 25712 # Per bank write bursts +system.physmem.perBankRdBursts::15 25022 # Per bank write bursts +system.physmem.perBankWrBursts::0 7825 # Per bank write bursts +system.physmem.perBankWrBursts::1 7603 # Per bank write bursts +system.physmem.perBankWrBursts::2 7492 # Per bank write bursts +system.physmem.perBankWrBursts::3 6933 # Per bank write bursts +system.physmem.perBankWrBursts::4 7149 # Per bank write bursts +system.physmem.perBankWrBursts::5 7135 # Per bank write bursts +system.physmem.perBankWrBursts::6 7628 # Per bank write bursts +system.physmem.perBankWrBursts::7 7255 # Per bank write bursts +system.physmem.perBankWrBursts::8 7538 # Per bank write bursts +system.physmem.perBankWrBursts::9 7229 # Per bank write bursts +system.physmem.perBankWrBursts::10 7235 # Per bank write bursts +system.physmem.perBankWrBursts::11 7425 # Per bank write bursts +system.physmem.perBankWrBursts::12 7840 # Per bank write bursts +system.physmem.perBankWrBursts::13 8302 # Per bank write bursts +system.physmem.perBankWrBursts::14 8309 # Per bank write bursts +system.physmem.perBankWrBursts::15 7527 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1982585344500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1963565980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407341 # Read request sizes (log2) +system.physmem.readPktSize::6 406688 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120928 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,176 +158,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads -system.physmem.totQLat 2785960750 # Total ticks spent queuing -system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads +system.physmem.totQLat 2148968000 # Total ticks spent queuing +system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 363789 # Number of row buffer hits during reads -system.physmem.writeRowHits 96765 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes -system.physmem.avgGap 3752984.45 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.009839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states -system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing +system.physmem.readRowHits 364299 # Number of row buffer hits during reads +system.physmem.writeRowHits 96294 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes +system.physmem.avgGap 3724906.77 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.639531 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states +system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.108451 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states -system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.691088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states +system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416468 # DTB read hits -system.cpu0.dtb.read_misses 7442 # DTB read misses +system.cpu0.dtb.read_hits 7494168 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004426 # DTB write hits -system.cpu0.dtb.write_misses 812 # DTB write misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5065702 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420894 # DTB hits -system.cpu0.dtb.data_misses 8254 # DTB misses +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559870 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482357 # ITB hits +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501177 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486228 # ITB accesses +system.cpu0.itb.fetch_accesses 3505048 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -340,36 +343,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851876 # number of cpu cycles simulated +system.cpu0.numCycles 3925790590 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -401,352 +404,352 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147596 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::total 149727 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47316464 # Number of instructions committed -system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185664 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43886764 # number of integer instructions -system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460790 # number of memory refs -system.cpu0.num_load_insts 7443408 # Number of load instructions -system.cpu0.num_store_insts 5017382 # Number of store instructions -system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles -system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles -system.cpu0.Branches 7133745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3064 # number of times the context was actually changed +system.cpu0.committedInsts 47755591 # Number of instructions committed +system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses +system.cpu0.num_func_calls 1202061 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44289668 # number of integer instructions +system.cpu0.num_fp_insts 210363 # number of float instructions +system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written +system.cpu0.num_mem_refs 12600044 # number of memory refs +system.cpu0.num_load_insts 7521304 # Number of load instructions +system.cpu0.num_store_insts 5078740 # Number of store instructions +system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles +system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles +system.cpu0.Branches 7206590 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction +system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47325062 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172723 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency +system.cpu0.op_class::total 47764191 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1179864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits +system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks -system.cpu0.dcache.writebacks::total 672790 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 686545 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks +system.cpu0.dcache.writebacks::total 678308 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 698162 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits -system.cpu0.icache.overall_hits::total 46637883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses -system.cpu0.icache.overall_misses::total 687179 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits +system.cpu0.icache.overall_hits::total 47065399 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks -system.cpu0.icache.writebacks::total 686545 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks +system.cpu0.icache.writebacks::total 698162 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2511191 # DTB read hits -system.cpu1.dtb.read_misses 2993 # DTB read misses +system.cpu1.dtb.read_hits 2421538 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1830032 # DTB write hits -system.cpu1.dtb.write_misses 342 # DTB write misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1759460 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4341223 # DTB hits -system.cpu1.dtb.data_misses 3335 # DTB misses +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4180998 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990291 # ITB hits +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1965348 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991507 # ITB accesses +system.cpu1.itb.fetch_accesses 1966564 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -759,32 +762,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965185472 # number of cpu cycles simulated +system.cpu1.numCycles 3927225148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -800,334 +803,342 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73972 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches +system.cpu1.kern.callpal::total 71579 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 912 +system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 892 system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 448 -system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 428 +system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13686745 # Number of instructions committed -system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430170 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12624358 # number of integer instructions -system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4365379 # number of memory refs -system.cpu1.num_load_insts 2525846 # Number of load instructions -system.cpu1.num_store_insts 1839533 # Number of store instructions -system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles -system.cpu1.Branches 1950147 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction -system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.committedInsts 13162574 # Number of instructions committed +system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses +system.cpu1.num_func_calls 411749 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12139381 # number of integer instructions +system.cpu1.num_fp_insts 173446 # number of float instructions +system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written +system.cpu1.num_mem_refs 4204594 # number of memory refs +system.cpu1.num_load_insts 2435865 # Number of load instructions +system.cpu1.num_store_insts 1768729 # Number of store instructions +system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles +system.cpu1.Branches 1871255 # Number of branches fetched +system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction +system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction +system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13690109 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173692 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy +system.cpu1.op_class::total 13165936 # Class of executed instruction +system.cpu1.dcache.tags.replacements 166516 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17608650 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17608650 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339562 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339562 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1707213 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1707213 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50427 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50427 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53080 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53080 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4046775 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4046775 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4046775 # number of overall hits -system.cpu1.dcache.overall_hits::total 4046775 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123491 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123491 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65586 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65586 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9255 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9255 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189077 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189077 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189077 # number of overall misses -system.cpu1.dcache.overall_misses::total 189077 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3427062000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3427062000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits +system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses +system.cpu1.dcache.overall_misses::total 181092 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks -system.cpu1.dcache.writebacks::total 119726 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 331529 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks +system.cpu1.dcache.writebacks::total 114398 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 316153 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits -system.cpu1.icache.overall_hits::total 13358029 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses -system.cpu1.icache.overall_misses::total 332081 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits +system.cpu1.icache.overall_hits::total 12849230 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses +system.cpu1.icache.overall_misses::total 316707 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks -system.cpu1.icache.writebacks::total 331529 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks +system.cpu1.icache.writebacks::total 316153 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1140,98 +1151,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55610 # Transaction distribution +system.iobus.trans_dist::WriteResp 55610 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1240,38 +1251,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1280,206 +1291,206 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.l2c.tags.replacements 342136 # number of replacements -system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use -system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906899 # Number of tag accesses -system.l2c.tags.data_accesses 35906899 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.l2c.tags.replacements 341504 # number of replacements +system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use +system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35882279 # Number of tag accesses +system.l2c.tags.data_accesses 35882279 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 65 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 124124 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48553 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172677 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 674650 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 331142 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1005792 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 659425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 113738 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 674650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 783549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 331142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 162291 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951632 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 674650 # number of overall hits -system.l2c.overall_hits::cpu0.data 783549 # number of overall hits -system.l2c.overall_hits::cpu1.inst 331142 # number of overall hits -system.l2c.overall_hits::cpu1.data 162291 # number of overall hits -system.l2c.overall_hits::total 1951632 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1812 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4784 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 12503 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 938 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13441 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 271537 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 338 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271875 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 12503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 386507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8215 # number of demand (read+write) misses -system.l2c.demand_misses::total 408163 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12503 # number of overall misses -system.l2c.overall_misses::cpu0.data 386507 # number of overall misses -system.l2c.overall_misses::cpu1.inst 938 # number of overall misses -system.l2c.overall_misses::cpu1.data 8215 # number of overall misses -system.l2c.overall_misses::total 408163 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3623500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 35439500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39063000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3369500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 943000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 4312500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 14618383500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1037446500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15655830000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1639795500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 123119500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1762915000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33668278500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 42563000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 33710841500 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1639795500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 48286662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 123119500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1080009500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 51129586500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1639795500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 48286662000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 123119500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1080009500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 51129586500 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 792516 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 792516 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 746948 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 746948 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5515 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 967 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 954 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1921 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 239094 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 56430 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295524 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 687153 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 332080 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1019233 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 930962 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 114076 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1045038 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 687153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1170056 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 332080 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 170506 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2359795 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 687153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1170056 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 332080 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 170506 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2359795 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941997 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767797 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867452 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.957601 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974843 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.966163 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.480857 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.139589 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.415692 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018195 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002825 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013187 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291674 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002963 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.260158 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018195 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.330332 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002825 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.048180 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172965 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018195 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.330332 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002825 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.048180 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172965 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1219.212651 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19558.222958 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 8165.342809 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3638.768898 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1013.978495 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2323.545259 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127149.547708 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131705.789006 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127441.695768 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131152.163481 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131257.462687 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 131159.511941 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123991.494713 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 125926.035503 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 123993.899770 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 125267.568349 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency +system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits +system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits +system.l2c.overall_hits::cpu0.data 789890 # number of overall hits +system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits +system.l2c.overall_hits::cpu1.data 156367 # number of overall hits +system.l2c.overall_hits::total 1948298 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses +system.l2c.demand_misses::total 407462 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses +system.l2c.overall_misses::cpu0.data 387198 # number of overall misses +system.l2c.overall_misses::cpu1.inst 455 # number of overall misses +system.l2c.overall_misses::cpu1.data 6828 # number of overall misses +system.l2c.overall_misses::total 407462 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 79408 # number of writebacks -system.l2c.writebacks::total 79408 # number of writebacks +system.l2c.writebacks::writebacks 78937 # number of writebacks +system.l2c.writebacks::total 78937 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits @@ -1488,230 +1499,238 @@ system.l2c.overall_mshr_hits::cpu1.inst 11 # nu system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2972 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1812 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4784 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 926 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 930 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1856 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114970 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7877 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122847 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12503 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 927 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13430 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271537 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 338 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271875 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12503 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 386507 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 927 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8215 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 408152 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12503 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 386507 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 927 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8215 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 408152 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7201 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14131 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 21332 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 204338000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 124770000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 329108000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 63412000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 64097500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 127509500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13468683500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958676001 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14427359501 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1514765500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 112494001 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1627259501 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30952908500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 39183000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 30992091500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1514765500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 44421592000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 112494001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 997859001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 47046710502 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1514765500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 44421592000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 112494001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 997859001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 47046710502 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767797 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867452 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480857 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139589 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415692 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013177 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291674 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002963 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260158 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172961 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172961 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68754.374159 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68857.615894 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.478261 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.547708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121705.725657 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117441.691706 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121166.009010 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113991.494713 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 115926.035503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113993.899770 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 7201 # Transaction distribution -system.membus.trans_dist::ReadResp 292681 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution -system.membus.trans_dist::CleanEvict 262098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292676 # Transaction distribution +system.membus.trans_dist::WriteReq 14058 # Transaction distribution +system.membus.trans_dist::WriteResp 14058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution +system.membus.trans_dist::CleanEvict 261938 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123156 # Transaction distribution -system.membus.trans_dist::ReadExResp 122284 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285480 # Transaction distribution +system.membus.trans_dist::ReadExReq 122469 # Transaction distribution +system.membus.trans_dist::ReadExResp 121633 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1228458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1311895 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82454 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31150976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31233430 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33891670 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22771 # Total snoops (count) -system.membus.snoop_fanout::samples 883231 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21640 # Total snoops (count) +system.membus.snoop_fanout::samples 498117 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883231 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883231 # Request fanout histogram -system.membus.reqLayer0.occupancy 40519500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 498117 # Request fanout histogram +system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327558723 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178214500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790762 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395545 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361654 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7201 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107124 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913453 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018074 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 816802 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17061 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019260 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080678 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2060877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995690 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558897 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7200817 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87916672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118008584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42470976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601102 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266997334 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484769 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873172 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.136988 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344078 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398828 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479819 86.31% 86.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393117 13.68% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873172 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223704496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031139756 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802215285 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499214310 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293827886 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index b4533a137..2fb77dfab 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1048317 # Simulator instruction rate (inst/s) -host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36222399744 # Simulator tick rate (ticks/s) -host_mem_usage 330588 # Number of bytes of host memory used -host_seconds 53.59 # Real time elapsed on the host +host_inst_rate 855166 # Simulator instruction rate (inst/s) +host_op_rate 855166 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29548473540 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 65.70 # Real time elapsed on the host sim_insts 56182685 # Number of instructions simulated sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index b93cd163b..85c0f1360 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1211130 # Simulator instruction rate (inst/s) -host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23615387886 # Simulator tick rate (ticks/s) -host_mem_usage 581436 # Number of bytes of host memory used -host_seconds 117.88 # Real time elapsed on the host +host_inst_rate 1008697 # Simulator instruction rate (inst/s) +host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19668230366 # Simulator tick rate (ticks/s) +host_mem_usage 576064 # Number of bytes of host memory used +host_seconds 141.54 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 4464ff885..9e43d8fd4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882879000 # Number of ticks simulated -final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802882797500 # Number of ticks simulated +final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1338296 # Simulator instruction rate (inst/s) -host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25547394462 # Simulator tick rate (ticks/s) -host_mem_usage 592020 # Number of bytes of host memory used -host_seconds 109.71 # Real time elapsed on the host -sim_insts 146828562 # Number of instructions simulated -sim_ops 178908371 # Number of ops (including micro ops) simulated +host_inst_rate 797664 # Simulator instruction rate (inst/s) +host_op_rate 971941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15227033289 # Simulator tick rate (ticks/s) +host_mem_usage 590380 # Number of bytes of host memory used +host_seconds 184.07 # Real time elapsed on the host +sim_insts 146828219 # Number of instructions simulated +sim_ops 178907974 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152660 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11759340 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1109732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152660 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1262392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8477312 # Number of bytes written to this memory +system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8494876 # Number of bytes written to this memory +system.physmem.bytes_written::total 8493084 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132458 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192873 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136849 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136821 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3358384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4195445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3024497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3024497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3364636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7226208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -138,9 +138,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339777 # DTB read hits +system.cpu0.dtb.read_hits 20339693 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391027 # DTB write hits +system.cpu0.dtb.write_hits 16391003 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346648 # DTB read accesses -system.cpu0.dtb.write_accesses 16392120 # DTB write accesses +system.cpu0.dtb.read_accesses 20346564 # DTB read accesses +system.cpu0.dtb.write_accesses 16392096 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730804 # DTB hits +system.cpu0.dtb.hits 36730696 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738768 # DTB accesses +system.cpu0.dtb.accesses 36738660 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -204,7 +204,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97439598 # ITB inst hits +system.cpu0.itb.inst_hits 97439155 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -221,39 +221,39 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442956 # ITB inst accesses -system.cpu0.itb.hits 97439598 # DTB hits +system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses +system.cpu0.itb.hits 97439155 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442956 # DTB accesses -system.cpu0.numCycles 5605767724 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442513 # DTB accesses +system.cpu0.numCycles 5605767562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed -system.cpu0.committedInsts 95427136 # Number of instructions committed -system.cpu0.committedOps 115560651 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762921 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed +system.cpu0.committedInsts 95426725 # Number of instructions committed +system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204240 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762921 # number of integer instructions +system.cpu0.num_func_calls 8000241 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762477 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457857 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135716 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349972220 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907498 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873797 # number of memory refs -system.cpu0.num_load_insts 20597358 # Number of load instructions -system.cpu0.num_store_insts 17276439 # Number of store instructions -system.cpu0.num_idle_cycles 5488182951.223861 # Number of idle cycles -system.cpu0.num_busy_cycles 117584772.776139 # Number of busy cycles +system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873679 # number of memory refs +system.cpu0.num_load_insts 20597264 # Number of load instructions +system.cpu0.num_store_insts 17276415 # Number of store instructions +system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles +system.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941714 # Number of branches fetched +system.cpu0.Branches 21941548 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887557 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction @@ -282,18 +282,18 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597358 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276439 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882349 # Class of executed instruction -system.cpu0.dcache.tags.replacements 693475 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853481 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932424 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776797 # Average number of references to valid blocks. +system.cpu0.op_class::total 116881836 # Class of executed instruction +system.cpu0.dcache.tags.replacements 693478 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853481 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,60 +301,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113882 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113882 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108626 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108626 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690357 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690357 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798983 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798983 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145063 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145063 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373096 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373096 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295789 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295789 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668885 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668885 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769207 # number of overall misses -system.cpu0.dcache.overall_misses::total 769207 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986146 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986146 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467868 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467868 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914270 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses +system.cpu0.dcache.overall_misses::total 769220 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses @@ -365,13 +365,13 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks -system.cpu0.dcache.writebacks::total 693475 # number of writebacks -system.cpu0.icache.tags.replacements 1109624 # number of replacements +system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks +system.cpu0.dcache.writebacks::total 693478 # number of writebacks +system.cpu0.icache.tags.replacements 1109639 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -381,26 +381,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195994025 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195994025 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331795 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331795 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331795 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331795 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331795 # number of overall hits -system.cpu0.icache.overall_hits::total 96331795 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110145 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110145 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110145 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110145 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110145 # number of overall misses -system.cpu0.icache.overall_misses::total 1110145 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441940 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441940 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441940 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441940 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits +system.cpu0.icache.overall_hits::total 96331337 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses +system.cpu0.icache.overall_misses::total 1110160 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses @@ -413,185 +413,186 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks -system.cpu0.icache.writebacks::total 1109624 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks +system.cpu0.icache.writebacks::total 1109639 # number of writebacks system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 249486 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2730668 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 265599 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.281168 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 249747 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.758477 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070793 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984012 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000107 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984124 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16108 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5529 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7406 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2667 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983154 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59695806 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59695806 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10175 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4509 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14684 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510631 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510631 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1264603 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1264603 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94360 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94360 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068362 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1068362 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352230 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352230 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10175 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4509 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1068362 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446590 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529636 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10175 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4509 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1068362 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446590 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1529636 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 118 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26269 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26269 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175160 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175160 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41783 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41783 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127928 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 127928 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 118 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41783 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303088 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 345205 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 118 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41783 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303088 # number of overall misses -system.cpu0.l2cache.overall_misses::total 345205 # number of overall misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345244 # number of overall misses system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510631 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510631 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264603 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1264603 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26269 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26269 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110145 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1110145 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480158 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110145 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874841 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110145 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874841 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025502 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.022240 # miss rate for ReadReq accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037637 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037637 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266429 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266429 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025502 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037637 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404291 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184125 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025502 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037637 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks -system.cpu0.l2cache.writebacks::total 193020 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks +system.cpu0.l2cache.writebacks::total 193031 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510631 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1292468 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26269 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480158 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402091 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791673 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142101304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552324 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 234736876 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623160 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4317939 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067042 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.252935 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623521 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031542 93.37% 93.37% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283312 6.56% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3085 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4317939 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -641,9 +642,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173929 # DTB read hits +system.cpu1.dtb.read_hits 12173945 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587213 # DTB write hits +system.cpu1.dtb.write_hits 7587221 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -654,12 +655,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176782 # DTB read accesses -system.cpu1.dtb.write_accesses 7587719 # DTB write accesses +system.cpu1.dtb.read_accesses 12176798 # DTB read accesses +system.cpu1.dtb.write_accesses 7587727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761142 # DTB hits +system.cpu1.dtb.hits 19761166 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764501 # DTB accesses +system.cpu1.dtb.accesses 19764525 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -707,7 +708,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671686 # ITB inst hits +system.cpu1.itb.inst_hits 53671758 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -724,39 +725,39 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673420 # ITB inst accesses -system.cpu1.itb.hits 53671686 # DTB hits +system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses +system.cpu1.itb.hits 53671758 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673420 # DTB accesses -system.cpu1.numCycles 5605296633 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673492 # DTB accesses +system.cpu1.numCycles 5605296470 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.committedInsts 51401426 # Number of instructions committed -system.cpu1.committedOps 63347720 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984340 # Number of integer alu accesses +system.cpu1.committedInsts 51401494 # Number of instructions committed +system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984340 # number of integer instructions +system.cpu1.num_func_calls 9170873 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984416 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674879 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298438 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110675031 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268976 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894428 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026400 # number of memory refs -system.cpu1.num_load_insts 12289552 # Number of load instructions -system.cpu1.num_store_insts 7736848 # Number of store instructions -system.cpu1.num_idle_cycles 5539683011.597479 # Number of idle cycles -system.cpu1.num_busy_cycles 65613621.402521 # Number of busy cycles +system.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026424 # number of memory refs +system.cpu1.num_load_insts 12289568 # Number of load instructions +system.cpu1.num_store_insts 7736856 # Number of store instructions +system.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles +system.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217504 # Number of branches fetched +system.cpu1.Branches 15217528 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401392 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -785,80 +786,80 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289552 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736848 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459571 # Class of executed instruction +system.cpu1.op_class::total 65459659 # Class of executed instruction system.cpu1.dcache.tags.replacements 191946 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503521 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.422366 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39752021 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39752021 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858700 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858700 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397505 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397505 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72417 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72417 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256205 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256205 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306305 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306305 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306336 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92461 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92461 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22562 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22562 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229099 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229099 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses -system.cpu1.dcache.overall_misses::total 259817 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995338 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995338 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489966 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489966 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses +system.cpu1.dcache.overall_misses::total 259810 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485304 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485304 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566122 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237547 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237547 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -871,9 +872,9 @@ system.cpu1.dcache.writebacks::writebacks 191946 # n system.cpu1.dcache.writebacks::total 191946 # number of writebacks system.cpu1.icache.tags.replacements 523401 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. +system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy @@ -882,26 +883,26 @@ system.cpu1.icache.tags.occ_task_id_blocks::1024 512 system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869465 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869465 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148863 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148863 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148863 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148863 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148863 # number of overall hits -system.cpu1.icache.overall_hits::total 53148863 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits +system.cpu1.icache.overall_hits::total 53148935 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses system.cpu1.icache.overall_misses::total 523913 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672776 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672776 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672776 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672776 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672776 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672776 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -922,88 +923,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47378 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184475 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62425 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 18.974369 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47503 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.255151 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.017200 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.929171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000077 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.929371 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15027 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9441 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5060 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917175 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24501973 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24501973 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3627 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1923 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5550 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 121108 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 121108 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583081 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583081 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19862 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19862 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510444 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510444 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99124 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99124 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3627 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1923 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510444 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 118986 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634980 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3627 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1923 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510444 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 118986 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634980 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 268 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22562 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22562 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43753 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43753 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13469 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13469 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73550 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73550 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 268 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13469 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117303 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131378 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 268 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13469 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117303 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131378 # number of overall misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634834 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131524 # number of overall misses system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121108 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 121108 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583081 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583081 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22562 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) @@ -1020,78 +1021,78 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.122319 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.098441 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687778 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687778 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025708 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025708 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425947 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425947 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.122319 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025708 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496439 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171432 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.122319 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025708 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks -system.cpu1.l2cache.writebacks::total 32706 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks +system.cpu1.l2cache.writebacks::total 32790 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121108 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 594239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778800 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2369077 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347790 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1820349 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108308 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314409 # Request fanout histogram +system.cpu1.toL2Bus.snoops 347973 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1625261 89.28% 89.28% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 193017 10.60% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2071 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1820349 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1143,12 +1144,12 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1188,225 +1189,231 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.replacements 107729 # number of replacements -system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use -system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. +system.l2c.tags.replacements 107745 # number of replacements +system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use +system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7764.318269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4071.663088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1666.007629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 770.829870 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.734448 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.952311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60675 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1869 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45497 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.925827 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5179303 # Number of tag accesses -system.l2c.tags.data_accesses 5179303 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 225726 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225726 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 564 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 679 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 81 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16940 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 58 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 25005 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76077 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 34 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11094 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11733 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 124113 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 58 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 25005 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89977 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11094 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14773 # number of demand (read+write) hits -system.l2c.demand_hits::total 141053 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 58 # number of overall hits -system.l2c.overall_hits::cpu0.inst 25005 # number of overall hits -system.l2c.overall_hits::cpu0.data 89977 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11094 # number of overall hits -system.l2c.overall_hits::cpu1.data 14773 # number of overall hits -system.l2c.overall_hits::total 141053 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3255 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13225 # number of UpgradeReq misses +system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5181909 # Number of tag accesses +system.l2c.tags.data_accesses 5181909 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits +system.l2c.demand_hits::total 141203 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits +system.l2c.overall_hits::cpu0.inst 24898 # number of overall hits +system.l2c.overall_hits::cpu0.data 90119 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11147 # number of overall hits +system.l2c.overall_hits::cpu1.data 14817 # number of overall hits +system.l2c.overall_hits::total 141203 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9957 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3262 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13219 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1885 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136548 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152370 # number of ReadExReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1139 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136539 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15807 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 16778 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 11188 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2375 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1125 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 31476 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 16771 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 11196 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1129 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 31500 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16778 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 147736 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16947 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16771 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 147735 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16936 # number of demand (read+write) misses system.l2c.demand_misses::total 183846 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16778 # number of overall misses -system.l2c.overall_misses::cpu0.data 147736 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2375 # number of overall misses -system.l2c.overall_misses::cpu1.data 16947 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16771 # number of overall misses +system.l2c.overall_misses::cpu0.data 147735 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2394 # number of overall misses +system.l2c.overall_misses::cpu1.data 16936 # number of overall misses system.l2c.overall_misses::total 183846 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 225726 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 225726 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10534 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13904 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150448 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18862 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169310 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 85 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 60 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 41783 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 87265 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 34 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 13469 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 12858 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 155589 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 85 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 41783 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 237713 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 34 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13469 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31720 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 324899 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 85 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 41783 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 237713 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 34 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13469 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31720 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 324899 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946459 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.965875 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.951165 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.900978 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.967960 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.940619 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907609 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.838829 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899947 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033333 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.401551 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128207 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176331 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087494 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.202302 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.033333 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.401551 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.621489 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.176331 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.534269 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.565856 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.033333 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.401551 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.621489 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.176331 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.534269 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.565856 # miss rate for overall accesses +system.l2c.WritebackDirty_accesses::writebacks 225821 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 225821 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10514 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3365 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13879 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1181 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2002 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150561 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169489 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 79 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 69 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 41669 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 87293 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13541 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 12825 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 155560 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 79 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 41669 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 237854 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13541 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31753 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 325049 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 79 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 41669 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 237854 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13541 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31753 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 325049 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947023 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.969391 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.952446 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.897686 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.964437 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.937063 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.906868 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 96268 # number of writebacks -system.l2c.writebacks::total 96268 # number of writebacks +system.l2c.writebacks::writebacks 96240 # number of writebacks +system.l2c.writebacks::total 96240 # number of writebacks +system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 43996 # Transaction distribution -system.membus.trans_dist::ReadResp 75724 # Transaction distribution +system.membus.trans_dist::ReadResp 75748 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132458 # Transaction distribution -system.membus.trans_dist::CleanEvict 8718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60357 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15566 # Transaction distribution -system.membus.trans_dist::ReadExReq 152312 # Transaction distribution -system.membus.trans_dist::ReadExResp 151914 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31728 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution +system.membus.trans_dist::CleanEvict 8725 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution +system.membus.trans_dist::ReadExReq 152277 # Transaction distribution +system.membus.trans_dist::ReadExResp 151876 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 738406 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 847800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17954824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18144606 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20476894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 537526 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 537521 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 537526 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram +system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 537526 # Request fanout histogram +system.membus.snoop_fanout::total 537521 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1448,41 +1455,41 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 862694 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444199 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9376 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 486 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301670 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225726 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 64248 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60580 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41006 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213448 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213448 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257670 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1161849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1585074 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34444668 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10399858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44844526 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180900 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1118187 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.282688 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.451270 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 113289 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 802575 71.77% 71.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 315126 28.18% 99.96% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 486 0.04% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1118187 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index d5c7e4211..491924c10 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1225194 # Simulator instruction rate (inst/s) -host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23889629831 # Simulator tick rate (ticks/s) -host_mem_usage 578692 # Number of bytes of host memory used -host_seconds 116.53 # Real time elapsed on the host +host_inst_rate 888036 # Simulator instruction rate (inst/s) +host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17315504636 # Simulator tick rate (ticks/s) +host_mem_usage 573724 # Number of bytes of host memory used +host_seconds 160.77 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 28d366488..89a189084 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871806 # Number of seconds simulated -sim_ticks 2871806231000 # Number of ticks simulated -final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.869789 # Number of seconds simulated +sim_ticks 2869788970000 # Number of ticks simulated +final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717242 # Simulator instruction rate (inst/s) -host_op_rate 867543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15665668571 # Simulator tick rate (ticks/s) -host_mem_usage 616200 # Number of bytes of host memory used -host_seconds 183.32 # Real time elapsed on the host -sim_insts 131483712 # Number of instructions simulated -sim_ops 159036662 # Number of ops (including micro ops) simulated +host_inst_rate 543935 # Simulator instruction rate (inst/s) +host_op_rate 657921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11865725522 # Simulator tick rate (ticks/s) +host_mem_usage 611884 # Number of bytes of host memory used +host_seconds 241.86 # Real time elapsed on the host +sim_insts 131553572 # Number of instructions simulated +sim_ops 159121620 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8634112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 543380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 351296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12108656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1158756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1310136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8536192 # Number of bytes written to this memory +system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8553756 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2520 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5489 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198346 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133378 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137769 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 403494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 441625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3006509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 189212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 122326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4216390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2972412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2978528 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2972412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 447727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3006509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 189226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 122326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7194919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198346 # Number of read requests accepted -system.physmem.writeReqs 137769 # Number of write requests accepted -system.physmem.readBursts 198346 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137769 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12684736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 8566272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12108656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8553756 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198258 # Number of read requests accepted +system.physmem.writeReqs 139536 # Number of write requests accepted +system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11680 # Per bank write bursts -system.physmem.perBankRdBursts::1 11729 # Per bank write bursts -system.physmem.perBankRdBursts::2 12020 # Per bank write bursts -system.physmem.perBankRdBursts::3 11779 # Per bank write bursts -system.physmem.perBankRdBursts::4 20245 # Per bank write bursts -system.physmem.perBankRdBursts::5 11824 # Per bank write bursts -system.physmem.perBankRdBursts::6 12521 # Per bank write bursts -system.physmem.perBankRdBursts::7 12818 # Per bank write bursts -system.physmem.perBankRdBursts::8 12201 # Per bank write bursts -system.physmem.perBankRdBursts::9 12749 # Per bank write bursts -system.physmem.perBankRdBursts::10 11883 # Per bank write bursts -system.physmem.perBankRdBursts::11 11375 # Per bank write bursts -system.physmem.perBankRdBursts::12 11512 # Per bank write bursts -system.physmem.perBankRdBursts::13 11780 # Per bank write bursts -system.physmem.perBankRdBursts::14 10986 # Per bank write bursts -system.physmem.perBankRdBursts::15 11097 # Per bank write bursts -system.physmem.perBankWrBursts::0 8306 # Per bank write bursts -system.physmem.perBankWrBursts::1 8598 # Per bank write bursts -system.physmem.perBankWrBursts::2 8866 # Per bank write bursts -system.physmem.perBankWrBursts::3 8386 # Per bank write bursts -system.physmem.perBankWrBursts::4 7973 # Per bank write bursts -system.physmem.perBankWrBursts::5 8273 # Per bank write bursts -system.physmem.perBankWrBursts::6 8936 # Per bank write bursts -system.physmem.perBankWrBursts::7 8926 # Per bank write bursts -system.physmem.perBankWrBursts::8 8615 # Per bank write bursts -system.physmem.perBankWrBursts::9 9047 # Per bank write bursts -system.physmem.perBankWrBursts::10 8395 # Per bank write bursts -system.physmem.perBankWrBursts::11 8237 # Per bank write bursts -system.physmem.perBankWrBursts::12 8245 # Per bank write bursts -system.physmem.perBankWrBursts::13 7999 # Per bank write bursts -system.physmem.perBankWrBursts::14 7661 # Per bank write bursts -system.physmem.perBankWrBursts::15 7385 # Per bank write bursts +system.physmem.perBankRdBursts::0 11529 # Per bank write bursts +system.physmem.perBankRdBursts::1 11853 # Per bank write bursts +system.physmem.perBankRdBursts::2 12105 # Per bank write bursts +system.physmem.perBankRdBursts::3 12154 # Per bank write bursts +system.physmem.perBankRdBursts::4 20931 # Per bank write bursts +system.physmem.perBankRdBursts::5 12788 # Per bank write bursts +system.physmem.perBankRdBursts::6 12012 # Per bank write bursts +system.physmem.perBankRdBursts::7 12170 # Per bank write bursts +system.physmem.perBankRdBursts::8 12327 # Per bank write bursts +system.physmem.perBankRdBursts::9 12530 # Per bank write bursts +system.physmem.perBankRdBursts::10 11492 # Per bank write bursts +system.physmem.perBankRdBursts::11 10989 # Per bank write bursts +system.physmem.perBankRdBursts::12 11634 # Per bank write bursts +system.physmem.perBankRdBursts::13 11866 # Per bank write bursts +system.physmem.perBankRdBursts::14 10750 # Per bank write bursts +system.physmem.perBankRdBursts::15 10979 # Per bank write bursts +system.physmem.perBankWrBursts::0 8343 # Per bank write bursts +system.physmem.perBankWrBursts::1 8774 # Per bank write bursts +system.physmem.perBankWrBursts::2 9050 # Per bank write bursts +system.physmem.perBankWrBursts::3 8765 # Per bank write bursts +system.physmem.perBankWrBursts::4 8633 # Per bank write bursts +system.physmem.perBankWrBursts::5 9228 # Per bank write bursts +system.physmem.perBankWrBursts::6 8690 # Per bank write bursts +system.physmem.perBankWrBursts::7 8516 # Per bank write bursts +system.physmem.perBankWrBursts::8 8766 # Per bank write bursts +system.physmem.perBankWrBursts::9 8956 # Per bank write bursts +system.physmem.perBankWrBursts::10 8280 # Per bank write bursts +system.physmem.perBankWrBursts::11 8060 # Per bank write bursts +system.physmem.perBankWrBursts::12 8431 # Per bank write bursts +system.physmem.perBankWrBursts::13 8106 # Per bank write bursts +system.physmem.perBankWrBursts::14 7529 # Per bank write bursts +system.physmem.perBankWrBursts::15 7486 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 2871805791000 # Total gap between requests +system.physmem.numWrRetry 45 # Number of times write queue was full causing retry +system.physmem.totGap 2869788469000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188586 # Read request sizes (log2) +system.physmem.readPktSize::6 188498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133378 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 139268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 135145 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -180,159 +180,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 81 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.677497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.342742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.582310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46815 53.24% 53.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17415 19.81% 73.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6112 6.95% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3386 3.85% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 2.81% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1473 1.68% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 853 0.97% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 929 1.06% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8478 9.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87931 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.852584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.448326 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.835616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.963518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.817635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5349 83.27% 83.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 441 6.86% 90.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.14% 91.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 47 0.73% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.59% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.39% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 52 0.81% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.30% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 115 1.79% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.17% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.16% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.16% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 81 1.26% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.14% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.44% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 75 1.17% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.08% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.16% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads -system.physmem.totQLat 4482627455 # Total ticks spent queuing -system.physmem.totMemAccLat 8198858705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 990995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22616.80 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads +system.physmem.totQLat 4572923146 # Total ticks spent queuing +system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41366.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 165480 # Number of row buffer hits during reads -system.physmem.writeRowHits 78635 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.74 # Row buffer hit rate for writes -system.physmem.avgGap 8544116.72 # Average gap between requests -system.physmem.pageHitRate 73.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342929160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187114125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 816004800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 442350720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85984866225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647656379000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1923001828830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.614852 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740877422516 # Time in different power states -system.physmem_0.memoryStateTime::REF 95895800000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing +system.physmem.readRowHits 165757 # Number of row buffer hits during reads +system.physmem.writeRowHits 78775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes +system.physmem.avgGap 8495676.27 # Average gap between requests +system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.573415 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states +system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35029624984 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321829200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175601250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 729939600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 424984320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85018582845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648503996000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922747118015 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.526158 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742296701194 # Time in different power states -system.physmem_1.memoryStateTime::REF 95895800000 # Time in different power states +system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.487743 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states +system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33613567806 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -388,56 +390,60 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8733 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8733 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1652 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8733 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8733 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8733 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7215 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6137.175819 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7184 99.57% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 27 0.37% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7215 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5610 77.75% 77.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1605 22.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7215 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8733 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 7943 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8733 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7215 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7215 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 15948 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25746594 # DTB read hits -system.cpu0.dtb.read_misses 7520 # DTB read misses -system.cpu0.dtb.write_hits 19247313 # DTB write hits -system.cpu0.dtb.write_misses 1213 # DTB write misses +system.cpu0.dtb.read_hits 25156507 # DTB read hits +system.cpu0.dtb.read_misses 6829 # DTB read misses +system.cpu0.dtb.write_hits 18749940 # DTB write hits +system.cpu0.dtb.write_misses 1114 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3753 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1863 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25754114 # DTB read accesses -system.cpu0.dtb.write_accesses 19248526 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25163336 # DTB read accesses +system.cpu0.dtb.write_accesses 18751054 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44993907 # DTB hits -system.cpu0.dtb.misses 8733 # DTB misses -system.cpu0.dtb.accesses 45002640 # DTB accesses +system.cpu0.dtb.hits 43906447 # DTB hits +system.cpu0.dtb.misses 7943 # DTB misses +system.cpu0.dtb.accesses 43914390 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,39 +473,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3674 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6117.849264 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2266 87.97% 87.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 279 10.83% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3349 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121577578 # ITB inst hits -system.cpu0.itb.inst_misses 3674 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 119016789 # ITB inst hits +system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -508,768 +517,763 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121581252 # ITB inst accesses -system.cpu0.itb.hits 121577578 # DTB hits -system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121581252 # DTB accesses -system.cpu0.numCycles 5743612462 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses +system.cpu0.itb.hits 119016789 # DTB hits +system.cpu0.itb.misses 3349 # DTB misses +system.cpu0.itb.accesses 119020138 # DTB accesses +system.cpu0.numCycles 5739577940 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed -system.cpu0.committedInsts 117761026 # Number of instructions committed -system.cpu0.committedOps 142319020 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 125932364 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12772321 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16008283 # number of instructions that are conditional controls -system.cpu0.num_int_insts 125932364 # number of integer instructions -system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 231711074 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87448067 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 515452324 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53494266 # number of times the CC registers were written -system.cpu0.num_mem_refs 46150372 # number of memory refs -system.cpu0.num_load_insts 26005626 # Number of load instructions -system.cpu0.num_store_insts 20144746 # Number of store instructions -system.cpu0.num_idle_cycles 5456042423.958100 # Number of idle cycles -system.cpu0.num_busy_cycles 287570038.041900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949932 # Percentage of idle cycles -system.cpu0.Branches 29545974 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 99839256 68.33% 68.33% # Class of executed instruction -system.cpu0.op_class::IntMult 112113 0.08% 68.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8315 0.01% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::MemRead 26005626 17.80% 86.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 20144746 13.79% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed +system.cpu0.committedInsts 115352403 # Number of instructions committed +system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses +system.cpu0.num_func_calls 12675179 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123360698 # number of integer instructions +system.cpu0.num_fp_insts 9756 # number of float instructions +system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written +system.cpu0.num_mem_refs 45042977 # number of memory refs +system.cpu0.num_load_insts 25408336 # Number of load instructions +system.cpu0.num_store_insts 19634641 # Number of store instructions +system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles +system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles +system.cpu0.Branches 29113703 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146112371 # Class of executed instruction -system.cpu0.dcache.tags.replacements 733230 # number of replacements -system.cpu0.dcache.tags.tagsinuse 488.702331 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 44081285 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 733742 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 60.077364 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.702331 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954497 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.954497 # Average percentage of cache occupancy +system.cpu0.op_class::total 143145074 # Class of executed instruction +system.cpu0.dcache.tags.replacements 692159 # number of replacements +system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90665231 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90665231 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 24440591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 24440591 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18493820 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18493820 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326163 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 326163 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374037 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374037 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371586 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371586 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42934411 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42934411 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 43260574 # number of overall hits -system.cpu0.dcache.overall_hits::total 43260574 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418663 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418663 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 337563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 337563 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133473 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 133473 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22401 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22401 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19896 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19896 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 756226 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 756226 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 889699 # number of overall misses -system.cpu0.dcache.overall_misses::total 889699 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5670544000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5670544000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6922080500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6922080500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 345375500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 345375500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 506120500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 506120500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1857000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1857000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12592624500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12592624500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12592624500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12592624500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24859254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18831383 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18831383 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459636 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 459636 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396438 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396438 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391482 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391482 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 43690637 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 43690637 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 44150273 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44150273 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016841 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016841 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017926 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017926 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290388 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290388 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056506 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056506 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017309 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.017309 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020152 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.020152 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20506.040354 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20506.040354 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.860810 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.860810 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25438.304182 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25438.304182 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits +system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses +system.cpu0.dcache.overall_misses::total 848828 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16651.932756 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks -system.cpu0.dcache.writebacks::total 733230 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25286 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25286 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25286 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25286 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393378 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 393378 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337562 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337562 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106333 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106333 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6706 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6706 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19896 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19896 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 730940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 730940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 837273 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 837273 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31817 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60316 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4848200000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4848200000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6584514000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6584514000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737943000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737943000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103994500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103994500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 486281500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 486281500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016730 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016730 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018964 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018964 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12324.532638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12324.532638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19506.087771 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19506.087771 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16344.342772 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15507.679690 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24441.169079 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24441.169079 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks +system.cpu0.dcache.writebacks::total 692159 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1147026 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1103881 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244302703 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244302703 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120430031 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120430031 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120430031 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120430031 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 120430031 # number of overall hits -system.cpu0.icache.overall_hits::total 120430031 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1147547 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1147547 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1147547 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1147547 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1147547 # number of overall misses -system.cpu0.icache.overall_misses::total 1147547 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12241983500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12241983500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12241983500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12241983500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12241983500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12241983500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 121577578 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 121577578 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 121577578 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 121577578 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 121577578 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 121577578 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009439 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009439 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009439 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009439 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009439 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009439 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10667.958262 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10667.958262 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10667.958262 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits +system.cpu0.icache.overall_hits::total 117912387 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses +system.cpu0.icache.overall_misses::total 1104402 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks -system.cpu0.icache.writebacks::total 1147026 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks +system.cpu0.icache.writebacks::total 1103881 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11668210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11668210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11668210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11668210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11668210000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11668210000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009439 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009439 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009439 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009439 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10167.958262 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 273594 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3064483 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 289692 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.578418 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266444 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14597.123435 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.512757 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.144663 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1477.423728 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.890938 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000153 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090175 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981275 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15061 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 254 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 333 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3292 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7648 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3847 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919250 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 62842008 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 62842008 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11176 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4956 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 16132 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 502092 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 502092 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1349261 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1349261 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238948 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 238948 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1101688 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1101688 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411953 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 411953 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11176 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4956 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1101688 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 650901 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1768721 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11176 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4956 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1101688 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 650901 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1768721 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 156 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 75 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 231 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55191 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55191 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19886 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19886 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43422 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43422 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45859 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 45859 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94464 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94464 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 156 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 75 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 45859 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 137886 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 183976 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 156 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 75 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 45859 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 137886 # number of overall misses -system.cpu0.l2cache.overall_misses::total 183976 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4297500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2025500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 6323000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 162363000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 162363000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41658000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41658000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1712496 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1712496 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2783886000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2783886000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3283750500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3283750500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3241501500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3241501500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4297500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2025500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3283750500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6025387500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9315461000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4297500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2025500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3283750500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6025387500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9315461000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11332 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5031 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 16363 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 502092 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 502092 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1349261 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1349261 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55192 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55192 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19886 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19886 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282370 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 282370 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147547 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1147547 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 506417 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 506417 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11332 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5031 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1147547 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 788787 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1952697 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11332 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5031 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1147547 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 788787 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1952697 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014908 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.014117 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999982 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999982 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses +system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10462 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1867375 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 747798 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153777 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153777 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.039963 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.039963 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186534 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186534 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014908 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.039963 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.174808 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.094216 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013766 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014908 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.039963 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.174808 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.094216 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27006.666667 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27372.294372 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2941.838343 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2941.838343 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2094.840591 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2094.840591 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 171249.600000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 171249.600000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64112.339367 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64112.339367 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71605.366449 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71605.366449 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34314.675432 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34314.675432 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27006.666667 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71605.366449 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 50634.109884 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27548.076923 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27006.666667 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71605.366449 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks -system.cpu0.l2cache.writebacks::total 231848 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1793 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 59 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1852 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1852 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1852 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1852 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 156 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 75 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 231 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264648 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 264648 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55191 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55191 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19886 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19886 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41629 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41629 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45859 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45859 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94405 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94405 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 156 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 75 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45859 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136034 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 182124 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 156 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 75 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45859 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136034 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264648 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 446772 # number of overall MSHR misses +system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference +system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks +system.cpu0.l2cache.writebacks::total 227975 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1192 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 226 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 140 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94137 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 181431 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 226 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135785 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40839 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69338 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1575500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4937000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20425308140 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1407414000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1407414000 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 337427000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 337427000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1370496 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1370496 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2353646000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2353646000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3008596500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3008596500 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2668850500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2668850500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1575500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3008596500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5022496500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8036030000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3361500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1575500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3008596500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5022496500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147427 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147427 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.039963 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186418 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186418 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172460 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093268 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.039963 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172460 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228797 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21372.294372 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77179.151703 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25500.788172 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25500.788172 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16968.067988 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16968.067988 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 137049.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 137049.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56538.614908 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.614908 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65605.366449 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28270.224035 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28270.224035 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44123.948519 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 734457 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1378164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 189732 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 311664 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85807 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 301438 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 298033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575765 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3263 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460164 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2683424 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12059 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27146 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6182793 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146888760 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101708758 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 45328 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 248662970 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 986506 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2981817 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.122538 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330833 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 984362 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2619305 87.84% 87.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 359638 12.06% 99.90% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2874 0.10% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2981817 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3886437494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115091926 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1730342500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1266858980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 15821984 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1300,65 +1304,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2347 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2347 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 475 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1872 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2347 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2347 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2347 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1701 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4763.004778 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.18% 0.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 360 21.16% 21.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 989 58.14% 79.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 206 12.11% 91.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 34 2.00% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 60 3.53% 97.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 28 1.65% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 11 0.65% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 1 0.06% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.12% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.18% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.18% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1701 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1226 72.08% 72.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 475 27.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1701 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3352 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2347 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1701 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1701 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4048 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3334777 # DTB read hits -system.cpu1.dtb.read_misses 1951 # DTB read misses -system.cpu1.dtb.write_hits 2915290 # DTB write hits -system.cpu1.dtb.write_misses 396 # DTB write misses +system.cpu1.dtb.read_hits 3941258 # DTB read hits +system.cpu1.dtb.read_misses 2845 # DTB read misses +system.cpu1.dtb.write_hits 3419362 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3336728 # DTB read accesses -system.cpu1.dtb.write_accesses 2915686 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3944103 # DTB read accesses +system.cpu1.dtb.write_accesses 3419869 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6250067 # DTB hits -system.cpu1.dtb.misses 2347 # DTB misses -system.cpu1.dtb.accesses 6252414 # DTB accesses +system.cpu1.dtb.hits 7360620 # DTB hits +system.cpu1.dtb.misses 3352 # DTB misses +system.cpu1.dtb.accesses 7363972 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1388,44 +1391,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1376 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5121.103483 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 113 13.80% 13.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 572 69.84% 83.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 87 10.62% 94.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.81% 98.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 99.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.49% 99.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13921759 # ITB inst hits -system.cpu1.itb.inst_misses 1376 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16556610 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1434,642 +1438,640 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13923135 # ITB inst accesses -system.cpu1.itb.hits 13921759 # DTB hits -system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13923135 # DTB accesses -system.cpu1.numCycles 5742672703 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses +system.cpu1.itb.hits 16556610 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 16558356 # DTB accesses +system.cpu1.numCycles 5738649789 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2702 # number of quiesce instructions executed -system.cpu1.committedInsts 13722686 # Number of instructions committed -system.cpu1.committedOps 16717642 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 15156242 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 915130 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1497977 # number of instructions that are conditional controls -system.cpu1.num_int_insts 15156242 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27539507 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10698774 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 61342237 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5194989 # number of times the CC registers were written -system.cpu1.num_mem_refs 6464220 # number of memory refs -system.cpu1.num_load_insts 3439445 # Number of load instructions -system.cpu1.num_store_insts 3024775 # Number of store instructions -system.cpu1.num_idle_cycles 5696078911.641530 # Number of idle cycles -system.cpu1.num_busy_cycles 46593791.358469 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008114 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991886 # Percentage of idle cycles -system.cpu1.Branches 2464409 # Number of branches fetched -system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10544854 61.90% 61.90% # Class of executed instruction -system.cpu1.op_class::IntMult 24300 0.14% 62.04% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3186 0.02% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::MemRead 3439445 20.19% 82.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 3024775 17.75% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed +system.cpu1.committedInsts 16201169 # Number of instructions committed +system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 1029080 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17804295 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 32314180 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written +system.cpu1.num_mem_refs 7593995 # number of memory refs +system.cpu1.num_load_insts 4052758 # Number of load instructions +system.cpu1.num_store_insts 3541237 # Number of store instructions +system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles +system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles +system.cpu1.Branches 2921126 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction +system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 17036584 # Class of executed instruction -system.cpu1.dcache.tags.replacements 148452 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.602887 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6022671 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 148794 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.476572 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106290860000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.602887 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915240 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915240 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 36 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.667969 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12680857 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12680857 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3066042 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3066042 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2748534 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2748534 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41898 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41898 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61599 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61599 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5814576 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5814576 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5856474 # number of overall hits -system.cpu1.dcache.overall_hits::total 5856474 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112908 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112908 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 79472 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 79472 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24389 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24389 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16600 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16600 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23097 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23097 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 192380 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 192380 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 216769 # number of overall misses -system.cpu1.dcache.overall_misses::total 216769 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1761858500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1761858500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2707072000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2707072000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321180000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 321180000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 626224500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 626224500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5032000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5032000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4468930500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4468930500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4468930500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4468930500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178950 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3178950 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2828006 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2828006 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66287 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66287 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86485 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86485 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84696 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84696 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6006956 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6006956 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6073243 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6073243 # number of overall (read+write) accesses +system.cpu1.op_class::total 20092250 # Class of executed instruction +system.cpu1.dcache.tags.replacements 186389 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits +system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses +system.cpu1.dcache.overall_misses::total 255643 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028102 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.367930 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.367930 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272705 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272705 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032026 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.032026 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035692 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035692 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858 # average StoreCondReq miss latency +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks -system.cpu1.dcache.writebacks::total 148452 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 223 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112685 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 112685 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79472 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 79472 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23925 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23925 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4929 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4929 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23097 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23097 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 192157 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 192157 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 216082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 216082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3082 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5505 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1634927500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1634927500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2627600000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2627600000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437401500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437401500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91610500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91610500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 603174500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 603174500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272705 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272705 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031989 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031989 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035579 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035579 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18282.194357 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18586.021505 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26114.841754 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26114.841754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks +system.cpu1.dcache.writebacks::total 186389 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 463484 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 505464 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 28307504 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 28307504 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13457758 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13457758 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13457758 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13457758 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13457758 # number of overall hits -system.cpu1.icache.overall_hits::total 13457758 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463996 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463996 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463996 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463996 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463996 # number of overall misses -system.cpu1.icache.overall_misses::total 463996 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214067500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4214067500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4214067500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4214067500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4214067500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4214067500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13921754 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13921754 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13921754 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13921754 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13921754 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13921754 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.120320 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.120320 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9082.120320 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits +system.cpu1.icache.overall_hits::total 16050629 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses +system.cpu1.icache.overall_misses::total 505976 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks -system.cpu1.icache.writebacks::total 463484 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks +system.cpu1.icache.writebacks::total 505464 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982069500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982069500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982069500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3982069500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982069500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3982069500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.120320 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 31332 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1042665 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 46454 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.445107 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 44688 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14460.199894 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.270812 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.044709 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 491.965701 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.882581 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.030027 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.912871 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 960 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14131 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 920 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 423 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1663 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12045 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.058594 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21157161 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21157161 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2444 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1492 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 3936 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 91966 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 91966 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 509880 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 509880 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18290 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 18290 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455220 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 455220 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77690 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 77690 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2444 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1492 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 455220 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 95980 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 555136 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2444 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1492 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 455220 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 95980 # number of overall hits -system.cpu1.l2cache.overall_hits::total 555136 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 298 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 646 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29049 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29049 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23092 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23092 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32133 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32133 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8776 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 8776 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63849 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 63849 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 298 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8776 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 95982 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 105404 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 298 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8776 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 95982 # number of overall misses -system.cpu1.l2cache.overall_misses::total 105404 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6985500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5943500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 12929000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63798000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 63798000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54501000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54501000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4914000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4914000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1634363000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1634363000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 528873500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 528873500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1442259000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1442259000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6985500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5943500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 528873500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3076622000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3618424500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6985500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5943500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 528873500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3076622000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3618424500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1790 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 4582 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91966 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 91966 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 509880 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 509880 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29049 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29049 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23092 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23092 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50423 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 50423 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 463996 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 463996 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141539 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 141539 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1790 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 463996 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 191962 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 660540 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1790 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 463996 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 191962 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 660540 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.166480 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.140986 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits +system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses +system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.637269 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.637269 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018914 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018914 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.451105 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.451105 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.166480 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018914 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.500005 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.159572 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.124642 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.166480 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018914 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.500005 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.159572 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19944.630872 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20013.931889 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2196.220180 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2196.220180 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2360.168024 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2360.168024 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 982800 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 982800 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50862.446706 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50862.446706 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60263.616682 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60263.616682 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22588.591834 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22588.591834 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19944.630872 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60263.616682 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34329.100414 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20073.275862 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19944.630872 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60263.616682 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks -system.cpu1.l2cache.writebacks::total 26072 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 73 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 348 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 298 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 646 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20991 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 20991 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29049 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29049 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23092 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23092 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32060 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 32060 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8776 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8776 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63849 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63849 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 348 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 298 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8776 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95909 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 105331 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 348 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 298 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8776 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95909 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20991 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 126322 # number of overall MSHR misses +system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference +system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks +system.cpu1.l2cache.writebacks::total 33019 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3259 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5682 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4155500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9053000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 927478543 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 578238500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 578238500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 429963000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 429963000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4632000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4632000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1434110000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1434110000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476217500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476217500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1059165000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1059165000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4155500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476217500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2493275000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2978545500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4897500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4155500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476217500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493275000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2078,120 +2080,120 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.635821 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.635821 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018914 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451105 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451105 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159462 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191241 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 926400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 926400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 119114 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 519969 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 86535 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 25223 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70168 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84814 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55180 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463996 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 214635 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391830 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7011 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2125683 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59359428 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24498524 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83876280 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 355270 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 998881 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.185518 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.393336 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 388756 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 815375 81.63% 81.63% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 181702 18.19% 99.82% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1804 0.18% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 998881 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1279425500 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79453408 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 696171000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 318356500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31021 # Transaction distribution -system.iobus.trans_dist::ReadResp 31021 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2210,11 +2212,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2233,23 +2235,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48736000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 93000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2263,7 +2265,7 @@ system.iobus.reqLayer16.occupancy 48000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2271,25 +2273,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32043500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187096722 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.380038 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290749964000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.380038 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898752 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898752 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2303,14 +2305,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2327,22 +2329,22 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2351,14 +2353,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2367,540 +2369,546 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency -system.l2c.tags.replacements 124374 # number of replacements -system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use -system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency +system.l2c.tags.replacements 126308 # number of replacements +system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use +system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.161578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7408.035333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2772.307356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35669.502662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1440.723489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 421.652649 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1798.018803 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205337 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.113038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042302 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544273 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.006434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027436 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.960865 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32172 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31879 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2433 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29060 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.490906 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.486435 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5838028 # Number of tag accesses -system.l2c.tags.data_accesses 5838028 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257920 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257920 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1955 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34214 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2096 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 941 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3037 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4136 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1368 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5504 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 86 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28311 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47114 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47400 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 25 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6412 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3327 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 137845 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 86 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47400 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 25 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3327 # number of demand (read+write) hits -system.l2c.demand_hits::total 143349 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 86 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28311 # number of overall hits -system.l2c.overall_hits::cpu0.data 51250 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47400 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 25 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6412 # number of overall hits -system.l2c.overall_hits::cpu1.data 6454 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3327 # number of overall hits -system.l2c.overall_hits::total 143349 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9332 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2240 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11572 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1282 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1888 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11165 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18870 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5890164 # Number of tag accesses +system.l2c.tags.data_accesses 5890164 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits +system.l2c.demand_hits::total 150368 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits +system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits +system.l2c.overall_hits::cpu0.data 49491 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits +system.l2c.overall_hits::cpu1.data 10698 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits +system.l2c.overall_hits::total 150368 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17548 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8846 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 135065 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 796 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5489 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 170116 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17548 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 135065 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8501 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5489 # number of demand (read+write) misses -system.l2c.demand_misses::total 188986 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses +system.l2c.demand_misses::total 188931 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17548 # number of overall misses -system.l2c.overall_misses::cpu0.data 20011 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 135065 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses -system.l2c.overall_misses::cpu1.data 8501 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5489 # number of overall misses -system.l2c.overall_misses::total 188986 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 27811000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6496500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 34307500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 5695500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2358500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 8054000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1626743500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1013044000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2639787500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 809500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2308407000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1204319000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 315452500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 119571000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 24395784032 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 809500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2308407000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2831062500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 315452500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1132615000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 27035571532 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 809500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2308407000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2831062500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19595366985 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 315452500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1132615000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 851586047 # number of overall miss cycles -system.l2c.overall_miss_latency::total 27035571532 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 257920 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 257920 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 41591 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4195 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45786 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2702 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2223 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4925 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9073 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24374 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 92 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 70 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 45859 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 55960 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182465 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 25 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 16 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 8776 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 5882 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8816 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 307961 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 70 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 45859 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 71261 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182465 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 16 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8776 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 14955 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8816 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 332335 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 45859 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 71261 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182465 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 16 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8776 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 14955 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8816 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 332335 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.224375 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.533969 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.252741 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.224278 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.576698 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.383350 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.729691 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.849223 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.774186 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.382651 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158077 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.269371 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.135328 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.552395 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.382651 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.280813 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.269371 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.568439 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.568661 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.065217 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.382651 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.280813 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740224 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.269371 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.568439 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.622618 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.568661 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2980.175739 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2900.223214 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2964.699274 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9398.514851 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1839.703588 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4265.889831 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145700.268697 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131478.780013 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 139893.349232 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131548.153636 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136142.776396 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133440.143824 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 150214.824121 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 143406.757930 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131548.153636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 141475.313578 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 133440.143824 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 133233.149041 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 143055.948758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 134916.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131548.153636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 141475.313578 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145081.012735 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 133440.143824 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 133233.149041 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 143055.948758 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses +system.l2c.overall_misses::cpu0.data 20230 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses +system.l2c.overall_misses::cpu1.data 8887 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses +system.l2c.overall_misses::total 188931 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 97172 # number of writebacks -system.l2c.writebacks::total 97172 # number of writebacks +system.l2c.writebacks::writebacks 98955 # number of writebacks +system.l2c.writebacks::total 98955 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 2825 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 2825 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9332 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2240 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11572 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 606 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1282 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1888 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11165 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7705 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18870 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3251 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3251 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8680 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2870 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11550 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 542 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1323 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1865 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11368 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8031 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19399 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17544 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8846 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2355 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 796 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 170103 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17603 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8862 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2278 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 856 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 169518 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17544 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20011 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2355 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8501 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 188973 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17603 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20230 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2278 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8887 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 188917 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17544 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20011 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 135065 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2355 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8501 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5489 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 188973 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17603 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20230 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2278 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8887 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 188917 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3079 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44095 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30922 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3092 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44083 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5502 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 75017 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 678754000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 162023000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 840777000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 45192500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 94781500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 139974000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1515091017 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 935989514 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2451080531 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 749500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2132646516 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1115857006 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 291145013 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 111607507 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 22693617289 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 749500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2132646516 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2630948023 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 291145013 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1047597021 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25144697820 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 749500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2132646516 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2630948023 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18244681120 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 291145013 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1047597021 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25144697820 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5542 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 74996 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 208012000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 65421000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 273433000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 13993000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729691 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.849223 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158077 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.135328 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.552352 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.568622 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.065217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.028571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.382564 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.280813 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740224 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.268345 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.568439 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.622618 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.568622 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72734.033433 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72331.696429 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72656.152783 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74575.082508 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73932.527301 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74138.771186 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135700.046305 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121478.197794 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129892.979915 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126142.550983 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 140210.435930 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133411.035014 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 124916.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121559.878933 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131475.089851 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135080.747196 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123628.455626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 44095 # Transaction distribution -system.membus.trans_dist::ReadResp 214453 # Transaction distribution -system.membus.trans_dist::WriteReq 30922 # Transaction distribution -system.membus.trans_dist::WriteResp 30922 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution -system.membus.trans_dist::CleanEvict 14958 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 39426 # Transaction distribution -system.membus.trans_dist::ReadExResp 18801 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170358 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 44083 # Transaction distribution +system.membus.trans_dist::ReadResp 213856 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution +system.membus.trans_dist::CleanEvict 15700 # Transaction distribution +system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39863 # Transaction distribution +system.membus.trans_dist::ReadExResp 19313 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 651465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846152 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18344268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18534678 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20852822 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120859 # Total snoops (count) -system.membus.snoop_fanout::samples 582572 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123593 # Total snoops (count) +system.membus.snoop_fanout::samples 436796 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 582572 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 582572 # Request fanout histogram -system.membus.reqLayer0.occupancy 88269500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 436796 # Request fanout histogram +system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11360500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 969988933 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1109172490 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1385877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2943,52 +2951,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 961097 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 519247 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 138785 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20683 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19864 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 819 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44098 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 467805 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 391320 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 106223 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107477 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42889 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150366 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50473 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50473 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 423722 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241271 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253131 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1494402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34264962 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3773844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38038806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 438960 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 896783 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.336520 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474448 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 378680 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 595817 66.44% 66.44% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 300147 33.47% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 819 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 896783 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 864823852 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 645977888 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 202227821 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index da0ada0fc..db033150d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812558 # Simulator instruction rate (inst/s) -host_op_rate 979692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21023218607 # Simulator tick rate (ticks/s) -host_mem_usage 578440 # Number of bytes of host memory used -host_seconds 138.40 # Real time elapsed on the host +host_inst_rate 581636 # Simulator instruction rate (inst/s) +host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15048595995 # Simulator tick rate (ticks/s) +host_mem_usage 573724 # Number of bytes of host memory used +host_seconds 193.35 # Real time elapsed on the host sim_insts 112457033 # Number of instructions simulated sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 254a8cf36..bc56e0971 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,27 +1,27 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854535000 # Number of ticks simulated -final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783853866500 # Number of ticks simulated +final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1181524 # Simulator instruction rate (inst/s) -host_op_rate 1438316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23038118447 # Simulator tick rate (ticks/s) -host_mem_usage 579724 # Number of bytes of host memory used -host_seconds 120.84 # Real time elapsed on the host -sim_insts 142771651 # Number of instructions simulated -sim_ops 173801592 # Number of ops (including micro ops) simulated +host_inst_rate 806647 # Simulator instruction rate (inst/s) +host_op_rate 981963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15728650419 # Simulator tick rate (ticks/s) +host_mem_usage 576800 # Number of bytes of host memory used +host_seconds 176.99 # Real time elapsed on the host +sim_insts 142770436 # Number of instructions simulated +sim_ops 173800089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 482816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5664516 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5664388 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533000 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533064 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 724196 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 482816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory @@ -32,42 +32,42 @@ system.physmem.bytes_written::total 8858100 # Nu system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 19769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73331 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73334 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7544 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88507 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189177 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 138134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory system.physmem.num_writes::total 142515 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1673938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1674007 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034729 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260142 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173434 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175661 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175661 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034732 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324797 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5703 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5703 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5703 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5703 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5701 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5701 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5701 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3075 65.68% 65.68% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1607 34.32% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4682 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3076 65.73% 65.73% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1604 34.27% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4680 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5701 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5703 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5701 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4680 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4682 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997085 # DTB read hits -system.cpu0.dtb.read_misses 4809 # DTB read misses -system.cpu0.dtb.write_hits 11281852 # DTB write hits -system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.read_hits 15997245 # DTB read hits +system.cpu0.dtb.read_misses 4805 # DTB read misses +system.cpu0.dtb.write_hits 11281011 # DTB write hits +system.cpu0.dtb.write_misses 896 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3231 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16001894 # DTB read accesses -system.cpu0.dtb.write_accesses 11282746 # DTB write accesses +system.cpu0.dtb.read_accesses 16002050 # DTB read accesses +system.cpu0.dtb.write_accesses 11281907 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278937 # DTB hits -system.cpu0.dtb.misses 5703 # DTB misses -system.cpu0.dtb.accesses 27284640 # DTB accesses +system.cpu0.dtb.hits 27278256 # DTB hits +system.cpu0.dtb.misses 5701 # DTB misses +system.cpu0.dtb.accesses 27283957 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -192,8 +192,8 @@ system.cpu0.itb.walker.walkWaitTime::total 2590 # system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1366 72.81% 72.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 510 27.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1367 72.87% 72.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 509 27.13% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 1876 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2590 # Table walker requests started/completed, data/inst @@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1876 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1876 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 4466 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74797685 # ITB inst hits +system.cpu0.itb.inst_hits 74798476 # ITB inst hits system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -219,40 +219,40 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800275 # ITB inst accesses -system.cpu0.itb.hits 74797685 # DTB hits +system.cpu0.itb.inst_accesses 74801066 # ITB inst accesses +system.cpu0.itb.hits 74798476 # DTB hits system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800275 # DTB accesses -system.cpu0.numCycles 5536444787 # number of cpu cycles simulated +system.cpu0.itb.accesses 74801066 # DTB accesses +system.cpu0.numCycles 5536444785 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.committedInsts 72639178 # Number of instructions committed -system.cpu0.committedOps 87981810 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77492203 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses -system.cpu0.num_func_calls 8694463 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459638 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77492203 # number of integer instructions -system.cpu0.num_fp_insts 5289 # number of float instructions -system.cpu0.num_int_register_reads 144072055 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447583 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read +system.cpu0.committedInsts 72639773 # Number of instructions committed +system.cpu0.committedOps 87981470 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77491639 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses +system.cpu0.num_func_calls 8694385 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459738 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77491639 # number of integer instructions +system.cpu0.num_fp_insts 5273 # number of float instructions +system.cpu0.num_int_register_reads 144069521 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447635 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268879809 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833575 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909868 # number of memory refs -system.cpu0.num_load_insts 16164638 # Number of load instructions -system.cpu0.num_store_insts 11745230 # Number of store instructions -system.cpu0.num_idle_cycles 5353616276.220466 # Number of idle cycles -system.cpu0.num_busy_cycles 182828510.779535 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles -system.cpu0.Branches 18600800 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776579 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction +system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31834253 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909194 # number of memory refs +system.cpu0.num_load_insts 16164821 # Number of load instructions +system.cpu0.num_store_insts 11744373 # Number of store instructions +system.cpu0.num_idle_cycles 5353617701.078379 # Number of idle cycles +system.cpu0.num_busy_cycles 182827083.921621 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles +system.cpu0.Branches 18600825 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776865 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59682 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -276,24 +276,24 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164638 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11745230 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164821 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11744373 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752729 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819392 # number of replacements +system.cpu0.op_class::total 89752341 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819388 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783791 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597669 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783376 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597483 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830580 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929356 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,90 +301,90 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234764 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234764 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305281 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14823482 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128763 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894769 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445022 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234992 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222324 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219233084 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219233084 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305417 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128492 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10893994 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339645 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234995 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222321 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236691 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223431 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26200050 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268504 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468554 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385805 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477790 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863595 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197438 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198880 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396318 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164088 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61721 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116066 # number of SoftPFReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199411 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468137 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385163 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863180 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137507 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164158 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301665 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54352 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61713 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335013 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389358 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses -system.cpu0.dcache.overall_misses::total 814047 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502719 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032344 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609110 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239655 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226290 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334959 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363019 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697978 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses +system.cpu0.dcache.overall_misses::total 814043 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502869 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239658 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226287 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236691 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26535063 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631472 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26775163 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902479 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677642 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534370 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166115 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774474 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677223 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012470 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014134 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227747 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227087 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012465 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014140 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226369 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227720 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227085 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012624 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013631 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014540 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015788 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -393,14 +393,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks system.cpu0.dcache.writebacks::total 682241 # number of writebacks -system.cpu0.icache.tags.replacements 1698998 # number of replacements +system.cpu0.icache.tags.replacements 1698997 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 145340473 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699509 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519096 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121661 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542018 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121595 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542085 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -410,43 +410,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740789 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740789 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955506 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71386251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341757 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955506 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71386251 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341757 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955506 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71386251 # number of overall hits -system.cpu0.icache.overall_hits::total 145341757 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844055 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855461 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699516 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844055 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855461 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699516 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844055 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855461 # number of overall misses -system.cpu0.icache.overall_misses::total 1699516 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799561 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241712 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799561 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72241712 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799561 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72241712 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148739503 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148739503 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73956240 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71384233 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145340473 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73956240 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71384233 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145340473 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73956240 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71384233 # number of overall hits +system.cpu0.icache.overall_hits::total 145340473 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844112 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855403 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699515 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844112 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855403 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699515 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844112 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855403 # number of overall misses +system.cpu0.icache.overall_misses::total 1699515 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72239636 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147039988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74800352 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72239636 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147039988 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74800352 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72239636 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147039988 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011285 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011841 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011285 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011841 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011285 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011841 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -454,8 +454,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks -system.cpu0.icache.writebacks::total 1698998 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1698997 # number of writebacks +system.cpu0.icache.writebacks::total 1698997 # number of writebacks system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,45 +485,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6189 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 6190 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6190 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6190 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6190 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6190 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::4K 3698 73.27% 73.27% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::total 5047 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6190 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6190 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5047 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11237 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15527164 # DTB read hits -system.cpu1.dtb.read_misses 5392 # DTB read misses -system.cpu1.dtb.write_hits 11842009 # DTB write hits -system.cpu1.dtb.write_misses 797 # DTB write misses +system.cpu1.dtb.read_hits 15526731 # DTB read hits +system.cpu1.dtb.read_misses 5394 # DTB read misses +system.cpu1.dtb.write_hits 11842705 # DTB write hits +system.cpu1.dtb.write_misses 796 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3189 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15532556 # DTB read accesses -system.cpu1.dtb.write_accesses 11842806 # DTB write accesses +system.cpu1.dtb.read_accesses 15532125 # DTB read accesses +system.cpu1.dtb.write_accesses 11843501 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27369173 # DTB hits -system.cpu1.dtb.misses 6189 # DTB misses -system.cpu1.dtb.accesses 27375362 # DTB accesses +system.cpu1.dtb.hits 27369436 # DTB hits +system.cpu1.dtb.misses 6190 # DTB misses +system.cpu1.dtb.accesses 27375626 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -571,7 +571,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72239602 # ITB inst hits +system.cpu1.itb.inst_hits 72237526 # ITB inst hits system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -588,40 +588,40 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72242653 # ITB inst accesses -system.cpu1.itb.hits 72239602 # DTB hits +system.cpu1.itb.inst_accesses 72240577 # ITB inst accesses +system.cpu1.itb.hits 72237526 # DTB hits system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72242653 # DTB accesses -system.cpu1.numCycles 88015617 # number of cpu cycles simulated +system.cpu1.itb.accesses 72240577 # DTB accesses +system.cpu1.numCycles 88014282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70132473 # Number of instructions committed -system.cpu1.committedOps 85819782 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75669076 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses -system.cpu1.num_func_calls 8179499 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270637 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75669076 # number of integer instructions -system.cpu1.num_fp_insts 6195 # number of float instructions -system.cpu1.num_int_register_reads 140985520 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52730881 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read +system.cpu1.committedInsts 70130663 # Number of instructions committed +system.cpu1.committedOps 85818619 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75668279 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses +system.cpu1.num_func_calls 8179291 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270395 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75668279 # number of integer instructions +system.cpu1.num_fp_insts 6211 # number of float instructions +system.cpu1.num_int_register_reads 140985352 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52729833 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261969734 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30530329 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028748 # number of memory refs -system.cpu1.num_load_insts 15690947 # Number of load instructions -system.cpu1.num_store_insts 12337801 # Number of store instructions -system.cpu1.num_idle_cycles 85360941.513009 # Number of idle cycles -system.cpu1.num_busy_cycles 2654675.486991 # Number of busy cycles +system.cpu1.num_cc_register_reads 261966626 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30529225 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028988 # number of memory refs +system.cpu1.num_load_insts 15690476 # Number of load instructions +system.cpu1.num_store_insts 12338512 # Number of store instructions +system.cpu1.num_idle_cycles 85359668.730648 # Number of idle cycles +system.cpu1.num_busy_cycles 2654613.269352 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17796178 # Number of branches fetched -system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59375458 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57193 0.07% 67.95% # Class of executed instruction +system.cpu1.Branches 17795727 # Number of branches fetched +system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59374032 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57191 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -645,15 +645,15 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690947 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12337801 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690476 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12338512 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87465703 # Class of executed instruction +system.cpu1.op_class::total 87464517 # Class of executed instruction system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -705,12 +705,12 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909889 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409732009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909889 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -750,20 +750,20 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.replacements 109907 # number of replacements -system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use -system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.846730 # Average number of references to valid blocks. +system.l2c.tags.replacements 109908 # number of replacements +system.l2c.tags.tagsinuse 65155.315514 # Cycle average of tags in use +system.l2c.tags.total_refs 4528029 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175189 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 25.846537 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.087166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.089063 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5143.112513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4734.411223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5143.111803 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4734.405961 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4025.485555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2484.315404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4025.485403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2484.320162 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -783,155 +783,155 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40604434 # Number of tag accesses -system.l2c.tags.data_accesses 40604434 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2284 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4980 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2427 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14406 # number of ReadReq hits +system.l2c.tags.tag_accesses 40604397 # Number of tag accesses +system.l2c.tags.data_accesses 40604397 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4983 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits +system.l2c.ReadReq_hits::total 14414 # number of ReadReq hits system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666999 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 1666994 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666994 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72343 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78788 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151131 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833292 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847909 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246688 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258762 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505450 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2284 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833292 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319031 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4980 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337550 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352188 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2284 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833292 # number of overall hits -system.l2c.overall_hits::cpu0.data 319031 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4980 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2427 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847909 # number of overall hits -system.l2c.overall_hits::cpu1.data 337550 # number of overall hits -system.l2c.overall_hits::total 2352188 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 72274 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151132 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833349 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847851 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681200 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246710 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258734 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505444 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4983 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847851 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337592 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352190 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4717 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833349 # number of overall hits +system.l2c.overall_hits::cpu0.data 318984 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4983 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847851 # number of overall hits +system.l2c.overall_hits::cpu1.data 337592 # number of overall hits +system.l2c.overall_hits::total 2352190 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1248 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1480 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83806 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83804 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147777 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 10754 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 7544 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9758 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5805 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9757 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5806 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 10754 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73730 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7544 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89611 # number of demand (read+write) misses -system.l2c.demand_misses::total 181645 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89610 # number of demand (read+write) misses +system.l2c.demand_misses::total 181646 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.inst 10754 # number of overall misses -system.l2c.overall_misses::cpu0.data 73728 # number of overall misses +system.l2c.overall_misses::cpu0.data 73730 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7544 # number of overall misses -system.l2c.overall_misses::cpu1.data 89611 # number of overall misses -system.l2c.overall_misses::total 181645 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2285 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4982 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14414 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 89610 # number of overall misses +system.l2c.overall_misses::total 181646 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4722 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4985 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14422 # number of ReadReq accesses(hits+misses) system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666994 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666994 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136313 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162594 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844046 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855453 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256446 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264567 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2285 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844046 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4982 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533833 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2285 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844046 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4982 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533833 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 136247 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162662 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298909 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 844103 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855395 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1699498 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 256467 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264540 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 521007 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4722 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844103 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4985 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855395 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427202 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533836 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4722 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844103 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4985 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855395 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427202 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533836 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.000555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469288 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515431 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515203 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012741 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012740 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008819 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038051 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021942 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038044 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021948 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012740 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187745 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209783 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209760 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012740 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187745 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209783 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209760 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -941,48 +941,54 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 101944 # number of writebacks system.l2c.writebacks::total 101944 # number of writebacks +system.membus.snoop_filter.tot_requests 367178 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 155396 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::WritebackDirty 138134 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145997 # Transaction distribution -system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadExReq 145998 # Transaction distribution +system.membus.trans_dist::ReadExResp 145998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 613926 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723284 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091708 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254745 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586201 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586265 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 434809 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 434811 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012707 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112006 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 429286 98.73% 98.73% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.27% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434809 # Request fanout histogram +system.membus.snoop_fanout::total 434811 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1024,47 +1030,47 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5060329 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540912 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5060315 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39264 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 71251 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291780 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 71253 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291775 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137151 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1698997 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137147 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116074 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581970 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96321057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313986697 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 182969 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5322182 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018547 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134917 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298909 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1699515 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521007 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116071 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581958 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320801 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313986321 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 115322 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5254527 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018786 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.135767 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5223474 98.15% 98.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98708 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5155817 98.12% 98.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98710 1.88% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5322182 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5254527 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e91a37dbe..0b3858068 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909645 # Number of seconds simulated -sim_ticks 2909644861500 # Number of ticks simulated -final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903880 # Number of seconds simulated +sim_ticks 2903879904500 # Number of ticks simulated +final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753896 # Simulator instruction rate (inst/s) -host_op_rate 908960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19506336140 # Simulator tick rate (ticks/s) -host_mem_usage 580236 # Number of bytes of host memory used -host_seconds 149.16 # Real time elapsed on the host -sim_insts 112454211 # Number of instructions simulated -sim_ops 135584166 # Number of ops (including micro ops) simulated +host_inst_rate 558564 # Simulator instruction rate (inst/s) +host_op_rate 673462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14421337908 # Simulator tick rate (ticks/s) +host_mem_usage 577056 # Number of bytes of host memory used +host_seconds 201.36 # Real time elapsed on the host +sim_insts 112472356 # Number of instructions simulated +sim_ops 135608165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 522464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 557092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4007584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 664132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4241316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 629760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4985028 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 522464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 664132 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73321 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10181064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 557092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 629760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7592448 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 7609972 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 63137 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66287 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77892 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 179563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1601691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 168052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118632 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1380079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 110 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 228252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1457675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 179563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 228252 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587737 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 179563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1604733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 216868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1716678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 216868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2614587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2620622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2614587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1386111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 228252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1460655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166625 # Number of read requests accepted -system.physmem.writeReqs 121754 # Number of write requests accepted -system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10658176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5824 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 91 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 216868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1716681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6126643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168052 # Number of read requests accepted +system.physmem.writeReqs 123013 # Number of write requests accepted +system.physmem.readBursts 168052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123013 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10746816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7623936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10181064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7609972 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10080 # Per bank write bursts -system.physmem.perBankRdBursts::1 9979 # Per bank write bursts -system.physmem.perBankRdBursts::2 10697 # Per bank write bursts -system.physmem.perBankRdBursts::3 10657 # Per bank write bursts -system.physmem.perBankRdBursts::4 18793 # Per bank write bursts -system.physmem.perBankRdBursts::5 9662 # Per bank write bursts -system.physmem.perBankRdBursts::6 9670 # Per bank write bursts -system.physmem.perBankRdBursts::7 10491 # Per bank write bursts -system.physmem.perBankRdBursts::8 9280 # Per bank write bursts -system.physmem.perBankRdBursts::9 9982 # Per bank write bursts -system.physmem.perBankRdBursts::10 9231 # Per bank write bursts -system.physmem.perBankRdBursts::11 8678 # Per bank write bursts -system.physmem.perBankRdBursts::12 9823 # Per bank write bursts -system.physmem.perBankRdBursts::13 10380 # Per bank write bursts -system.physmem.perBankRdBursts::14 9718 # Per bank write bursts -system.physmem.perBankRdBursts::15 9413 # Per bank write bursts -system.physmem.perBankWrBursts::0 7393 # Per bank write bursts -system.physmem.perBankWrBursts::1 7263 # Per bank write bursts -system.physmem.perBankWrBursts::2 8284 # Per bank write bursts -system.physmem.perBankWrBursts::3 8168 # Per bank write bursts -system.physmem.perBankWrBursts::4 7485 # Per bank write bursts -system.physmem.perBankWrBursts::5 7265 # Per bank write bursts -system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7667 # Per bank write bursts -system.physmem.perBankWrBursts::8 7080 # Per bank write bursts -system.physmem.perBankWrBursts::9 7523 # Per bank write bursts -system.physmem.perBankWrBursts::10 6694 # Per bank write bursts -system.physmem.perBankWrBursts::11 6470 # Per bank write bursts -system.physmem.perBankWrBursts::12 7527 # Per bank write bursts -system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7260 # Per bank write bursts -system.physmem.perBankWrBursts::15 6788 # Per bank write bursts +system.physmem.perBankRdBursts::0 9950 # Per bank write bursts +system.physmem.perBankRdBursts::1 9634 # Per bank write bursts +system.physmem.perBankRdBursts::2 10758 # Per bank write bursts +system.physmem.perBankRdBursts::3 10205 # Per bank write bursts +system.physmem.perBankRdBursts::4 18891 # Per bank write bursts +system.physmem.perBankRdBursts::5 10113 # Per bank write bursts +system.physmem.perBankRdBursts::6 10004 # Per bank write bursts +system.physmem.perBankRdBursts::7 10172 # Per bank write bursts +system.physmem.perBankRdBursts::8 9614 # Per bank write bursts +system.physmem.perBankRdBursts::9 10312 # Per bank write bursts +system.physmem.perBankRdBursts::10 9754 # Per bank write bursts +system.physmem.perBankRdBursts::11 9150 # Per bank write bursts +system.physmem.perBankRdBursts::12 10004 # Per bank write bursts +system.physmem.perBankRdBursts::13 10185 # Per bank write bursts +system.physmem.perBankRdBursts::14 9904 # Per bank write bursts +system.physmem.perBankRdBursts::15 9269 # Per bank write bursts +system.physmem.perBankWrBursts::0 7437 # Per bank write bursts +system.physmem.perBankWrBursts::1 7207 # Per bank write bursts +system.physmem.perBankWrBursts::2 8535 # Per bank write bursts +system.physmem.perBankWrBursts::3 7773 # Per bank write bursts +system.physmem.perBankWrBursts::4 7341 # Per bank write bursts +system.physmem.perBankWrBursts::5 7352 # Per bank write bursts +system.physmem.perBankWrBursts::6 7319 # Per bank write bursts +system.physmem.perBankWrBursts::7 7510 # Per bank write bursts +system.physmem.perBankWrBursts::8 7314 # Per bank write bursts +system.physmem.perBankWrBursts::9 7939 # Per bank write bursts +system.physmem.perBankWrBursts::10 7417 # Per bank write bursts +system.physmem.perBankWrBursts::11 7018 # Per bank write bursts +system.physmem.perBankWrBursts::12 7498 # Per bank write bursts +system.physmem.perBankWrBursts::13 7483 # Per bank write bursts +system.physmem.perBankWrBursts::14 7310 # Per bank write bursts +system.physmem.perBankWrBursts::15 6671 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 2909644504500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2903879542500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157053 # Read request sizes (log2) +system.physmem.readPktSize::6 158480 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117373 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118632 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,179 +165,181 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.672197 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.145957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.231527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21388 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14603 24.93% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5975 10.20% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3225 5.51% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2561 4.37% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 2.61% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1012 1.73% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1135 1.94% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7154 12.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58581 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.894255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 552.382236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5567 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.602107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.973761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.010341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21606 36.77% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14724 25.05% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5582 9.50% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3238 5.51% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2495 4.25% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1555 2.65% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 968 1.65% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1073 1.83% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7526 12.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.881665 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 551.015664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5570 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5570 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.155117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.796345 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.496905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.31% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 13 0.23% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4758 85.42% 86.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 105 1.89% 88.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 66 1.18% 89.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.26% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 40 0.72% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.31% 91.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 0.86% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 92.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 152 2.73% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.14% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.18% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 62 1.11% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.16% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.48% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 105 1.89% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.13% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.09% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5570 # Writes before turning the bus around for reads -system.physmem.totQLat 1610742500 # Total ticks spent queuing -system.physmem.totMemAccLat 4733255000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9672.15 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5814 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5814 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.489164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.609616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.405574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 19 0.33% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 12 0.21% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.07% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 14 0.24% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4869 83.75% 84.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 76 1.31% 85.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 108 1.86% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 83 1.43% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 296 5.09% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 49 0.84% 95.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.22% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.19% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 16 0.28% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 172 2.96% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.14% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.07% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.10% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5814 # Writes before turning the bus around for reads +system.physmem.totQLat 1475229250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623710500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8785.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28422.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27535.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing -system.physmem.readRowHits 136266 # Number of row buffer hits during reads -system.physmem.writeRowHits 89520 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10089654.60 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230678280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125866125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702226200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90291916755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666582969500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948370345100 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624992 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772326098500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97159400000 # Time in different power states +system.physmem.avgWrQLen 12.36 # Average write queue length when enqueuing +system.physmem.readRowHits 138207 # Number of row buffer hits during reads +system.physmem.writeRowHits 90068 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes +system.physmem.avgGap 9976739.02 # Average gap between requests +system.physmem.pageHitRate 79.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228947040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 124921500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 699870600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 391871520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189666943440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87330979935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665718515750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944162049785 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.506247 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770909332000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96966740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40158524000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35998339250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 212194080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 115780500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596731200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370662480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88418921265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668225948000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947984023925 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.492219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775082980250 # Time in different power states -system.physmem_1.memoryStateTime::REF 97159400000 # Time in different power states +system.physmem_1.actEnergy 215331480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 117492375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 609889800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 380052000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189666943440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85596128505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667240315250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943826152850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.390575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773463023000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96966740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37402333250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33450042500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -383,59 +389,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6403 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6403 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1830 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4572 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6402 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6402 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6402 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5332 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7407.871184 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4008 75.17% 75.17% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1320 24.76% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5332 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3528 66.18% 66.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1803 33.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5331 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6403 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6844 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6844 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2237 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4607 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6844 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6844 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5812 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12925.584997 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11265.166351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6611.780154 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 1551 26.69% 26.69% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 2959 50.91% 77.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1234 21.23% 98.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 66 1.14% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5812 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3596 61.87% 61.87% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2216 38.13% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5812 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6844 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6403 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5331 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5812 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5331 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 11734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5812 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12656 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12042048 # DTB read hits -system.cpu0.dtb.read_misses 5594 # DTB read misses -system.cpu0.dtb.write_hits 9609454 # DTB write hits -system.cpu0.dtb.write_misses 809 # DTB write misses -system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12196931 # DTB read hits +system.cpu0.dtb.read_misses 5939 # DTB read misses +system.cpu0.dtb.write_hits 9657394 # DTB write hits +system.cpu0.dtb.write_misses 905 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3984 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4577 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 860 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 883 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12047642 # DTB read accesses -system.cpu0.dtb.write_accesses 9610263 # DTB write accesses +system.cpu0.dtb.perms_faults 223 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12202870 # DTB read accesses +system.cpu0.dtb.write_accesses 9658299 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21651502 # DTB hits -system.cpu0.dtb.misses 6403 # DTB misses -system.cpu0.dtb.accesses 21657905 # DTB accesses +system.cpu0.dtb.hits 21854325 # DTB hits +system.cpu0.dtb.misses 6844 # DTB misses +system.cpu0.dtb.accesses 21861169 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,512 +469,506 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3203 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3203 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 686 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2517 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3203 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3203 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3203 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2349 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6519.168051 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.54% 25.54% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 662 28.18% 53.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 191 8.13% 61.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.48% 78.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.46% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 498 21.20% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2349 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1663 70.80% 70.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 686 29.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3527 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3527 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 843 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2684 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3527 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3527 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3527 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13515.230312 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11626.856178 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7003.990357 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 705 26.19% 26.19% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1285 47.73% 73.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 689 25.59% 99.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 12 0.45% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1849 68.68% 68.68% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 843 31.32% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2692 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3203 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3203 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3527 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3527 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5552 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56738612 # ITB inst hits -system.cpu0.itb.inst_misses 3203 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2692 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2692 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6219 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57466570 # ITB inst hits +system.cpu0.itb.inst_misses 3527 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2718 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56741815 # ITB inst accesses -system.cpu0.itb.hits 56738612 # DTB hits -system.cpu0.itb.misses 3203 # DTB misses -system.cpu0.itb.accesses 56741815 # DTB accesses -system.cpu0.numCycles 2910043779 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57470097 # ITB inst accesses +system.cpu0.itb.hits 57466570 # DTB hits +system.cpu0.itb.misses 3527 # DTB misses +system.cpu0.itb.accesses 57470097 # DTB accesses +system.cpu0.numCycles 2904046767 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.committedInsts 55199902 # Number of instructions committed -system.cpu0.committedOps 66610456 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58846956 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5257 # Number of float alu accesses -system.cpu0.num_func_calls 4818664 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7556613 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58846956 # number of integer instructions -system.cpu0.num_fp_insts 5257 # number of float instructions -system.cpu0.num_int_register_reads 106933232 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40497320 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3778 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240479401 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25666284 # number of times the CC registers were written -system.cpu0.num_mem_refs 22274939 # number of memory refs -system.cpu0.num_load_insts 12196843 # Number of load instructions -system.cpu0.num_store_insts 10078096 # Number of store instructions -system.cpu0.num_idle_cycles 2694635007.442764 # Number of idle cycles -system.cpu0.num_busy_cycles 215408771.557236 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074023 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925977 # Percentage of idle cycles -system.cpu0.Branches 12742817 # Number of branches fetched -system.cpu0.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45792240 67.22% 67.22% # Class of executed instruction -system.cpu0.op_class::IntMult 56099 0.08% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12196843 17.90% 85.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 10078096 14.79% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed +system.cpu0.committedInsts 55929982 # Number of instructions committed +system.cpu0.committedOps 67277087 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59477787 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5777 # Number of float alu accesses +system.cpu0.num_func_calls 4936884 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7560751 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59477787 # number of integer instructions +system.cpu0.num_fp_insts 5777 # number of float instructions +system.cpu0.num_int_register_reads 108128339 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41101378 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1294 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 243146097 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25735731 # number of times the CC registers were written +system.cpu0.num_mem_refs 22502519 # number of memory refs +system.cpu0.num_load_insts 12359077 # Number of load instructions +system.cpu0.num_store_insts 10143442 # Number of store instructions +system.cpu0.num_idle_cycles 2686489862.931067 # Number of idle cycles +system.cpu0.num_busy_cycles 217556904.068932 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074915 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925085 # Percentage of idle cycles +system.cpu0.Branches 12907844 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46271329 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 59336 0.09% 67.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4393 0.01% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::MemRead 12359077 17.95% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10143442 14.73% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68127374 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819099 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702232 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234609 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819611 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.750157 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.298558 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.403674 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084567 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914851 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu0.op_class::total 68839780 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819212 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43241766 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819724 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.751616 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.161528 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.665688 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607737 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391925 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177105423 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177105423 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11354436 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11757578 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23112014 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9226475 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9597217 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823692 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202415 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392701 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229309 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221967 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238239 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460206 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20580911 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21354795 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935706 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20771197 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21557210 # number of overall hits -system.cpu0.dcache.overall_hits::total 42328407 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199328 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200534 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399862 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149618 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 149039 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298657 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58774 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59550 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118324 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10841 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11919 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22760 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 177132709 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177132709 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11626239 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23116538 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9270780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9555063 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825843 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200211 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192673 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392884 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225024 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218448 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443472 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 232922 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227346 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20761079 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21181302 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41942381 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20961290 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21373975 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335265 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199689 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 200118 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399807 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 142721 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155928 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298649 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 56972 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61224 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118196 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10863 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11717 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22580 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 348946 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 349573 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 698519 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 407720 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 409123 # number of overall misses -system.cpu0.dcache.overall_misses::total 816843 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3302461000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3180866500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6483327500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9863039500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9227377000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19090416500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137120000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 157150000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 294270000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13165500500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 12408243500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25573744000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13165500500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 12408243500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25573744000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11553764 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11958112 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23511876 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9376093 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9746256 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19122349 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249060 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511025 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224761 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241228 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465989 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221967 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238241 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460208 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20929857 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21704368 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42634225 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21178917 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21966333 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43145250 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017252 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016770 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017007 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015957 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015292 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015618 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235983 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227320 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231542 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048233 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048842 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 342410 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 356046 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 698456 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 399382 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 417270 # number of overall misses +system.cpu0.dcache.overall_misses::total 816652 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2971524000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2998963500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5970487500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5760942000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6862631000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12623573000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 131745000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 146890000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 278635000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 166000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8732466000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9861594500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18594060500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8732466000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9861594500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18594060500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11689988 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11826357 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23516345 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9413501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9710991 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19124492 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257183 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253897 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511080 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 235887 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230165 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466052 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 232924 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227346 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21103489 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21537348 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42640837 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21360672 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21791245 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43151917 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017082 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016921 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017001 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015161 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016057 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015616 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221523 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.241137 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231267 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046052 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050907 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048450 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016672 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016106 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016384 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019251 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018625 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16567.973391 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15861.981011 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16213.912550 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65921.476694 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61912.499413 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63920.874113 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12648.279679 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13184.830942 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12929.261863 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37729.334911 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35495.428709 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36611.379218 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.543756 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30328.882757 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31308.028593 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 148 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016225 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016532 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016380 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018697 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019149 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018925 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14880.759581 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14985.975774 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14933.424127 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40365.061904 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44011.537376 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42268.927738 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12127.865231 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12536.485448 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12339.902569 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 83000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25502.952601 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27697.529252 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26621.663355 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21864.946342 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23633.605339 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22768.646253 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.727273 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 683901 # number of writebacks -system.cpu0.dcache.writebacks::total 683901 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 477 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 439 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7004 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7232 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14236 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 477 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 477 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 916 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198851 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 200095 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 398946 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149618 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 149039 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298657 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57662 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58611 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116273 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3837 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4687 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8524 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 683633 # number of writebacks +system.cpu0.dcache.writebacks::total 683633 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 281 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 383 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 664 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7123 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 6928 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14051 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 281 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 665 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 281 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 384 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 665 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199408 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199735 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 399143 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142721 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155927 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298648 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 56083 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60109 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116192 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3740 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4789 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8529 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 348469 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 349134 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697603 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 406131 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 407745 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813876 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15000 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16138 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.demand_mshr_misses::cpu0.data 342129 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 355662 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697791 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 398212 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 415771 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813983 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14424 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16714 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13390 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14199 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15123 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12466 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28390 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30337 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29547 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29180 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3086715500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2967879500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6054595000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9713421500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9078338000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18791759500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 797262500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 818412000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615674500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52113500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63305500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115419000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12800137000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12046217500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24846354500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13597399500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12864629500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3048418500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3229696000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278114500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015292 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015618 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223736 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227529 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019430 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018292 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2766355500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2792156000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5558511500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5618221000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6706526000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12324747000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 723870500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 803461500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1527332000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48171500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60949500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109121000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8384576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9498682000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17883258500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9108447000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10302143500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 19410590500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2834492500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3446734000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281226500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2834492500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3446734000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281226500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017058 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016889 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015161 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016057 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218067 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015855 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020807 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018301 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016086 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019176 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018562 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018864 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1695677 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.124123 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.966796 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.469848 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117123 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879824 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016212 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016514 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018642 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019080 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13872.841110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13979.302576 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13926.115452 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39365.061904 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43010.678074 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41268.473253 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12907.128720 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13366.742085 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13144.898100 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12880.080214 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12726.978492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.114199 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 82000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24507.061664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26707.047703 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25628.388013 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22873.361426 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24778.408066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.432296 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196512.236550 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206218.379801 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201722.220438 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95931.651267 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118119.739548 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.365896 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1697986 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.728403 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113871932 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698498 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.042724 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25838751500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 416.287276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.441127 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.813061 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997516 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117247589 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117247589 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55898438 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57956761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113855199 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55898438 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57956761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113855199 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55898438 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57956761 # number of overall hits -system.cpu0.icache.overall_hits::total 113855199 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 840174 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 856021 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1696195 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 840174 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 856021 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1696195 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 840174 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 856021 # number of overall misses -system.cpu0.icache.overall_misses::total 1696195 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11888847500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12382350500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24271198000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11888847500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12382350500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24271198000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11888847500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12382350500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24271198000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56738612 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58812782 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115551394 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56738612 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58812782 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115551394 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56738612 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58812782 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115551394 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014808 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014555 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014679 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014808 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014555 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014679 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014808 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014555 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014679 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14150.458715 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14465.007868 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.202657 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14150.458715 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14465.007868 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14309.202657 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14150.458715 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14465.007868 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14309.202657 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117268940 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117268940 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56612158 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57259774 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113871932 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56612158 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57259774 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113871932 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56612158 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57259774 # number of overall hits +system.cpu0.icache.overall_hits::total 113871932 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 854412 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 844092 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1698504 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 854412 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 844092 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1698504 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 854412 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 844092 # number of overall misses +system.cpu0.icache.overall_misses::total 1698504 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11714597500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11693316500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23407914000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11714597500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11693316500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23407914000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11714597500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11693316500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23407914000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57466570 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58103866 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115570436 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57466570 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58103866 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115570436 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57466570 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58103866 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115570436 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014868 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014527 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014868 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014527 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014868 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014527 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13710.712747 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13853.130346 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13781.488887 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13781.488887 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13710.712747 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13853.130346 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13781.488887 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1695677 # number of writebacks -system.cpu0.icache.writebacks::total 1695677 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840174 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 856021 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1696195 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 840174 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 856021 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1696195 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 840174 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 856021 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1696195 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable +system.cpu0.icache.writebacks::writebacks 1697986 # number of writebacks +system.cpu0.icache.writebacks::total 1697986 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 854412 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 844092 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698504 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 854412 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 844092 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698504 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 854412 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 844092 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698504 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11048673500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11526329500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22575003000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11048673500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11526329500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22575003000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11048673500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11526329500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22575003000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.202657 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126678.452671 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10860185500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10849224500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21709410000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10860185500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10849224500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21709410000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10860185500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10849224500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21709410000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014868 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014868 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014868 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.488887 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1000,57 +998,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6953 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2221 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4731 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6555 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6555 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1891 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4663 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6952 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7349.012526 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5859 99.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 292297068 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -4.609996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1639785500 561.00% 561.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1347488432 -461.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 292297068 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3658 62.43% 62.43% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2201 37.57% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5859 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 6554 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6554 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6554 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12314.493823 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10586.515921 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7100.180026 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4356 80.32% 80.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1063 19.60% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1582538528 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.367973 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.482254 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000207500 63.20% 63.20% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 582331028 36.80% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1582538528 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3557 65.60% 65.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1865 34.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5422 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6555 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5859 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6555 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5422 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5859 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12812 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5422 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11977 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12477429 # DTB read hits -system.cpu1.dtb.read_misses 5926 # DTB read misses -system.cpu1.dtb.write_hits 9996759 # DTB write hits -system.cpu1.dtb.write_misses 1027 # DTB write misses -system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12327133 # DTB read hits +system.cpu1.dtb.read_misses 5631 # DTB read misses +system.cpu1.dtb.write_hits 9951025 # DTB write hits +system.cpu1.dtb.write_misses 924 # DTB write misses +system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4677 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12483355 # DTB read accesses -system.cpu1.dtb.write_accesses 9997786 # DTB write accesses +system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12332764 # DTB read accesses +system.cpu1.dtb.write_accesses 9951949 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22474188 # DTB hits -system.cpu1.dtb.misses 6953 # DTB misses -system.cpu1.dtb.accesses 22481141 # DTB accesses +system.cpu1.dtb.hits 22278158 # DTB hits +system.cpu1.dtb.misses 6555 # DTB misses +system.cpu1.dtb.accesses 22284713 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1080,119 +1082,121 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3501 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3501 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 842 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2659 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3501 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3501 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3501 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7193.126612 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1956 72.44% 72.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 743 27.52% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1858 68.81% 68.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 842 31.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3197 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3197 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 694 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2503 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3197 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3197 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3197 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12629.995793 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10731.102955 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7036.590613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 768 32.31% 32.31% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1084 45.60% 77.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 512 21.54% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 12 0.50% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1683 70.80% 70.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 694 29.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2377 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3501 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3501 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3197 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3197 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6201 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58812782 # ITB inst hits -system.cpu1.itb.inst_misses 3501 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2377 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2377 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5574 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58103866 # ITB inst hits +system.cpu1.itb.inst_misses 3197 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2701 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2384 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58816283 # ITB inst accesses -system.cpu1.itb.hits 58812782 # DTB hits -system.cpu1.itb.misses 3501 # DTB misses -system.cpu1.itb.accesses 58816283 # DTB accesses -system.cpu1.numCycles 2909245944 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58107063 # ITB inst accesses +system.cpu1.itb.hits 58103866 # DTB hits +system.cpu1.itb.misses 3197 # DTB misses +system.cpu1.itb.accesses 58107063 # DTB accesses +system.cpu1.numCycles 2903713042 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 57254309 # Number of instructions committed -system.cpu1.committedOps 68973710 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61043070 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5904 # Number of float alu accesses -system.cpu1.num_func_calls 5072826 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7673629 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61043070 # number of integer instructions -system.cpu1.num_fp_insts 5904 # number of float instructions -system.cpu1.num_int_register_reads 111123439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42146017 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4671 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 249248543 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26227592 # number of times the CC registers were written -system.cpu1.num_mem_refs 23131346 # number of memory refs -system.cpu1.num_load_insts 12645224 # Number of load instructions -system.cpu1.num_store_insts 10486122 # Number of store instructions -system.cpu1.num_idle_cycles 2689856281.302534 # Number of idle cycles -system.cpu1.num_busy_cycles 219389662.697466 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles -system.cpu1.Branches 13172935 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47380499 67.13% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4490 0.01% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12645224 17.92% 85.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 10486122 14.86% 100.00% # Class of executed instruction +system.cpu1.committedInsts 56542374 # Number of instructions committed +system.cpu1.committedOps 68331078 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60434186 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5384 # Number of float alu accesses +system.cpu1.num_func_calls 4958421 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7671718 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60434186 # number of integer instructions +system.cpu1.num_fp_insts 5384 # number of float instructions +system.cpu1.num_int_register_reads 109968089 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41558580 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3965 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1422 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 246670954 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26165253 # number of times the CC registers were written +system.cpu1.num_mem_refs 22910809 # number of memory refs +system.cpu1.num_load_insts 12487681 # Number of load instructions +system.cpu1.num_store_insts 10423128 # Number of store instructions +system.cpu1.num_idle_cycles 2692724474.472886 # Number of idle cycles +system.cpu1.num_busy_cycles 210988567.527115 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072662 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927338 # Percentage of idle cycles +system.cpu1.Branches 13013850 # Number of branches fetched +system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46919270 67.13% 67.13% # Class of executed instruction +system.cpu1.op_class::IntMult 55219 0.08% 67.21% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4062 0.01% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::MemRead 12487681 17.87% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10423128 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70576858 # Class of executed instruction -system.iobus.trans_dist::ReadReq 30177 # Transaction distribution -system.iobus.trans_dist::ReadResp 30177 # Transaction distribution +system.cpu1.op_class::total 69889494 # Class of executed instruction +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1215,9 +1219,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1238,22 +1242,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 46333000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 95500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 644000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1273,56 +1277,56 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6284000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36462000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187070020 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187660851 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084263 # Cycle average of tags in use +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.079319 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313834387000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084263 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067766 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067766 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309377087000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079319 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067457 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067457 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328068 # Number of tag accesses -system.iocache.tags.data_accesses 328068 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses -system.iocache.ReadReq_misses::total 228 # number of ReadReq misses +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses -system.iocache.demand_misses::total 36452 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36452 # number of overall misses -system.iocache.overall_misses::total 36452 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4577089020 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4577089020 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4577089020 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4577089020 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses +system.iocache.demand_misses::total 36458 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36458 # number of overall misses +system.iocache.overall_misses::total 36458 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28898377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28898377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277821474 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277821474 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4306719851 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4306719851 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4306719851 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4306719851 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1331,14 +1335,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125564.825524 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125564.825524 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 123497.337607 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123497.337607 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118093.569843 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118093.569843 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118128.253086 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118128.253086 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118128.253086 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118128.253086 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1347,22 +1351,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2753072506 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2753072506 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2753072506 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2753072506 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17198377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17198377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464512228 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2464512228 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2481710605 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2481710605 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2481710605 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2481710605 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,494 +1375,520 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency -system.l2c.tags.replacements 87562 # number of replacements -system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use -system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152797 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.784741 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73497.337607 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73497.337607 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68035.341983 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68035.341983 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68070.398952 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68070.398952 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency +system.l2c.tags.replacements 88930 # number of replacements +system.l2c.tags.tagsinuse 64921.564367 # Cycle average of tags in use +system.l2c.tags.total_refs 4554585 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154189 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.538975 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50199.163746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4089.871618 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2504.674114 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5610.944787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2455.815915 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.085616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56202 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40564313 # Number of tag accesses -system.l2c.tags.data_accesses 40564313 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5816 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3489 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18690 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683901 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683901 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1664900 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1664900 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 86062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166980 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 832345 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 845838 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1678183 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 253790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257782 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511572 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5816 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3025 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 832345 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 334708 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3489 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 845838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 343844 # number of demand (read+write) hits -system.l2c.demand_hits::total 2375425 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5816 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3025 # number of overall hits -system.l2c.overall_hits::cpu0.inst 832345 # number of overall hits -system.l2c.overall_hits::cpu0.data 334708 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3489 # number of overall hits -system.l2c.overall_hits::cpu1.inst 845838 # number of overall hits -system.l2c.overall_hits::cpu1.data 343844 # number of overall hits -system.l2c.overall_hits::total 2375425 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 50439.038395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4115.597994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2621.496048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.860554 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5480.404826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2258.346213 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.769639 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062799 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.040001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.083624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.034460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990624 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65253 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6981 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56097 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995682 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40592424 # Number of tag accesses +system.l2c.tags.data_accesses 40592424 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3327 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5249 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2715 # number of ReadReq hits +system.l2c.ReadReq_hits::total 17347 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683633 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683633 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1666927 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666927 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 83399 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 82059 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165458 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 846260 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 834237 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1680497 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 253600 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258179 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511779 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3327 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 846260 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 336999 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5249 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2715 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 834237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 340238 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375081 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6056 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3327 # number of overall hits +system.l2c.overall_hits::cpu0.inst 846260 # number of overall hits +system.l2c.overall_hits::cpu0.data 336999 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5249 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2715 # number of overall hits +system.l2c.overall_hits::cpu1.inst 834237 # number of overall hits +system.l2c.overall_hits::cpu1.data 340238 # number of overall hits +system.l2c.overall_hits::total 2375081 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1389 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::total 10 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1330 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1405 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2735 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67296 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 61616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128912 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7811 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10168 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6560 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7811 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73856 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 57981 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72450 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130431 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 8141 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 9842 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 17983 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 5631 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 6454 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 12085 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 63612 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67227 # number of demand (read+write) misses -system.l2c.demand_misses::total 159070 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7811 # number of overall misses -system.l2c.overall_misses::cpu0.data 73856 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.demand_misses::cpu1.inst 9842 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78904 # number of demand (read+write) misses +system.l2c.demand_misses::total 160509 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8141 # number of overall misses +system.l2c.overall_misses::cpu0.data 63612 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10168 # number of overall misses -system.l2c.overall_misses::cpu1.data 67227 # number of overall misses -system.l2c.overall_misses::total 159070 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 530500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 398500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 133000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1062000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1012500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 780000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1792500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8529037500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 7843663000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 16372700500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1020054500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1330939500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2350994000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 872232500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 739124500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1611357000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 530500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1020054500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9401270000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 398500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1330939500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 8582787500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20336113500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 530500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1020054500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9401270000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 398500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1330939500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 8582787500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20336113500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5820 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3025 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6363 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3490 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 18698 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 683901 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 683901 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1664900 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1664900 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1404 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1361 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.inst 9842 # number of overall misses +system.l2c.overall_misses::cpu1.data 78904 # number of overall misses +system.l2c.overall_misses::total 160509 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 251000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 84000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 447000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 865500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 321500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 201500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 523000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 161000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4487898000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5568339500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 10056237500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 663327500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 794140000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1457467500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 478260000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 540016500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1018276500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 251000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 663327500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4966158000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 447000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 83500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 794140000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6108356000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12532847000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 663327500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4966158000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 447000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 83500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 794140000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6108356000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12532847000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 6059 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3328 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5254 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2716 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 17357 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 683633 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 683633 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666927 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666927 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1341 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1418 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2759 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 148214 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 147678 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295892 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 840156 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 856006 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1696162 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 260350 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 263393 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 523743 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5820 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 840156 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 408564 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6363 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3490 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 856006 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 411071 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534495 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5820 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 840156 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 408564 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6363 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3490 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 856006 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 411071 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534495 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000287 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000428 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989316 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.994122 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 141380 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 154509 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295889 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 854401 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 844079 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1698480 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 259231 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264633 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 523864 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 6059 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3328 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 854401 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 400611 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2716 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 844079 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 419142 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2535590 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 6059 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3328 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 854401 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 400611 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2716 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 844079 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 419142 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2535590 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000300 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000576 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991797 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990832 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991301 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.454046 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.417232 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.435672 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009297 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011878 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010600 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025197 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021303 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023238 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.180770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000287 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.163541 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062762 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000687 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009297 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.180770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000287 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.163541 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062762 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132625 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 132750 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 728.941685 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 576.496674 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 653.719912 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126739.144971 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127299.126850 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127006.799212 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130592.049674 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130894.915421 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 130763.335002 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132962.271341 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131727.766886 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 132393.147646 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 130592.049674 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 127291.892331 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 130894.915421 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127668.756601 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127843.801471 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 130592.049674 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 127291.892331 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 130894.915421 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127668.756601 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127843.801471 # average overall miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410108 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.468905 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.440811 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009528 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011660 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010588 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021722 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.024388 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023069 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000300 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009528 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.158787 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011660 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.188251 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.063302 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000495 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000300 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009528 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.158787 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000952 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011660 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.188251 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.063302 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89400 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 86550 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 241.729323 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 143.416370 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 191.224863 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77402.907849 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76857.688061 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 77100.056735 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 81479.855055 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80688.884373 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 81046.961019 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84933.404369 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83671.599008 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 84259.536616 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 81479.855055 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78081.895719 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 81479.855055 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 78069.515186 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80688.884373 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 77415.035993 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78081.895719 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 81183 # number of writebacks -system.l2c.writebacks::total 81183 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 82442 # number of writebacks +system.l2c.writebacks::total 82442 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 8 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1389 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1353 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1330 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1405 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2735 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67296 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 61616 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128912 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7811 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10168 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6560 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5611 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 12171 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7811 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 73856 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 57981 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 72450 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 130431 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8141 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9842 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 17983 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 5631 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6454 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 12085 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8141 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 63612 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67227 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 159070 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7811 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 73856 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9842 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 78904 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 160509 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8141 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 63612 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67227 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 159070 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15000 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16138 # number of ReadReq MSHR uncacheable +system.l2c.overall_mshr_misses::cpu1.inst 9842 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 78904 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 160509 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14424 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16714 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13390 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14199 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15123 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 12466 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28390 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30337 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 29547 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 29180 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 490500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 368500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 982000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 94515000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 92030500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 186545500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7856077500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7227503000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15083580500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 941944500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1229259500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 2171204000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 806632500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 683014500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1489647000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 490500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 941944500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 8662710000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 1229259500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7910517500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 18745413500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 490500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 941944500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 8662710000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 1229259500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7910517500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 18745413500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 643340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2860870000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3027916000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6918904000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2860870000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3027916000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6918904000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989316 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994122 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 221000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 397000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 73500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 765500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25317500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 26732000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 52049500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 141000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3908088000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4843839500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8751927500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 581917500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695720000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1277637500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421950000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 475476500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 897426500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 221000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 581917500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4330038000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 397000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 73500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 695720000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5319316000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10927757000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 581917500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4330038000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 397000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 73500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695720000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5319316000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10927757000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2654142000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3237757500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6466411500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 574512000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2654142000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3237757500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 6466411500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000368 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000576 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991797 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990832 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991301 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.454046 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417232 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.435672 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021303 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023238 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062762 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062762 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68045.356371 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68019.586105 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68032.640408 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.410108 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.440811 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010588 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021722 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024388 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023069 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.158787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.188251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063302 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.158787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.188251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063302 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76550 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19026.334520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19030.895795 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.961019 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.222610 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89827.799777 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110958.104866 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.596998 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 325066 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 134283 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70546 # Transaction distribution +system.membus.trans_dist::ReadResp 70472 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution -system.membus.trans_dist::CleanEvict 6607 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118632 # Transaction distribution +system.membus.trans_dist::CleanEvict 6722 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4502 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 127157 # Transaction distribution -system.membus.trans_dist::ReadExResp 127157 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution +system.membus.trans_dist::ReadExReq 128664 # Transaction distribution +system.membus.trans_dist::ReadExResp 128664 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30312 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 541912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 614797 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 619036 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15473916 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15637269 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390010 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 17954389 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 267453 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018325 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134123 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 262552 98.17% 98.17% # Request fanout histogram +system.membus.snoop_fanout::1 4901 1.83% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390010 # Request fanout histogram -system.membus.reqLayer0.occupancy 90443000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 267453 # Request fanout histogram +system.membus.reqLayer0.occupancy 90452000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1721000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823181865 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 831225033 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 943214000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 950845250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1187123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1901,60 +1931,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5053855 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2538047 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5058603 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38310 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 74697 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2294848 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74739 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297326 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 801289 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1695677 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 141805 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 766075 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1697986 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 142067 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295892 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295892 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696195 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523971 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5106078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581570 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7740883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217113784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96423069 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313611645 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176532 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2781330 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021292 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144357 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295889 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295889 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1698504 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 524085 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4401 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5113014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581913 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 33981 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7746863 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217409912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96413853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45252 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313893193 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 111017 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2716898 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021705 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145719 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2722109 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59221 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2657927 97.83% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 58971 2.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2781330 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4961202000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2716898 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4965685500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553314500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2556778000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275768500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275944496 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11880000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11911000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22657000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22668000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 422618199..5987f38c7 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112151729000 # Number of ticks simulated final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1369712 # Simulator instruction rate (inst/s) -host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34999130987 # Simulator tick rate (ticks/s) -host_mem_usage 614748 # Number of bytes of host memory used -host_seconds 146.07 # Real time elapsed on the host +host_inst_rate 1314225 # Simulator instruction rate (inst/s) +host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33581335470 # Simulator tick rate (ticks/s) +host_mem_usage 609616 # Number of bytes of host memory used +host_seconds 152.23 # Real time elapsed on the host sim_insts 200067055 # Number of instructions simulated sim_ops 409581065 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 94a3f35b5..303fd9f5f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu sim_ticks 5194946000500 # Number of ticks simulated final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 910377 # Simulator instruction rate (inst/s) -host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36822413305 # Simulator tick rate (ticks/s) -host_mem_usage 616280 # Number of bytes of host memory used -host_seconds 141.08 # Real time elapsed on the host +host_inst_rate 930999 # Simulator instruction rate (inst/s) +host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37656529565 # Simulator tick rate (ticks/s) +host_mem_usage 609616 # Number of bytes of host memory used +host_seconds 137.96 # Real time elapsed on the host sim_insts 128436892 # Number of instructions simulated sim_ops 247560077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts |